u64 create_pbc(struct hfi1_pportdata *ppd, u64, int, u32, u32);
/* firmware.c */
+#define SBUS_MASTER_BROADCAST 0xfd
#define NUM_PCIE_SERDES 16 /* number of PCIe serdes on the SBus */
extern const u8 pcie_serdes_broadcast[];
extern const u8 pcie_pcs_addrs[2][NUM_PCIE_SERDES];
return 0;
}
-/* SBus Master broadcast address */
-#define SBUS_MASTER_BROADCAST 0xfd
-
/*
* Write the SBus request register
*
ret = load_sbus_firmware(dd, &fw_sbus);
if (ret)
goto clear;
+ fw_sbus_load = 0;
}
if (fw_fabric_serdes_load) {
__func__);
}
+retry:
+ if (therm) {
+ /* toggle SPICO_ENABLE to get back to the state
+ just after the firmware load */
+ sbus_request(dd, SBUS_MASTER_BROADCAST, 0x01,
+ WRITE_SBUS_RECEIVER, 0x00000040);
+ sbus_request(dd, SBUS_MASTER_BROADCAST, 0x01,
+ WRITE_SBUS_RECEIVER, 0x00000140);
+ dd_dev_info(dd, "%s: toggle SPICO_ENABLE to reset the bus\n",
+ __func__);
+ }
+
/* step 3: download SBus Master firmware */
/* step 4: download PCIe Gen3 SerDes firmware */
-retry:
dd_dev_info(dd, "%s: downloading firmware\n", __func__);
ret = load_pcie_firmware(dd);
if (ret)