#endif
#include <mach/hardware.h>
-#include <mach/platform.h>
/*
* USB device configuration structure
#define UDCA_BUFF_SIZE (128)
-/* TODO: When the clock framework is introduced in LPC32xx, IO_ADDRESS will
- * be replaced with an inremap()ed pointer
- * */
-#define USB_CTRL IO_ADDRESS(LPC32XX_CLK_PM_BASE + 0x64)
-
-/* USB_CTRL bit defines */
-#define USB_SLAVE_HCLK_EN (1 << 24)
-#define USB_HOST_NEED_CLK_EN (1 << 21)
-#define USB_DEV_NEED_CLK_EN (1 << 22)
-
/**********************************************************************
* USB device controller register offsets
**********************************************************************/
i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
ISP1301_I2C_INTERRUPT_RISING, INT_VBUS_VLD);
- /* Enable usb_need_clk clock after transceiver is initialized */
- writel((readl(USB_CTRL) | USB_DEV_NEED_CLK_EN), USB_CTRL);
-
dev_info(udc->dev, "ISP1301 Vendor ID : 0x%04x\n",
i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x00));
dev_info(udc->dev, "ISP1301 Product ID : 0x%04x\n",
/* 48MHz PLL up */
clk_prepare_enable(udc->usb_pll_clk);
-
- /* Enable the USB device clock */
- writel(readl(USB_CTRL) | USB_DEV_NEED_CLK_EN,
- USB_CTRL);
-
clk_prepare_enable(udc->usb_otg_clk);
} else {
if (!udc->clocked)
/* 48MHz PLL dpwn */
clk_disable_unprepare(udc->usb_pll_clk);
-
- /* Disable the USB device clock */
- writel(readl(USB_CTRL) & ~USB_DEV_NEED_CLK_EN,
- USB_CTRL);
-
clk_disable_unprepare(udc->usb_otg_clk);
}
}
goto io_map_fail;
}
- /* Enable AHB slave USB clock, needed for further USB clock control */
- writel(USB_SLAVE_HCLK_EN | (1 << 19), USB_CTRL);
-
/* Get required clocks */
udc->usb_pll_clk = clk_get(&pdev->dev, "ck_pll5");
if (IS_ERR(udc->usb_pll_clk)) {
goto pll_set_fail;
}
- writel(readl(USB_CTRL) | USB_DEV_NEED_CLK_EN, USB_CTRL);
-
/* Enable USB device clock */
retval = clk_prepare_enable(udc->usb_slv_clk);
if (retval < 0) {