size = <0x0 0x04000000>;
alignment = <0x0 0x400000>;
};
+ galcore_reserved:linux,galcore {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x4000000>;
+ alignment = <0x0 0x400000>;
+ linux,contiguous-region;
+ };
+ };
+ galcore {
+ status = "okay";
+ memory-region = <&galcore_reserved>;
};
-
cvbsout {
compatible = "amlogic, cvbsout-g12b";
dev_name = "cvbsout";
};
};
+ galcore {
+ compatible = "amlogic, galcore";
+ dev_name = "galcore";
+ status = "disabled";
+ clocks = <&clkc CLKID_VNANOQ_AXI_CLK_COMP>,
+ <&clkc CLKID_VNANOQ_CORE_CLK_COMP>;
+ clock-names = "cts_vipnanoq_axi_clk_composite",
+ "cts_vipnanoq_core_clk_composite";
+ interrupts = <0 147 1>;
+ interrupt-names = "galcore";
+ reg = <0x0 0xff100000 0x0 0x800>;
+ };
+
aocec: aocec {
compatible = "amlogic, aocec-g12a";
device_name = "aocec";
},
};
-static struct clk_mux cts_vipnanoq_mux = {
- .reg = (void *)HHI_VIPNANOQ_CLK_CNTL,
- .mask = 0x1,
- .shift = 31,
- .lock = &clk_lock,
- .flags = CLK_PARENT_ALTERNATE,
- .hw.init = &(struct clk_init_data){
- .name = "cts_vipnanoq_mux",
- .ops = &meson_clk_mux_ops,
- .parent_names = (const char *[]) {
- "cts_vipnanoq_core_clk_composite",
- "cts_vipnanoq_axi_clk_composite"
- },
- .num_parents = 2,
- .flags = CLK_GET_RATE_NOCACHE,
- },
-};
+
static struct clk_mux cts_mipi_isp_clk_mux = {
.reg = (void *)HHI_MIPI_ISP_CLK_CNTL,
+ (u64)(cts_vipnanoq_axi_clk_gate.reg);
cts_vipnanoq_axi_clk_div.reg = clk_base
+ (u64)(cts_vipnanoq_axi_clk_div.reg);
- cts_vipnanoq_mux.reg = clk_base
- + (u64)(cts_vipnanoq_mux.reg);
+
cts_mipi_isp_clk_mux.reg = clk_base
+ (u64)(cts_mipi_isp_clk_mux.reg);
panic("%s: %d register cts_vipnanoq_axi_clk_composite error\n",
__func__, __LINE__);
- clks[CLKID_VNANOQ_MUX] = clk_register(NULL,
- &cts_vipnanoq_mux.hw);
- if (IS_ERR(clks[CLKID_VNANOQ_MUX]))
- panic("%s: %d clk_register %s error\n",
- __func__, __LINE__, cts_vipnanoq_mux.hw.init->name);
+
clks[CLKID_MIPI_ISP_CLK_COMP] = clk_register_composite(NULL,
"cts_mipi_isp_clk_composite",