G12B: NANOQ: nanoq dts and clock tree modify
authorxingwei.zhou <xingwei.zhou@amlogic.com>
Tue, 5 Jun 2018 08:15:44 +0000 (16:15 +0800)
committerYixun Lan <yixun.lan@amlogic.com>
Fri, 29 Jun 2018 07:30:50 +0000 (00:30 -0700)
PD#165090: NANOQ: modify a311d platform dts and add nanoq clock tree

Change-Id: I62419ade33c2e10a03d12f1fe26f7f54a44364a4
Signed-off-by: xingwei.zhou <xingwei.zhou@amlogic.com>
arch/arm64/boot/dts/amlogic/g12b_a311d_skt.dts
arch/arm64/boot/dts/amlogic/mesong12b.dtsi
drivers/amlogic/clk/g12b/g12b.c

index 73f704ba2f2c5f83355bc064b9d8e6866a5adbd5..4d3037c8f634fbcc4142015b13978e5fd9bea6ff 100644 (file)
                        size = <0x0 0x04000000>;
                        alignment = <0x0 0x400000>;
                };
+               galcore_reserved:linux,galcore {
+                       compatible = "shared-dma-pool";
+                       reusable;
+                       size = <0x0 0x4000000>;
+                       alignment = <0x0 0x400000>;
+                       linux,contiguous-region;
+               };
+       };
+       galcore {
+               status = "okay";
+               memory-region = <&galcore_reserved>;
        };
-
        cvbsout {
                compatible = "amlogic, cvbsout-g12b";
                dev_name = "cvbsout";
index 1f679f105aa46d5049e3522fce7ec3f0491d8833..7e7bc3a0de641a182200a61011c0e51a84fa2799 100644 (file)
                };
        };
 
+       galcore {
+               compatible = "amlogic, galcore";
+               dev_name = "galcore";
+               status = "disabled";
+               clocks = <&clkc CLKID_VNANOQ_AXI_CLK_COMP>,
+                       <&clkc CLKID_VNANOQ_CORE_CLK_COMP>;
+               clock-names = "cts_vipnanoq_axi_clk_composite",
+                       "cts_vipnanoq_core_clk_composite";
+               interrupts = <0 147 1>;
+               interrupt-names = "galcore";
+               reg = <0x0 0xff100000 0x0 0x800>;
+       };
+
        aocec: aocec {
                compatible = "amlogic, aocec-g12a";
                device_name = "aocec";
index 1667179743cf7330e61b986709ee8cdcd89d1a16..9ca993f49e127778464b18ad1a5d53e5e805790f 100644 (file)
@@ -292,23 +292,7 @@ static struct clk_gate cts_vipnanoq_axi_clk_gate = {
        },
 };
 
-static struct clk_mux cts_vipnanoq_mux = {
-       .reg = (void *)HHI_VIPNANOQ_CLK_CNTL,
-       .mask = 0x1,
-       .shift = 31,
-       .lock = &clk_lock,
-       .flags = CLK_PARENT_ALTERNATE,
-       .hw.init = &(struct clk_init_data){
-               .name = "cts_vipnanoq_mux",
-               .ops = &meson_clk_mux_ops,
-               .parent_names = (const char *[]) {
-                       "cts_vipnanoq_core_clk_composite",
-                       "cts_vipnanoq_axi_clk_composite"
-               },
-               .num_parents = 2,
-               .flags = CLK_GET_RATE_NOCACHE,
-       },
-};
+
 
 static struct clk_mux cts_mipi_isp_clk_mux = {
        .reg = (void *)HHI_MIPI_ISP_CLK_CNTL,
@@ -524,8 +508,7 @@ static void __init g12b_clkc_init(struct device_node *np)
                + (u64)(cts_vipnanoq_axi_clk_gate.reg);
        cts_vipnanoq_axi_clk_div.reg = clk_base
                + (u64)(cts_vipnanoq_axi_clk_div.reg);
-       cts_vipnanoq_mux.reg = clk_base
-               + (u64)(cts_vipnanoq_mux.reg);
+
 
        cts_mipi_isp_clk_mux.reg = clk_base
                + (u64)(cts_mipi_isp_clk_mux.reg);
@@ -641,11 +624,7 @@ static void __init g12b_clkc_init(struct device_node *np)
                panic("%s: %d register cts_vipnanoq_axi_clk_composite error\n",
                        __func__, __LINE__);
 
-       clks[CLKID_VNANOQ_MUX] = clk_register(NULL,
-               &cts_vipnanoq_mux.hw);
-       if (IS_ERR(clks[CLKID_VNANOQ_MUX]))
-               panic("%s: %d clk_register %s error\n",
-                       __func__, __LINE__, cts_vipnanoq_mux.hw.init->name);
+
 
        clks[CLKID_MIPI_ISP_CLK_COMP] = clk_register_composite(NULL,
                "cts_mipi_isp_clk_composite",