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ASoC: TWL4030: Modify codec default settings
authorPeter Ujfalusi <peter.ujfalusi@nokia.com>
Thu, 28 Jan 2010 13:57:04 +0000 (15:57 +0200)
committerMark Brown <broonie@opensource.wolfsonmicro.com>
Thu, 28 Jan 2010 14:33:10 +0000 (14:33 +0000)
Change the legacy default register configuration, which left some
internal components on.
Now we have either DAPM, or other ways to control these bits,
so there is no need to enable them by default.

The affected parts:
Disable ADCL and ADCR
Disable ARXL2 and ARXR2 analog PGA (playback)
Disable APLL by default

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
sound/soc/codecs/twl4030.c patch | blob | blame | history

diff --git a/sound/soc/codecs/twl4030.c b/sound/soc/codecs/twl4030.c
index 74f0d65f0784dd06770c101231a3c96436d783a3..e0106a5fd40b5c2c3766abbb614223cea538d4f0 100644 (file)
--- a/sound/soc/codecs/twl4030.c
+++ b/sound/soc/codecs/twl4030.c
@@ -64,12 +64,12 @@ static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
        0x00, /* REG_VRXPGA             (0x14)  */
        0x00, /* REG_VSTPGA             (0x15)  */
        0x00, /* REG_VRX2ARXPGA         (0x16)  */
-       0x0c, /* REG_AVDAC_CTL          (0x17)  */
+       0x00, /* REG_AVDAC_CTL          (0x17)  */
        0x00, /* REG_ARX2VTXPGA         (0x18)  */
        0x00, /* REG_ARXL1_APGA_CTL     (0x19)  */
        0x00, /* REG_ARXR1_APGA_CTL     (0x1A)  */
-       0x4b, /* REG_ARXL2_APGA_CTL     (0x1B)  */
-       0x4b, /* REG_ARXR2_APGA_CTL     (0x1C)  */
+       0x4a, /* REG_ARXL2_APGA_CTL     (0x1B)  */
+       0x4a, /* REG_ARXR2_APGA_CTL     (0x1C)  */
        0x00, /* REG_ATX2ARXPGA         (0x1D)  */
        0x00, /* REG_BT_IF              (0x1E)  */
        0x00, /* REG_BTPGA              (0x1F)  */
@@ -99,7 +99,7 @@ static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
        0x00, /* REG_I2S_RX_SCRAMBLE_H  (0x37)  */
        0x00, /* REG_I2S_RX_SCRAMBLE_M  (0x38)  */
        0x00, /* REG_I2S_RX_SCRAMBLE_L  (0x39)  */
-       0x16, /* REG_APLL_CTL           (0x3A)  */
+       0x06, /* REG_APLL_CTL           (0x3A)  */
        0x00, /* REG_DTMF_CTL           (0x3B)  */
        0x00, /* REG_DTMF_PGA_CTL2      (0x3C)  */
        0x00, /* REG_DTMF_PGA_CTL1      (0x3D)  */