kvm: x86: CPUID.01H:EDX.APIC[bit 9] should mirror IA32_APIC_BASE[11]
authorJim Mattson <jmattson@google.com>
Wed, 9 Nov 2016 17:50:11 +0000 (09:50 -0800)
committerRadim Krčmář <rkrcmar@redhat.com>
Tue, 22 Nov 2016 13:51:55 +0000 (14:51 +0100)
From the Intel SDM, volume 3, section 10.4.3, "Enabling or Disabling the
Local APIC,"

  When IA32_APIC_BASE[11] is 0, the processor is functionally equivalent
  to an IA-32 processor without an on-chip APIC. The CPUID feature flag
  for the APIC (see Section 10.4.2, "Presence of the Local APIC") is
  also set to 0.

Signed-off-by: Jim Mattson <jmattson@google.com>
[Changed subject tag from nVMX to x86.]
Signed-off-by: Radim Krčmář <rkrcmar@redhat.com>
arch/x86/kvm/cpuid.c
arch/x86/kvm/lapic.c

index a982fd80bcebd5858d89b28b519d0ab47f266247..25f0f15fab1a5de049e881fcfe3e664c394f1bf8 100644 (file)
@@ -87,6 +87,10 @@ int kvm_update_cpuid(struct kvm_vcpu *vcpu)
                        best->ecx |= F(OSXSAVE);
        }
 
+       best->edx &= ~F(APIC);
+       if (vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE)
+               best->edx |= F(APIC);
+
        if (apic) {
                if (best->ecx & F(TSC_DEADLINE_TIMER))
                        apic->lapic_timer.timer_mode_mask = 3 << 17;
index 890f218ddd7a26f28b7692440c981f3da6d7cbfc..09edd32b8e42b8906038899cb0e15951b984a5a0 100644 (file)
@@ -1806,14 +1806,17 @@ void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
        u64 old_value = vcpu->arch.apic_base;
        struct kvm_lapic *apic = vcpu->arch.apic;
 
-       if (!apic) {
+       if (!apic)
                value |= MSR_IA32_APICBASE_BSP;
-               vcpu->arch.apic_base = value;
-               return;
-       }
 
        vcpu->arch.apic_base = value;
 
+       if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE)
+               kvm_update_cpuid(vcpu);
+
+       if (!apic)
+               return;
+
        /* update jump label if enable bit changes */
        if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
                if (value & MSR_IA32_APICBASE_ENABLE) {