[MIPS] Use correct dma flushing in dma_cache_sync()

Not cache coherent R10k systems (like IP28) need to do real cache
invalidates in dma_cache_sync().

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index 810535dd091be1f1aaff24c6403f0686b8b01d63..ae39dd88b9aa0eb97cb63b4c56bbe41c1811ad94 100644 (file)
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
@@ -383,7 +383,7 @@ void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
        BUG_ON(direction == DMA_NONE);
 
        if (!plat_device_is_coherent(dev))
-               dma_cache_wback_inv((unsigned long)vaddr, size);
+               __dma_sync((unsigned long)vaddr, size, direction);
 }
 
 EXPORT_SYMBOL(dma_cache_sync);