drm/i915: Don't clobber CHICKEN_PIPESL_1 on BDW

Misplaced parens cause us to totally clobber the CHICKEN_PIPESL_1
registers with 0xffffffff. Move the parens to the correct place
to avoid this.

In particular this caused bit 30 of said registers to be set, which
caused the sprite CSC to produce incorrect results.

Cc: stable@vger.kernel.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=72220
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8df1826a6015f6b5c402572fc746aedfae7914e1..2cc9de7899b12dbad1db537de6fce303d1f77a80 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4839,8 +4839,8 @@ static void gen8_init_clock_gating(struct drm_device *dev)
        /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
        for_each_pipe(pipe) {
                I915_WRITE(CHICKEN_PIPESL_1(pipe),
-                          I915_READ(CHICKEN_PIPESL_1(pipe) |
-                                    DPRS_MASK_VBLANK_SRD));
+                          I915_READ(CHICKEN_PIPESL_1(pipe)) |
+                          DPRS_MASK_VBLANK_SRD);
        }
 
        /* Use Force Non-Coherent whenever executing a 3D context. This is a