qed: Add infrastructure for PTP support
authorSudarsana Reddy Kalluru <sudarsana.Kalluru@cavium.com>
Wed, 15 Feb 2017 08:24:10 +0000 (10:24 +0200)
committerDavid S. Miller <davem@davemloft.net>
Wed, 15 Feb 2017 17:42:52 +0000 (12:42 -0500)
The patch adds the required qed interfaces for configuring/reading
the PTP clock on the adapter.

Signed-off-by: Sudarsana Reddy Kalluru <Sudarsana.Kalluru@cavium.com>
Signed-off-by: Yuval Mintz <Yuval.Mintz@cavium.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/qlogic/qed/Makefile
drivers/net/ethernet/qlogic/qed/qed.h
drivers/net/ethernet/qlogic/qed/qed_l2.c
drivers/net/ethernet/qlogic/qed/qed_l2.h
drivers/net/ethernet/qlogic/qed/qed_main.c
drivers/net/ethernet/qlogic/qed/qed_ptp.c [new file with mode: 0644]
drivers/net/ethernet/qlogic/qed/qed_ptp.h [new file with mode: 0644]
drivers/net/ethernet/qlogic/qed/qed_reg_addr.h
include/linux/qed/qed_eth_if.h

index 729e43768e99d48ca57561df3233bb9d3a33b5df..1a7300f72cab43d11ae73008d033d17564f1b25a 100644 (file)
@@ -2,7 +2,7 @@ obj-$(CONFIG_QED) := qed.o
 
 qed-y := qed_cxt.o qed_dev.o qed_hw.o qed_init_fw_funcs.o qed_init_ops.o \
         qed_int.o qed_main.o qed_mcp.o qed_sp_commands.o qed_spq.o qed_l2.o \
-        qed_selftest.o qed_dcbx.o qed_debug.o
+        qed_selftest.o qed_dcbx.o qed_debug.o qed_ptp.o
 qed-$(CONFIG_QED_SRIOV) += qed_sriov.o qed_vf.o
 qed-$(CONFIG_QED_LL2) += qed_ll2.o
 qed-$(CONFIG_QED_RDMA) += qed_roce.o
index 1f61cf3209e87285242511c5b667ff1742e1e790..6557f94b92ed9f33189528b56a168a997ffb7c19 100644 (file)
@@ -456,6 +456,8 @@ struct qed_hwfn {
        u8 dcbx_no_edpm;
        u8 db_bar_no_edpm;
 
+       /* p_ptp_ptt is valid for leading HWFN only */
+       struct qed_ptt *p_ptp_ptt;
        struct qed_simd_fp_handler      simd_proto_handler[64];
 
 #ifdef CONFIG_QED_SRIOV
index 7520eb34ad007f4e81cd6c653fb339c9d4bf6a61..df932be5a4e5aa1e47b16530d51a5dcf78f15706 100644 (file)
@@ -214,6 +214,7 @@ int qed_sp_eth_vport_start(struct qed_hwfn *p_hwfn,
        p_ramrod->vport_id      = abs_vport_id;
 
        p_ramrod->mtu                   = cpu_to_le16(p_params->mtu);
+       p_ramrod->handle_ptp_pkts       = p_params->handle_ptp_pkts;
        p_ramrod->inner_vlan_removal_en = p_params->remove_inner_vlan;
        p_ramrod->drop_ttl0_en          = p_params->drop_ttl0;
        p_ramrod->untagged              = p_params->only_untagged;
@@ -1886,6 +1887,7 @@ static int qed_start_vport(struct qed_dev *cdev,
                start.drop_ttl0 = params->drop_ttl0;
                start.opaque_fid = p_hwfn->hw_info.opaque_fid;
                start.concrete_fid = p_hwfn->hw_info.concrete_fid;
+               start.handle_ptp_pkts = params->handle_ptp_pkts;
                start.vport_id = params->vport_id;
                start.max_buffers_per_cqe = 16;
                start.mtu = params->mtu;
@@ -2328,6 +2330,8 @@ extern const struct qed_iov_hv_ops qed_iov_ops_pass;
 extern const struct qed_eth_dcbnl_ops qed_dcbnl_ops_pass;
 #endif
 
+extern const struct qed_eth_ptp_ops qed_ptp_ops_pass;
+
 static const struct qed_eth_ops qed_eth_ops_pass = {
        .common = &qed_common_ops_pass,
 #ifdef CONFIG_QED_SRIOV
@@ -2336,6 +2340,7 @@ static const struct qed_eth_ops qed_eth_ops_pass = {
 #ifdef CONFIG_DCB
        .dcb = &qed_dcbnl_ops_pass,
 #endif
+       .ptp = &qed_ptp_ops_pass,
        .fill_dev_info = &qed_fill_eth_dev_info,
        .register_ops = &qed_register_eth_ops,
        .check_mac = &qed_check_mac,
index 93cb932ef6637edb6d28a3af4bdbbbfcc135a882..e763abd334f64e08d3df948d6b78e7993f6ca251 100644 (file)
@@ -156,6 +156,7 @@ struct qed_sp_vport_start_params {
        enum qed_tpa_mode tpa_mode;
        bool remove_inner_vlan;
        bool tx_switching;
+       bool handle_ptp_pkts;
        bool only_untagged;
        bool drop_ttl0;
        u8 max_buffers_per_cqe;
index 93eee83ccdc3ee7164bafebece4d5ce18d7e6526..592e104687a7e550859204220e7c068dcfc0fa99 100644 (file)
@@ -902,6 +902,7 @@ static int qed_slowpath_start(struct qed_dev *cdev,
        struct qed_mcp_drv_version drv_version;
        const u8 *data = NULL;
        struct qed_hwfn *hwfn;
+       struct qed_ptt *p_ptt;
        int rc = -EINVAL;
 
        if (qed_iov_wq_start(cdev))
@@ -916,6 +917,14 @@ static int qed_slowpath_start(struct qed_dev *cdev,
                                  QED_FW_FILE_NAME);
                        goto err;
                }
+
+               p_ptt = qed_ptt_acquire(QED_LEADING_HWFN(cdev));
+               if (p_ptt) {
+                       QED_LEADING_HWFN(cdev)->p_ptp_ptt = p_ptt;
+               } else {
+                       DP_NOTICE(cdev, "Failed to acquire PTT for PTP\n");
+                       goto err;
+               }
        }
 
        cdev->rx_coalesce_usecs = QED_DEFAULT_RX_USECS;
@@ -1003,6 +1012,10 @@ err:
        if (IS_PF(cdev))
                release_firmware(cdev->firmware);
 
+       if (IS_PF(cdev) && QED_LEADING_HWFN(cdev)->p_ptp_ptt)
+               qed_ptt_release(QED_LEADING_HWFN(cdev),
+                               QED_LEADING_HWFN(cdev)->p_ptp_ptt);
+
        qed_iov_wq_stop(cdev, false);
 
        return rc;
@@ -1016,6 +1029,8 @@ static int qed_slowpath_stop(struct qed_dev *cdev)
        qed_ll2_dealloc_if(cdev);
 
        if (IS_PF(cdev)) {
+               qed_ptt_release(QED_LEADING_HWFN(cdev),
+                               QED_LEADING_HWFN(cdev)->p_ptp_ptt);
                qed_free_stream_mem(cdev);
                if (IS_QED_ETH_IF(cdev))
                        qed_sriov_disable(cdev, true);
diff --git a/drivers/net/ethernet/qlogic/qed/qed_ptp.c b/drivers/net/ethernet/qlogic/qed/qed_ptp.c
new file mode 100644 (file)
index 0000000..d27aa85
--- /dev/null
@@ -0,0 +1,323 @@
+/* QLogic qed NIC Driver
+ * Copyright (c) 2015-2017  QLogic Corporation
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and /or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#include <linux/types.h>
+#include "qed.h"
+#include "qed_dev_api.h"
+#include "qed_hw.h"
+#include "qed_l2.h"
+#include "qed_ptp.h"
+#include "qed_reg_addr.h"
+
+/* 16 nano second time quantas to wait before making a Drift adjustment */
+#define QED_DRIFT_CNTR_TIME_QUANTA_SHIFT       0
+/* Nano seconds to add/subtract when making a Drift adjustment */
+#define QED_DRIFT_CNTR_ADJUSTMENT_SHIFT                28
+/* Add/subtract the Adjustment_Value when making a Drift adjustment */
+#define QED_DRIFT_CNTR_DIRECTION_SHIFT         31
+#define QED_TIMESTAMP_MASK                     BIT(16)
+
+/* Read Rx timestamp */
+static int qed_ptp_hw_read_rx_ts(struct qed_dev *cdev, u64 *timestamp)
+{
+       struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
+       struct qed_ptt *p_ptt = p_hwfn->p_ptp_ptt;
+       u32 val;
+
+       *timestamp = 0;
+       val = qed_rd(p_hwfn, p_ptt, NIG_REG_LLH_PTP_HOST_BUF_SEQID);
+       if (!(val & QED_TIMESTAMP_MASK)) {
+               DP_INFO(p_hwfn, "Invalid Rx timestamp, buf_seqid = %d\n", val);
+               return -EINVAL;
+       }
+
+       val = qed_rd(p_hwfn, p_ptt, NIG_REG_LLH_PTP_HOST_BUF_TS_LSB);
+       *timestamp = qed_rd(p_hwfn, p_ptt, NIG_REG_LLH_PTP_HOST_BUF_TS_MSB);
+       *timestamp <<= 32;
+       *timestamp |= val;
+
+       /* Reset timestamp register to allow new timestamp */
+       qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_HOST_BUF_SEQID,
+              QED_TIMESTAMP_MASK);
+
+       return 0;
+}
+
+/* Read Tx timestamp */
+static int qed_ptp_hw_read_tx_ts(struct qed_dev *cdev, u64 *timestamp)
+{
+       struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
+       struct qed_ptt *p_ptt = p_hwfn->p_ptp_ptt;
+       u32 val;
+
+       *timestamp = 0;
+       val = qed_rd(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_BUF_SEQID);
+       if (!(val & QED_TIMESTAMP_MASK)) {
+               DP_INFO(p_hwfn, "Invalid Tx timestamp, buf_seqid = %d\n", val);
+               return -EINVAL;
+       }
+
+       val = qed_rd(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_BUF_TS_LSB);
+       *timestamp = qed_rd(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_BUF_TS_MSB);
+       *timestamp <<= 32;
+       *timestamp |= val;
+
+       /* Reset timestamp register to allow new timestamp */
+       qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_BUF_SEQID, QED_TIMESTAMP_MASK);
+
+       return 0;
+}
+
+/* Read Phy Hardware Clock */
+static int qed_ptp_hw_read_cc(struct qed_dev *cdev, u64 *phc_cycles)
+{
+       struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
+       struct qed_ptt *p_ptt = p_hwfn->p_ptp_ptt;
+       u32 temp = 0;
+
+       temp = qed_rd(p_hwfn, p_ptt, NIG_REG_TSGEN_SYNC_TIME_LSB);
+       *phc_cycles = qed_rd(p_hwfn, p_ptt, NIG_REG_TSGEN_SYNC_TIME_MSB);
+       *phc_cycles <<= 32;
+       *phc_cycles |= temp;
+
+       return 0;
+}
+
+/* Filter PTP protocol packets that need to be timestamped */
+static int qed_ptp_hw_cfg_rx_filters(struct qed_dev *cdev,
+                                    enum qed_ptp_filter_type type)
+{
+       struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
+       struct qed_ptt *p_ptt = p_hwfn->p_ptp_ptt;
+       u32 rule_mask, parm_mask;
+
+       switch (type) {
+       case QED_PTP_FILTER_L2_IPV4_IPV6:
+               parm_mask = 0x6AA;
+               rule_mask = 0x3EEE;
+               break;
+       case QED_PTP_FILTER_L2:
+               parm_mask = 0x6BF;
+               rule_mask = 0x3EFF;
+               break;
+       case QED_PTP_FILTER_IPV4_IPV6:
+               parm_mask = 0x7EA;
+               rule_mask = 0x3FFE;
+               break;
+       case QED_PTP_FILTER_IPV4:
+               parm_mask = 0x7EE;
+               rule_mask = 0x3FFE;
+               break;
+       default:
+               DP_INFO(p_hwfn, "Invalid PTP filter type %d\n", type);
+               return -EINVAL;
+       }
+
+       qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_PARAM_MASK, parm_mask);
+       qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_RULE_MASK, rule_mask);
+
+       qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_TO_HOST, 0x1);
+
+       /* Reset possibly old timestamps */
+       qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_HOST_BUF_SEQID,
+              QED_TIMESTAMP_MASK);
+
+       return 0;
+}
+
+/* Adjust the HW clock by a rate given in parts-per-billion (ppb) units.
+ * FW/HW accepts the adjustment value in terms of 3 parameters:
+ *   Drift period - adjustment happens once in certain number of nano seconds.
+ *   Drift value - time is adjusted by a certain value, for example by 5 ns.
+ *   Drift direction - add or subtract the adjustment value.
+ * The routine translates ppb into the adjustment triplet in an optimal manner.
+ */
+static int qed_ptp_hw_adjfreq(struct qed_dev *cdev, s32 ppb)
+{
+       s64 best_val = 0, val, best_period = 0, period, approx_dev, dif, dif2;
+       struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
+       struct qed_ptt *p_ptt = p_hwfn->p_ptp_ptt;
+       u32 drift_ctr_cfg = 0, drift_state;
+       int drift_dir = 1;
+
+       if (ppb < 0) {
+               ppb = -ppb;
+               drift_dir = 0;
+       }
+
+       if (ppb > 1) {
+               s64 best_dif = ppb, best_approx_dev = 1;
+
+               /* Adjustment value is up to +/-7ns, find an optimal value in
+                * this range.
+                */
+               for (val = 7; val > 0; val--) {
+                       period = div_s64(val * 1000000000, ppb);
+                       period -= 8;
+                       period >>= 4;
+                       if (period < 1)
+                               period = 1;
+                       if (period > 0xFFFFFFE)
+                               period = 0xFFFFFFE;
+
+                       /* Check both rounding ends for approximate error */
+                       approx_dev = period * 16 + 8;
+                       dif = ppb * approx_dev - val * 1000000000;
+                       dif2 = dif + 16 * ppb;
+
+                       if (dif < 0)
+                               dif = -dif;
+                       if (dif2 < 0)
+                               dif2 = -dif2;
+
+                       /* Determine which end gives better approximation */
+                       if (dif * (approx_dev + 16) > dif2 * approx_dev) {
+                               period++;
+                               approx_dev += 16;
+                               dif = dif2;
+                       }
+
+                       /* Track best approximation found so far */
+                       if (best_dif * approx_dev > dif * best_approx_dev) {
+                               best_dif = dif;
+                               best_val = val;
+                               best_period = period;
+                               best_approx_dev = approx_dev;
+                       }
+               }
+       } else if (ppb == 1) {
+               /* This is a special case as its the only value which wouldn't
+                * fit in a s64 variable. In order to prevent castings simple
+                * handle it seperately.
+                */
+               best_val = 4;
+               best_period = 0xee6b27f;
+       } else {
+               best_val = 0;
+               best_period = 0xFFFFFFF;
+       }
+
+       drift_ctr_cfg = (best_period << QED_DRIFT_CNTR_TIME_QUANTA_SHIFT) |
+                       (((int)best_val) << QED_DRIFT_CNTR_ADJUSTMENT_SHIFT) |
+                       (((int)drift_dir) << QED_DRIFT_CNTR_DIRECTION_SHIFT);
+
+       qed_wr(p_hwfn, p_ptt, NIG_REG_TSGEN_RST_DRIFT_CNTR, 0x1);
+
+       drift_state = qed_rd(p_hwfn, p_ptt, NIG_REG_TSGEN_RST_DRIFT_CNTR);
+       if (drift_state & 1) {
+               qed_wr(p_hwfn, p_ptt, NIG_REG_TSGEN_DRIFT_CNTR_CONF,
+                      drift_ctr_cfg);
+       } else {
+               DP_INFO(p_hwfn, "Drift counter is not reset\n");
+               return -EINVAL;
+       }
+
+       qed_wr(p_hwfn, p_ptt, NIG_REG_TSGEN_RST_DRIFT_CNTR, 0x0);
+
+       return 0;
+}
+
+static int qed_ptp_hw_enable(struct qed_dev *cdev)
+{
+       struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
+       struct qed_ptt *p_ptt = p_hwfn->p_ptp_ptt;
+
+       /* Reset PTP event detection rules - will be configured in the IOCTL */
+       qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_PARAM_MASK, 0x7FF);
+       qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_RULE_MASK, 0x3FFF);
+       qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_PARAM_MASK, 0x7FF);
+       qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_RULE_MASK, 0x3FFF);
+
+       qed_wr(p_hwfn, p_ptt, NIG_REG_TX_PTP_EN, 7);
+       qed_wr(p_hwfn, p_ptt, NIG_REG_RX_PTP_EN, 7);
+
+       qed_wr(p_hwfn, p_ptt, NIG_REG_TS_OUTPUT_ENABLE_PDA, 0x1);
+
+       /* Pause free running counter */
+       qed_wr(p_hwfn, p_ptt, NIG_REG_TIMESYNC_GEN_REG_BB, 2);
+
+       qed_wr(p_hwfn, p_ptt, NIG_REG_TSGEN_FREE_CNT_VALUE_LSB, 0);
+       qed_wr(p_hwfn, p_ptt, NIG_REG_TSGEN_FREE_CNT_VALUE_MSB, 0);
+       /* Resume free running counter */
+       qed_wr(p_hwfn, p_ptt, NIG_REG_TIMESYNC_GEN_REG_BB, 4);
+
+       /* Disable drift register */
+       qed_wr(p_hwfn, p_ptt, NIG_REG_TSGEN_DRIFT_CNTR_CONF, 0x0);
+       qed_wr(p_hwfn, p_ptt, NIG_REG_TSGEN_RST_DRIFT_CNTR, 0x0);
+
+       /* Reset possibly old timestamps */
+       qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_HOST_BUF_SEQID,
+              QED_TIMESTAMP_MASK);
+       qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_BUF_SEQID, QED_TIMESTAMP_MASK);
+
+       return 0;
+}
+
+static int qed_ptp_hw_hwtstamp_tx_on(struct qed_dev *cdev)
+{
+       struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
+       struct qed_ptt *p_ptt = p_hwfn->p_ptp_ptt;
+
+       qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_PARAM_MASK, 0x6AA);
+       qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_RULE_MASK, 0x3EEE);
+
+       return 0;
+}
+
+static int qed_ptp_hw_disable(struct qed_dev *cdev)
+{
+       struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
+       struct qed_ptt *p_ptt = p_hwfn->p_ptp_ptt;
+
+       /* Reset PTP event detection rules */
+       qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_PARAM_MASK, 0x7FF);
+       qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_RULE_MASK, 0x3FFF);
+
+       qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_PARAM_MASK, 0x7FF);
+       qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_RULE_MASK, 0x3FFF);
+
+       /* Disable the PTP feature */
+       qed_wr(p_hwfn, p_ptt, NIG_REG_RX_PTP_EN, 0x0);
+       qed_wr(p_hwfn, p_ptt, NIG_REG_TX_PTP_EN, 0x0);
+
+       return 0;
+}
+
+const struct qed_eth_ptp_ops qed_ptp_ops_pass = {
+       .hwtstamp_tx_on = qed_ptp_hw_hwtstamp_tx_on,
+       .cfg_rx_filters = qed_ptp_hw_cfg_rx_filters,
+       .read_rx_ts = qed_ptp_hw_read_rx_ts,
+       .read_tx_ts = qed_ptp_hw_read_tx_ts,
+       .read_cc = qed_ptp_hw_read_cc,
+       .adjfreq = qed_ptp_hw_adjfreq,
+       .disable = qed_ptp_hw_disable,
+       .enable = qed_ptp_hw_enable,
+};
diff --git a/drivers/net/ethernet/qlogic/qed/qed_ptp.h b/drivers/net/ethernet/qlogic/qed/qed_ptp.h
new file mode 100644 (file)
index 0000000..63c666d
--- /dev/null
@@ -0,0 +1,47 @@
+/* QLogic qed NIC Driver
+ * Copyright (c) 2015-2017  QLogic Corporation
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and /or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef _QED_PTP_H
+#define _QED_PTP_H
+#include <linux/types.h>
+
+int qed_ptp_hwtstamp_tx_on(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
+int qed_ptp_cfg_rx_filters(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
+                          enum qed_ptp_filter_type type);
+int qed_ptp_read_rx_ts(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u64 *ts);
+int qed_ptp_read_tx_ts(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u64 *ts);
+int qed_ptp_read_cc(struct qed_hwfn *p_hwfn,
+                   struct qed_ptt *p_ptt, u64 *cycles);
+int qed_ptp_adjfreq(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, s32 ppb);
+int qed_ptp_disable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
+int qed_ptp_enable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
+
+#endif
index b6722c6ff7611eedc252b175bd4a14b4ec23c757..3b7edf6ff234196732f9edf9fbfe4c53202bbec1 100644 (file)
 #define DORQ_REG_PF_ICID_BIT_SHIFT_NORM        0x100448UL
 #define DORQ_REG_PF_MIN_ADDR_REG1 0x100400UL
 #define DORQ_REG_PF_DPI_BIT_SHIFT 0x100450UL
+#define NIG_REG_RX_PTP_EN 0x501900UL
+#define NIG_REG_TX_PTP_EN 0x501904UL
+#define NIG_REG_LLH_PTP_TO_HOST        0x501908UL
+#define NIG_REG_LLH_PTP_TO_MCP 0x50190cUL
+#define NIG_REG_PTP_SW_TXTSEN 0x501910UL
+#define NIG_REG_LLH_PTP_ETHERTYPE_1 0x501914UL
+#define NIG_REG_LLH_PTP_MAC_DA_2_LSB 0x501918UL
+#define NIG_REG_LLH_PTP_MAC_DA_2_MSB 0x50191cUL
+#define NIG_REG_LLH_PTP_PARAM_MASK 0x501920UL
+#define NIG_REG_LLH_PTP_RULE_MASK 0x501924UL
+#define NIG_REG_TX_LLH_PTP_PARAM_MASK 0x501928UL
+#define NIG_REG_TX_LLH_PTP_RULE_MASK 0x50192cUL
+#define NIG_REG_LLH_PTP_HOST_BUF_SEQID 0x501930UL
+#define NIG_REG_LLH_PTP_HOST_BUF_TS_LSB 0x501934UL
+#define NIG_REG_LLH_PTP_HOST_BUF_TS_MSB        0x501938UL
+#define NIG_REG_LLH_PTP_MCP_BUF_SEQID 0x50193cUL
+#define NIG_REG_LLH_PTP_MCP_BUF_TS_LSB 0x501940UL
+#define NIG_REG_LLH_PTP_MCP_BUF_TS_MSB 0x501944UL
+#define NIG_REG_TX_LLH_PTP_BUF_SEQID 0x501948UL
+#define NIG_REG_TX_LLH_PTP_BUF_TS_LSB 0x50194cUL
+#define NIG_REG_TX_LLH_PTP_BUF_TS_MSB 0x501950UL
+#define NIG_REG_RX_PTP_TS_MSB_ERR 0x501954UL
+#define NIG_REG_TX_PTP_TS_MSB_ERR 0x501958UL
+#define NIG_REG_TSGEN_SYNC_TIME_LSB 0x5088c0UL
+#define NIG_REG_TSGEN_SYNC_TIME_MSB 0x5088c4UL
+#define NIG_REG_TSGEN_RST_DRIFT_CNTR 0x5088d8UL
+#define NIG_REG_TSGEN_DRIFT_CNTR_CONF 0x5088dcUL
+#define NIG_REG_TS_OUTPUT_ENABLE_PDA 0x508870UL
+#define NIG_REG_TIMESYNC_GEN_REG_BB 0x500d00UL
+#define NIG_REG_TSGEN_FREE_CNT_VALUE_LSB 0x5088a8UL
+#define NIG_REG_TSGEN_FREE_CNT_VALUE_MSB 0x5088acUL
 #endif
index 3613d63cd5d045ecf973242b74f1c26e593c6a25..4cd1f0ccfa367a5215dd121ca22efa6267e7c51e 100644 (file)
@@ -96,6 +96,7 @@ struct qed_update_vport_params {
 
 struct qed_start_vport_params {
        bool remove_inner_vlan;
+       bool handle_ptp_pkts;
        bool gro_enable;
        bool drop_ttl0;
        u8 vport_id;
@@ -159,6 +160,15 @@ struct qed_eth_cb_ops {
        void (*force_mac) (void *dev, u8 *mac, bool forced);
 };
 
+#define QED_MAX_PHC_DRIFT_PPB   291666666
+
+enum qed_ptp_filter_type {
+       QED_PTP_FILTER_L2,
+       QED_PTP_FILTER_IPV4,
+       QED_PTP_FILTER_IPV4_IPV6,
+       QED_PTP_FILTER_L2_IPV4_IPV6
+};
+
 #ifdef CONFIG_DCB
 /* Prototype declaration of qed_eth_dcbnl_ops should match with the declaration
  * of dcbnl_rtnl_ops structure.
@@ -218,6 +228,17 @@ struct qed_eth_dcbnl_ops {
 };
 #endif
 
+struct qed_eth_ptp_ops {
+       int (*hwtstamp_tx_on)(struct qed_dev *);
+       int (*cfg_rx_filters)(struct qed_dev *, enum qed_ptp_filter_type);
+       int (*read_rx_ts)(struct qed_dev *, u64 *);
+       int (*read_tx_ts)(struct qed_dev *, u64 *);
+       int (*read_cc)(struct qed_dev *, u64 *);
+       int (*disable)(struct qed_dev *);
+       int (*adjfreq)(struct qed_dev *, s32);
+       int (*enable)(struct qed_dev *);
+};
+
 struct qed_eth_ops {
        const struct qed_common_ops *common;
 #ifdef CONFIG_QED_SRIOV
@@ -226,6 +247,7 @@ struct qed_eth_ops {
 #ifdef CONFIG_DCB
        const struct qed_eth_dcbnl_ops *dcb;
 #endif
+       const struct qed_eth_ptp_ops *ptp;
 
        int (*fill_dev_info)(struct qed_dev *cdev,
                             struct qed_dev_eth_info *info);