dt-bindings: Add MSM DSI controller documentation

Signed-off-by: Hai Li <hali@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>

diff --git a/Documentation/devicetree/bindings/drm/msm/dsi.txt b/Documentation/devicetree/bindings/drm/msm/dsi.txt
new file mode 100644 (file)
index 0000000..ff8aebb
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+++ b/Documentation/devicetree/bindings/drm/msm/dsi.txt
@@ -0,0 +1,95 @@
+Qualcomm Technologies Inc. adreno/snapdragon DSI output
+
+Required properties:
+- compatible:
+  * "qcom,mdss-dsi-ctrl"
+- reg: Physical base address and length of the registers of controller, PLL,
+  PHY and PHY regulator
+- reg-names: The names of register regions. The following regions are required:
+  * "dsi_ctrl"
+  * "dsi_pll"
+  * "dsi_phy"
+  * "dsi_phy_regulator"
+- qcom,dsi-host-index: The ID of DSI controller hardware instance. This should
+  be 0 or 1, since we have 2 DSI controllers at most for now.
+- interrupts: The interrupt signal from the DSI block.
+- power-domains: Should be <&mmcc MDSS_GDSC>.
+- clocks: device clocks
+  See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.
+- clock-names: the following clocks are required:
+  * "bus_clk"
+  * "byte_clk"
+  * "core_clk"
+  * "core_mmss_clk"
+  * "iface_clk"
+  * "mdp_core_clk"
+  * "pixel_clk"
+- #clock-cells: The value should be 1.
+- vdd-supply: phandle to vdd regulator device node
+- vddio-supply: phandle to vdd-io regulator device node
+- vdda-supply: phandle to vdda regulator device node
+
+Optional properties:
+- panel@0: Node of panel connected to this DSI controller.
+  See files in Documentation/devicetree/bindings/panel/ for each supported
+  panel.
+- qcom,dual-panel-mode: Boolean value indicating if the DSI controller is
+  driving a panel which needs 2 DSI links.
+- qcom,master-panel: Boolean value indicating if the DSI controller is driving
+  the master link of the 2-DSI panel.
+- qcom,sync-dual-panel: Boolean value indicating if the DSI controller is
+  driving a 2-DSI panel whose 2 links need receive command simultaneously.
+- interrupt-parent: phandle to the MDP block if the interrupt signal is routed
+  through MDP block
+
+Example:
+       mdss_dsi0: qcom,mdss_dsi@fd922800 {
+               compatible = "qcom,mdss-dsi-ctrl";
+               qcom,dsi-host-index = <0>;
+               interrupt-parent = <&mdss_mdp>;
+               interrupts = <4 0>;
+               reg-names =
+                       "dsi_ctrl",
+                       "dsi_pll",
+                       "dsi_phy",
+                       "dsi_phy_regulator",
+               reg =   <0xfd922800 0x200>,
+                       <0xfd922a00 0xd4>,
+                       <0xfd922b00 0x2b0>,
+                       <0xfd922d80 0x7b>,
+                       <0xfd828000 0x108>;
+               power-domains = <&mmcc MDSS_GDSC>;
+               clock-names =
+                       "bus_clk",
+                       "byte_clk",
+                       "core_clk",
+                       "core_mmss_clk",
+                       "iface_clk",
+                       "mdp_core_clk",
+                       "pixel_clk";
+               clocks =
+                       <&mmcc MDSS_AXI_CLK>,
+                       <&mmcc MDSS_BYTE0_CLK>,
+                       <&mmcc MDSS_ESC0_CLK>,
+                       <&mmcc MMSS_MISC_AHB_CLK>,
+                       <&mmcc MDSS_AHB_CLK>,
+                       <&mmcc MDSS_MDP_CLK>,
+                       <&mmcc MDSS_PCLK0_CLK>;
+               #clock-cells = <1>;
+               vdda-supply = <&pma8084_l2>;
+               vdd-supply = <&pma8084_l22>;
+               vddio-supply = <&pma8084_l12>;
+
+               qcom,dual-panel-mode;
+               qcom,master-panel;
+               qcom,sync-dual-panel;
+
+               panel: panel@0 {
+                       compatible = "sharp,lq101r1sx01";
+                       reg = <0>;
+                       link2 = <&secondary>;
+
+                       power-supply = <...>;
+                       backlight = <...>;
+               };
+       };