b43: HT-PHY: use separated function for forcing RF sequence
authorRafał Miłecki <zajec5@gmail.com>
Wed, 24 Aug 2011 09:52:34 +0000 (11:52 +0200)
committerJohn W. Linville <linville@tuxdriver.com>
Fri, 26 Aug 2011 14:47:57 +0000 (10:47 -0400)
Comparison of the HT and N code has shown similarities in the ops
performed after b43_mac_phy_clock_set. That way we understood what is
happening in the HT-PHY code.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
drivers/net/wireless/b43/phy_ht.c
drivers/net/wireless/b43/phy_ht.h

index 62a90842ebfcd2031fed4fbf91cba30c6ac41eaf..c0e436c168669946a01823d769d30707de6c7e5d 100644 (file)
@@ -191,6 +191,27 @@ static void b43_phy_ht_afe_unk1(struct b43_wldev *dev)
        }
 }
 
+static void b43_phy_ht_force_rf_sequence(struct b43_wldev *dev, u16 rf_seq)
+{
+       u8 i;
+
+       u16 save_seq_mode = b43_phy_read(dev, B43_PHY_HT_RF_SEQ_MODE);
+       b43_phy_set(dev, B43_PHY_HT_RF_SEQ_MODE, 0x3);
+
+       b43_phy_set(dev, B43_PHY_HT_RF_SEQ_TRIG, rf_seq);
+       for (i = 0; i < 200; i++) {
+               if (!(b43_phy_read(dev, B43_PHY_HT_RF_SEQ_STATUS) & rf_seq)) {
+                       i = 0;
+                       break;
+               }
+               msleep(1);
+       }
+       if (i)
+               b43err(dev->wl, "Forcing RF sequence timeout\n");
+
+       b43_phy_write(dev, B43_PHY_HT_RF_SEQ_MODE, save_seq_mode);
+}
+
 static void b43_phy_ht_bphy_init(struct b43_wldev *dev)
 {
        unsigned int i;
@@ -313,7 +334,6 @@ static void b43_phy_ht_op_prepare_structs(struct b43_wldev *dev)
 
 static int b43_phy_ht_op_init(struct b43_wldev *dev)
 {
-       u8 i;
        u16 tmp;
 
        b43_phy_ht_tables_init(dev);
@@ -418,14 +438,8 @@ static int b43_phy_ht_op_init(struct b43_wldev *dev)
 
        b43_mac_phy_clock_set(dev, true);
 
-       for (i = 0; i < 2; i++) {
-               tmp = b43_phy_read(dev, B43_PHY_EXTG(0));
-               b43_phy_set(dev, B43_PHY_EXTG(0), 0x3);
-               b43_phy_set(dev, B43_PHY_EXTG(3), i ? 0x20 : 0x1);
-               /* FIXME: wait for some bit to be cleared (find out which) */
-               b43_phy_read(dev, B43_PHY_EXTG(4));
-               b43_phy_write(dev, B43_PHY_EXTG(0), tmp);
-       }
+       b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RX2TX);
+       b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RST2RX);
 
        /* TODO: PHY op on reg 0xb0 */
 
index f70af0caaa334596447bea3618f4dfdea64d7814..0661ae2661016913d1a60dd17f478e8bd5938e6c 100644 (file)
 #define B43_PHY_HT_BW5                         0x1D2
 #define B43_PHY_HT_BW6                         0x1D3
 
+#define B43_PHY_HT_RF_SEQ_MODE                 B43_PHY_EXTG(0x000)
+#define B43_PHY_HT_RF_SEQ_TRIG                 B43_PHY_EXTG(0x003)
+#define  B43_PHY_HT_RF_SEQ_TRIG_RX2TX          0x0001 /* RX2TX */
+#define  B43_PHY_HT_RF_SEQ_TRIG_TX2RX          0x0002 /* TX2RX */
+#define  B43_PHY_HT_RF_SEQ_TRIG_UPGH           0x0004 /* Update gain H */
+#define  B43_PHY_HT_RF_SEQ_TRIG_UPGL           0x0008 /* Update gain L */
+#define  B43_PHY_HT_RF_SEQ_TRIG_UPGU           0x0010 /* Update gain U */
+#define  B43_PHY_HT_RF_SEQ_TRIG_RST2RX         0x0020 /* Reset to RX */
+#define B43_PHY_HT_RF_SEQ_STATUS               B43_PHY_EXTG(0x004)
+/* Values for the status are the same as for the trigger */
+
 #define B43_PHY_HT_RF_CTL1                     B43_PHY_EXTG(0x010)
 
 #define B43_PHY_HT_AFE_CTL1                    B43_PHY_EXTG(0x110)