VCLK(OSC_AUD, VCLK_CLKOUT0, "OSC_AUD", 0, 0, NULL),
};
+#if 0
static __initdata struct of_device_id ext_clk_match[] = {
{.compatible = "samsung,exynos9610-oscclk", .data = (void *)0},
{},
};
+#endif
void exynos9610_vclk_init(void)
{
/* register exynos9610 clocks */
void __init exynos9610_clk_init(struct device_node *np)
{
+#if 0
void __iomem *reg_base;
int ret;
samsung_clk_of_add_provider(np, exynos9610_clk_provider);
late_time_init = exynos9610_vclk_init;
-
+#endif
pr_info("EXYNOS9610: Clock setup completed\n");
}
static int __init exynos4_timer_resources(struct device_node *np, void __iomem *base)
{
int err, cpu;
+#if 0
struct clk *mct_clk, *tick_clk;
tick_clk = np ? of_clk_get_by_name(np, "fin_pll") :
if (IS_ERR(mct_clk))
panic("%s: unable to retrieve mct clock instance\n", __func__);
clk_prepare_enable(mct_clk);
-
+#endif
+ clk_rate = 26000000;
reg_base = base;
if (!reg_base)
panic("%s: unable to ioremap mct address space\n", __func__);