drm/radeon: add get_allowed_info_register for r6xx/r7xx
authorAlex Deucher <alexander.deucher@amd.com>
Wed, 1 Oct 2014 13:36:57 +0000 (09:36 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 19 Mar 2015 16:26:38 +0000 (12:26 -0400)
Registers that can be fetched from the info ioctl.

Tested-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/radeon/r600.c
drivers/gpu/drm/radeon/radeon_asic.c
drivers/gpu/drm/radeon/radeon_asic.h

index 2fcad344492f526a98b46b34d2979cd9dd5a872e..8f6d862a188228101dc9070f5ab2ada5f819d1a6 100644 (file)
@@ -108,6 +108,32 @@ static void r600_pcie_gen2_enable(struct radeon_device *rdev);
 extern int evergreen_rlc_resume(struct radeon_device *rdev);
 extern void rv770_set_clk_bypass_mode(struct radeon_device *rdev);
 
+/**
+ * r600_get_allowed_info_register - fetch the register for the info ioctl
+ *
+ * @rdev: radeon_device pointer
+ * @reg: register offset in bytes
+ * @val: register value
+ *
+ * Returns 0 for success or -EINVAL for an invalid register
+ *
+ */
+int r600_get_allowed_info_register(struct radeon_device *rdev,
+                                  u32 reg, u32 *val)
+{
+       switch (reg) {
+       case GRBM_STATUS:
+       case GRBM_STATUS2:
+       case R_000E50_SRBM_STATUS:
+       case DMA_STATUS_REG:
+       case UVD_STATUS:
+               *val = RREG32(reg);
+               return 0;
+       default:
+               return -EINVAL;
+       }
+}
+
 /**
  * r600_get_xclk - get the xclk
  *
index 558be7a88b2f4483d28ec7195f0fe84af11e51de..f2c343717c4b5f7acfe14edad298ac6885655ee0 100644 (file)
@@ -940,6 +940,7 @@ static struct radeon_asic r600_asic = {
        .mc_wait_for_idle = &r600_mc_wait_for_idle,
        .get_xclk = &r600_get_xclk,
        .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
+       .get_allowed_info_register = r600_get_allowed_info_register,
        .gart = {
                .tlb_flush = &r600_pcie_gart_tlb_flush,
                .get_page_entry = &rs600_gart_get_page_entry,
@@ -1024,6 +1025,7 @@ static struct radeon_asic rv6xx_asic = {
        .mc_wait_for_idle = &r600_mc_wait_for_idle,
        .get_xclk = &r600_get_xclk,
        .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
+       .get_allowed_info_register = r600_get_allowed_info_register,
        .gart = {
                .tlb_flush = &r600_pcie_gart_tlb_flush,
                .get_page_entry = &rs600_gart_get_page_entry,
@@ -1116,6 +1118,7 @@ static struct radeon_asic rs780_asic = {
        .mc_wait_for_idle = &r600_mc_wait_for_idle,
        .get_xclk = &r600_get_xclk,
        .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
+       .get_allowed_info_register = r600_get_allowed_info_register,
        .gart = {
                .tlb_flush = &r600_pcie_gart_tlb_flush,
                .get_page_entry = &rs600_gart_get_page_entry,
@@ -1221,6 +1224,7 @@ static struct radeon_asic rv770_asic = {
        .mc_wait_for_idle = &r600_mc_wait_for_idle,
        .get_xclk = &rv770_get_xclk,
        .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
+       .get_allowed_info_register = r600_get_allowed_info_register,
        .gart = {
                .tlb_flush = &r600_pcie_gart_tlb_flush,
                .get_page_entry = &rs600_gart_get_page_entry,
index 4259daf94d91a51fdedb7ba73ba09813798cc755..3e1346d585b3e3641a5685c8b16840b8c29e1bf8 100644 (file)
@@ -384,6 +384,8 @@ u32 r600_gfx_get_wptr(struct radeon_device *rdev,
                      struct radeon_ring *ring);
 void r600_gfx_set_wptr(struct radeon_device *rdev,
                       struct radeon_ring *ring);
+int r600_get_allowed_info_register(struct radeon_device *rdev,
+                                  u32 reg, u32 *val);
 /* r600 irq */
 int r600_irq_process(struct radeon_device *rdev);
 int r600_irq_init(struct radeon_device *rdev);