[9610] arm64: dts: Enable SD card for erd9610

Change-Id: I4f58d39764b57353e3ddccb7ac082b5ba454415d
Signed-off-by: JaeHun Jung <jh0801.jung@samsung.com>

diff --git a/arch/arm64/boot/dts/exynos/exynos9610-erd9610.dts b/arch/arm64/boot/dts/exynos/exynos9610-erd9610.dts
index 8c8386122a3a945ac2fac8fa0f8e24227c8f2b2e..fe725b14ded2d351979a05720a831463334d1d54 100644 (file)
--- a/arch/arm64/boot/dts/exynos/exynos9610-erd9610.dts
+++ b/arch/arm64/boot/dts/exynos/exynos9610-erd9610.dts
@@ -846,6 +846,65 @@
                };
        };
 
+       pinctrl@11850000 {
+               dwmmc2_cd_ext_irq: dwmmc2_cd_ext_irq {
+                       samsung,pins = "gpa0-7";
+                       samsung,pin-function = <0xf>;
+                       samsung,pin-pud = <3>;
+                       samsung,pin-drv = <3>;
+               };
+       };
+
+       dwmmc2@13550000 {
+               status = "okay";
+               num-slots = <1>;
+               supports-4bit;
+               supports-cmd23;
+               supports-erase;
+               supports-highspeed;
+               sd-uhs-sdr50;
+               sd-uhs-sdr104;
+               card-detect-gpio;
+               bypass-for-allpass;
+               card-init-hwacg-ctrl;
+               skip-init-mmc-scan;
+               qos-dvfs-level = <100000>;
+               fifo-depth = <0x40>;
+               desc-size = <4>;
+               card-detect-delay = <200>;
+               data-timeout = <200>;
+               hto-timeout = <80>;
+               samsung,dw-mshc-ciu-div = <3>;
+               clock-frequency = <800000000>;
+               samsung,dw-mshc-sdr-timing = <3 0 2 0>;
+               samsung,dw-mshc-ddr-timing = <3 0 2 1>;
+               samsung,dw-mshc-sdr50-timing = <3 0 4 2>;
+               samsung,dw-mshc-sdr104-timing = <3 0 3 0>;
+
+               num-ref-clks = <9>;
+               ciu_clkin = <25 50 50 25 50 100 200 50 50>;
+
+               /* Swapping clock drive strength */
+               clk-drive-number = <4>;
+               pinctrl-names = "default",
+                       "fast-slew-rate-1x",
+                       "fast-slew-rate-2x",
+                       "fast-slew-rate-3x",
+                       "fast-slew-rate-4x";
+               pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus1 &sd2_bus4 &dwmmc2_cd_ext_irq>;
+               pinctrl-1 = <&sd2_clk_fast_slew_rate_1x>;
+               pinctrl-2 = <&sd2_clk_fast_slew_rate_2x>;
+               pinctrl-3 = <&sd2_clk_fast_slew_rate_3x>;
+               pinctrl-4 = <&sd2_clk_fast_slew_rate_4x>;
+
+               card-detect = <&gpa0 7 0xf>;
+               slot@0 {
+                       reg = <0>;
+                       bus-width = <4>;
+                       disable-wp;
+               };
+       };
+
        pinctrl@11850000 {
                attn_irq: attn-irq {
                        samsung,pins = "gpa2-4";

diff --git a/arch/arm64/boot/dts/exynos/exynos9610.dtsi b/arch/arm64/boot/dts/exynos/exynos9610.dtsi
index 2f7c10d4a4af55f99aa5f2e24377e09c89e0b3dd..a4bbfc86b2723bba1f486d245fd65ac1df0eafe6 100644 (file)
--- a/arch/arm64/boot/dts/exynos/exynos9610.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos9610.dtsi
@@ -106,6 +106,7 @@
                decon0 = &decon_f;
                scaler0 = &scaler_0;
                mfc0 = &mfc_0;
+               mshc2 = &dwmmc_2;
        };
 
        chipid@10000000 {
@@ -3149,6 +3150,18 @@
                };
        };
 
+       dwmmc_2: dwmmc2@13550000 {
+               compatible = "samsung,exynos-dw-mshc";
+               reg = <0x0 0x13550000 0x2000>;
+               reg-names = "dw_mmc";
+               interrupts = <0 147 0>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               clocks = <&clock MMC_CARD>;
+               clock-names = "ciu";
+               status = "disabled";
+       };
+
        /* Secure log */
        seclog {
                compatible = "samsung,exynos-seclog";