{9, 58, 22, 14, 14, 5}, /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
};
-static void wlc_clkctl_clk(struct wlc_hw_info *wlc, uint mode);
-static void wlc_coreinit(struct wlc_info *wlc);
+static void brcms_b_clkctl_clk(struct wlc_hw_info *wlc, uint mode);
+static void brcms_b_coreinit(struct wlc_info *wlc);
/* used by wlc_wakeucode_init() */
static void wlc_write_inits(struct wlc_hw_info *wlc_hw,
static void wlc_ucode_txant_set(struct wlc_hw_info *wlc_hw);
/* used by wlc_dpc() */
-static bool wlc_bmac_dotxstatus(struct wlc_hw_info *wlc, tx_status_t *txs,
+static bool brcms_b_dotxstatus(struct wlc_hw_info *wlc, tx_status_t *txs,
u32 s2);
-static bool wlc_bmac_txstatus(struct wlc_hw_info *wlc, bool bound, bool *fatal);
-static bool wlc_bmac_recv(struct wlc_hw_info *wlc_hw, uint fifo, bool bound);
+static bool brcms_b_txstatus(struct wlc_hw_info *wlc, bool bound, bool *fatal);
+static bool brcms_b_recv(struct wlc_hw_info *wlc_hw, uint fifo, bool bound);
/* used by wlc_down() */
static void wlc_flushqueues(struct wlc_info *wlc);
static void wlc_write_mhf(struct wlc_hw_info *wlc_hw, u16 *mhfs);
static void wlc_mctrl_reset(struct wlc_hw_info *wlc_hw);
-static void wlc_corerev_fifofixup(struct wlc_hw_info *wlc_hw);
-static bool wlc_bmac_tx_fifo_suspended(struct wlc_hw_info *wlc_hw,
+static void brcms_b_corerev_fifofixup(struct wlc_hw_info *wlc_hw);
+static bool brcms_b_tx_fifo_suspended(struct wlc_hw_info *wlc_hw,
uint tx_fifo);
-static void wlc_bmac_tx_fifo_suspend(struct wlc_hw_info *wlc_hw, uint tx_fifo);
-static void wlc_bmac_tx_fifo_resume(struct wlc_hw_info *wlc_hw, uint tx_fifo);
+static void brcms_b_tx_fifo_suspend(struct wlc_hw_info *wlc_hw, uint tx_fifo);
+static void brcms_b_tx_fifo_resume(struct wlc_hw_info *wlc_hw, uint tx_fifo);
/* Low Level Prototypes */
-static int wlc_bmac_bandtype(struct wlc_hw_info *wlc_hw);
-static void wlc_bmac_info_init(struct wlc_hw_info *wlc_hw);
-static void wlc_bmac_xtal(struct wlc_hw_info *wlc_hw, bool want);
-static u16 wlc_bmac_read_objmem(struct wlc_hw_info *wlc_hw, uint offset,
+static int brcms_b_bandtype(struct wlc_hw_info *wlc_hw);
+static void brcms_b_info_init(struct wlc_hw_info *wlc_hw);
+static void brcms_b_xtal(struct wlc_hw_info *wlc_hw, bool want);
+static u16 brcms_b_read_objmem(struct wlc_hw_info *wlc_hw, uint offset,
u32 sel);
-static void wlc_bmac_write_objmem(struct wlc_hw_info *wlc_hw, uint offset,
+static void brcms_b_write_objmem(struct wlc_hw_info *wlc_hw, uint offset,
u16 v, u32 sel);
-static void wlc_bmac_core_phy_clk(struct wlc_hw_info *wlc_hw, bool clk);
-static bool wlc_bmac_attach_dmapio(struct wlc_info *wlc, uint j, bool wme);
-static void wlc_bmac_detach_dmapio(struct wlc_hw_info *wlc_hw);
+static void brcms_b_core_phy_clk(struct wlc_hw_info *wlc_hw, bool clk);
+static bool brcms_b_attach_dmapio(struct wlc_info *wlc, uint j, bool wme);
+static void brcms_b_detach_dmapio(struct wlc_hw_info *wlc_hw);
static void wlc_ucode_bsinit(struct wlc_hw_info *wlc_hw);
static bool wlc_validboardtype(struct wlc_hw_info *wlc);
static bool wlc_isgoodchip(struct wlc_hw_info *wlc_hw);
-static bool wlc_bmac_validate_chip_access(struct wlc_hw_info *wlc_hw);
+static bool brcms_b_validate_chip_access(struct wlc_hw_info *wlc_hw);
static char *wlc_get_macaddr(struct wlc_hw_info *wlc_hw);
static void wlc_mhfdef(struct wlc_info *wlc, u16 *mhfs, u16 mhf2_init);
static void wlc_mctrl_write(struct wlc_hw_info *wlc_hw);
-static void wlc_bmac_mute(struct wlc_hw_info *wlc_hw, bool want, mbool flags);
+static void brcms_b_mute(struct wlc_hw_info *wlc_hw, bool want, mbool flags);
static void wlc_ucode_mute_override_set(struct wlc_hw_info *wlc_hw);
static void wlc_ucode_mute_override_clear(struct wlc_hw_info *wlc_hw);
static u32 wlc_wlintrsoff(struct wlc_info *wlc);
int len);
static void wlc_write_hw_bcntemplate1(struct wlc_hw_info *wlc_hw, void *bcn,
int len);
-static void wlc_bmac_bsinit(struct wlc_info *wlc, chanspec_t chanspec);
+static void brcms_b_bsinit(struct wlc_info *wlc, chanspec_t chanspec);
static u32 wlc_setband_inact(struct wlc_info *wlc, uint bandunit);
-static void wlc_bmac_setband(struct wlc_hw_info *wlc_hw, uint bandunit,
+static void brcms_b_setband(struct wlc_hw_info *wlc_hw, uint bandunit,
chanspec_t chanspec);
-static void wlc_bmac_update_slot_timing(struct wlc_hw_info *wlc_hw,
+static void brcms_b_update_slot_timing(struct wlc_hw_info *wlc_hw,
bool shortslot);
static void wlc_upd_ofdm_pctl1_table(struct wlc_hw_info *wlc_hw);
-static u16 wlc_bmac_ofdm_ratetable_offset(struct wlc_hw_info *wlc_hw,
+static u16 brcms_b_ofdm_ratetable_offset(struct wlc_hw_info *wlc_hw,
u8 rate);
/* === Low Level functions === */
-void wlc_bmac_set_shortslot(struct wlc_hw_info *wlc_hw, bool shortslot)
+void brcms_b_set_shortslot(struct wlc_hw_info *wlc_hw, bool shortslot)
{
wlc_hw->shortslot = shortslot;
- if (BAND_2G(wlc_bmac_bandtype(wlc_hw)) && wlc_hw->up) {
+ if (BAND_2G(brcms_b_bandtype(wlc_hw)) && wlc_hw->up) {
wlc_suspend_mac_and_wait(wlc_hw->wlc);
- wlc_bmac_update_slot_timing(wlc_hw, shortslot);
+ brcms_b_update_slot_timing(wlc_hw, shortslot);
wlc_enable_mac(wlc_hw->wlc);
}
}
* or shortslot 11g (9us slots)
* The PSM needs to be suspended for this call.
*/
-static void wlc_bmac_update_slot_timing(struct wlc_hw_info *wlc_hw,
+static void brcms_b_update_slot_timing(struct wlc_hw_info *wlc_hw,
bool shortslot)
{
d11regs_t *regs;
if (shortslot) {
/* 11g short slot: 11a timing */
W_REG(®s->ifs_slot, 0x0207); /* APHY_SLOT_TIME */
- wlc_bmac_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME);
+ brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME);
} else {
/* 11g long slot: 11b timing */
W_REG(®s->ifs_slot, 0x0212); /* BPHY_SLOT_TIME */
- wlc_bmac_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME);
+ brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME);
}
}
/* radio off */
wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
- wlc_bmac_core_phy_clk(wlc_hw, OFF);
+ brcms_b_core_phy_clk(wlc_hw, OFF);
wlc_setxband(wlc_hw, bandunit);
* Param 'bound' indicates max. # frames to process before break out.
*/
static bool
-wlc_bmac_recv(struct wlc_hw_info *wlc_hw, uint fifo, bool bound)
+brcms_b_recv(struct wlc_hw_info *wlc_hw, uint fifo, bool bound)
{
struct sk_buff *p;
struct sk_buff *head = NULL;
/* tx status */
if (macintstatus & MI_TFS) {
- if (wlc_bmac_txstatus(wlc->hw, bounded, &fatal))
+ if (brcms_b_txstatus(wlc->hw, bounded, &fatal))
wlc->macintstatus |= MI_TFS;
if (fatal) {
wiphy_err(wiphy, "MI_TFS: fatal\n");
}
/* received data or control frame, MI_DMAINT is indication of RX_FIFO interrupt */
- if (macintstatus & MI_DMAINT) {
- if (wlc_bmac_recv(wlc_hw, RX_FIFO, bounded)) {
+ if (macintstatus & MI_DMAINT)
+ if (brcms_b_recv(wlc_hw, RX_FIFO, bounded))
wlc->macintstatus |= MI_DMAINT;
- }
- }
/* TX FIFO suspend/flush completion */
- if (macintstatus & MI_TXSTOP) {
- if (wlc_bmac_tx_fifo_suspended(wlc_hw, TX_DATA_FIFO)) {
- /* wiphy_err(wiphy, "dpc: fifo_suspend_comlete\n"); */
- }
- }
+ if (macintstatus & MI_TXSTOP)
+ if (brcms_b_tx_fifo_suspended(wlc_hw, TX_DATA_FIFO));
/* noise sample collected */
if (macintstatus & MI_BG_NOISE) {
}
/* common low-level watchdog code */
-void wlc_bmac_watchdog(void *arg)
+void brcms_b_watchdog(void *arg)
{
struct wlc_info *wlc = (struct wlc_info *) arg;
struct wlc_hw_info *wlc_hw = wlc->hw;
wlc_hw->now++;
/* Check for FIFO error interrupts */
- wlc_bmac_fifoerrors(wlc_hw);
+ brcms_b_fifoerrors(wlc_hw);
/* make sure RX dma has buffers */
dma_rxfill(wlc->hw->di[RX_FIFO]);
}
void
-wlc_bmac_set_chanspec(struct wlc_hw_info *wlc_hw, chanspec_t chanspec,
+brcms_b_set_chanspec(struct wlc_hw_info *wlc_hw, chanspec_t chanspec,
bool mute, struct txpwr_limits *txpwr)
{
uint bandunit;
if (NBANDS_HW(wlc_hw) > 1) {
bandunit = CHSPEC_WLCBANDUNIT(chanspec);
if (wlc_hw->band->bandunit != bandunit) {
- /* wlc_bmac_setband disables other bandunit,
+ /* brcms_b_setband disables other bandunit,
* use light band switch if not up yet
*/
if (wlc_hw->up) {
wlc_phy_chanspec_radio_set(wlc_hw->
bandstate[bandunit]->
pi, chanspec);
- wlc_bmac_setband(wlc_hw, bandunit, chanspec);
+ brcms_b_setband(wlc_hw, bandunit, chanspec);
} else {
wlc_setxband(wlc_hw, bandunit);
}
wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, chanspec);
/* Update muting of the channel */
- wlc_bmac_mute(wlc_hw, mute, 0);
+ brcms_b_mute(wlc_hw, mute, 0);
}
}
-int wlc_bmac_state_get(struct wlc_hw_info *wlc_hw, wlc_bmac_state_t *state)
+int brcms_b_state_get(struct wlc_hw_info *wlc_hw, brcms_b_state_t *state)
{
state->machwcap = wlc_hw->machwcap;
return 0;
}
-static bool wlc_bmac_attach_dmapio(struct wlc_info *wlc, uint j, bool wme)
+static bool brcms_b_attach_dmapio(struct wlc_info *wlc, uint j, bool wme)
{
uint i;
char name[8];
return true;
}
-static void wlc_bmac_detach_dmapio(struct wlc_hw_info *wlc_hw)
+static void brcms_b_detach_dmapio(struct wlc_hw_info *wlc_hw)
{
uint j;
* initialize software state for each core and band
* put the whole chip in reset(driver down state), no clock
*/
-int wlc_bmac_attach(struct wlc_info *wlc, u16 vendor, u16 device, uint unit,
+int brcms_b_attach(struct wlc_info *wlc, u16 vendor, u16 device, uint unit,
bool piomode, void *regsva, uint bustype, void *btparam)
{
struct wlc_hw_info *wlc_hw;
wlc_hw->_piomode = piomode;
/* populate struct wlc_hw_info with default values */
- wlc_bmac_info_init(wlc_hw);
+ brcms_b_info_init(wlc_hw);
/*
* Do the hardware portion of the attach.
wlc_hw->sih = ai_attach(regsva, bustype, btparam,
&wlc_hw->vars, &wlc_hw->vars_size);
if (wlc_hw->sih == NULL) {
- wiphy_err(wiphy, "wl%d: wlc_bmac_attach: si_attach failed\n",
+ wiphy_err(wiphy, "wl%d: brcms_b_attach: si_attach failed\n",
unit);
err = 11;
goto fail;
/* verify again the device is supported */
if (!wlc_chipmatch(vendor, device)) {
- wiphy_err(wiphy, "wl%d: wlc_bmac_attach: Unsupported "
+ wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported "
"vendor/device (0x%x/0x%x)\n",
unit, vendor, device);
err = 12;
* For PMU chips, the first wlc_clkctl_clk is no-op since core-clk is still false;
* But it will be called again inside wlc_corereset, after d11 is out of reset.
*/
- wlc_clkctl_clk(wlc_hw, CLK_FAST);
- wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
+ brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
+ brcms_b_corereset(wlc_hw, WLC_USE_COREFLAGS);
- if (!wlc_bmac_validate_chip_access(wlc_hw)) {
- wiphy_err(wiphy, "wl%d: wlc_bmac_attach: validate_chip_access "
+ if (!brcms_b_validate_chip_access(wlc_hw)) {
+ wiphy_err(wiphy, "wl%d: brcms_b_attach: validate_chip_access "
"failed\n", unit);
err = 14;
goto fail;
j = BOARDREV_PROMOTED;
wlc_hw->boardrev = (u16) j;
if (!wlc_validboardtype(wlc_hw)) {
- wiphy_err(wiphy, "wl%d: wlc_bmac_attach: Unsupported Broadcom "
+ wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported Broadcom "
"board type (0x%x)" " or revision level (0x%x)\n",
unit, wlc_hw->sih->boardtype, wlc_hw->boardrev);
err = 15;
wlc_hw->boardflags2 = (u32) getintvar(vars, "boardflags2");
if (wlc_hw->boardflags & BFL_NOPLLDOWN)
- wlc_bmac_pllreq(wlc_hw, true, WLC_PLLREQ_SHARED);
+ brcms_b_pllreq(wlc_hw, true, WLC_PLLREQ_SHARED);
if ((wlc_hw->sih->bustype == PCI_BUS)
&& (ai_pci_war16165(wlc_hw->sih)))
wlc_hw->physhim = wlc_phy_shim_attach(wlc_hw, wlc->wl, wlc);
if (wlc_hw->physhim == NULL) {
- wiphy_err(wiphy, "wl%d: wlc_bmac_attach: wlc_phy_shim_attach "
+ wiphy_err(wiphy, "wl%d: brcms_b_attach: wlc_phy_shim_attach "
"failed\n", unit);
err = 25;
goto fail;
/* Get a phy for this band */
wlc_hw->band->pi = wlc_phy_attach(wlc_hw->phy_sh,
- (void *)regs, wlc_bmac_bandtype(wlc_hw), vars,
+ (void *)regs, brcms_b_bandtype(wlc_hw), vars,
wlc->wiphy);
if (wlc_hw->band->pi == NULL) {
- wiphy_err(wiphy, "wl%d: wlc_bmac_attach: wlc_phy_"
+ wiphy_err(wiphy, "wl%d: brcms_b_attach: wlc_phy_"
"attach failed\n", unit);
err = 17;
goto fail;
goto bad_phy;
} else {
bad_phy:
- wiphy_err(wiphy, "wl%d: wlc_bmac_attach: unsupported "
+ wiphy_err(wiphy, "wl%d: brcms_b_attach: unsupported "
"phy type/rev (%d/%d)\n", unit,
wlc_hw->band->phytype, wlc_hw->band->phyrev);
err = 18;
wlc_hw->band->CWmin = APHY_CWMIN;
wlc_hw->band->CWmax = PHY_CWMAX;
- if (!wlc_bmac_attach_dmapio(wlc, j, wme)) {
+ if (!brcms_b_attach_dmapio(wlc, j, wme)) {
err = 19;
goto fail;
}
(void *)wlc_wlintrsrestore, NULL, wlc);
/* turn off pll and xtal to match driver "down" state */
- wlc_bmac_xtal(wlc_hw, OFF);
+ brcms_b_xtal(wlc_hw, OFF);
/* *********************************************************************
* The hardware is in the DOWN state at this point. D11 core
/* init etheraddr state variables */
macaddr = wlc_get_macaddr(wlc_hw);
if (macaddr == NULL) {
- wiphy_err(wiphy, "wl%d: wlc_bmac_attach: macaddr not found\n",
+ wiphy_err(wiphy, "wl%d: brcms_b_attach: macaddr not found\n",
unit);
err = 21;
goto fail;
brcmu_ether_atoe(macaddr, wlc_hw->etheraddr);
if (is_broadcast_ether_addr(wlc_hw->etheraddr) ||
is_zero_ether_addr(wlc_hw->etheraddr)) {
- wiphy_err(wiphy, "wl%d: wlc_bmac_attach: bad macaddr %s\n",
+ wiphy_err(wiphy, "wl%d: brcms_b_attach: bad macaddr %s\n",
unit, macaddr);
err = 22;
goto fail;
return err;
fail:
- wiphy_err(wiphy, "wl%d: wlc_bmac_attach: failed with err %d\n", unit,
+ wiphy_err(wiphy, "wl%d: brcms_b_attach: failed with err %d\n", unit,
err);
return err;
}
* may get overrides later in this function
* BMAC_NOTES, move low out and resolve the dangling ones
*/
-static void wlc_bmac_info_init(struct wlc_hw_info *wlc_hw)
+static void brcms_b_info_init(struct wlc_hw_info *wlc_hw)
{
struct wlc_info *wlc = wlc_hw->wlc;
/*
* low level detach
*/
-int wlc_bmac_detach(struct wlc_info *wlc)
+int brcms_b_detach(struct wlc_info *wlc)
{
uint i;
struct wlc_hwband *band;
ai_pci_sleep(wlc_hw->sih);
}
- wlc_bmac_detach_dmapio(wlc_hw);
+ brcms_b_detach_dmapio(wlc_hw);
band = wlc_hw->band;
for (i = 0; i < NBANDS_HW(wlc_hw); i++) {
}
-void wlc_bmac_reset(struct wlc_hw_info *wlc_hw)
+void brcms_b_reset(struct wlc_hw_info *wlc_hw)
{
BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
/* reset the core */
if (!DEVICEREMOVED(wlc_hw->wlc))
- wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
+ brcms_b_corereset(wlc_hw, WLC_USE_COREFLAGS);
/* purge the dma rings */
wlc_flushqueues(wlc_hw->wlc);
}
void
-wlc_bmac_init(struct wlc_hw_info *wlc_hw, chanspec_t chanspec,
+brcms_b_init(struct wlc_hw_info *wlc_hw, chanspec_t chanspec,
bool mute) {
u32 macintmask;
bool fastclk;
/* request FAST clock if not on */
fastclk = wlc_hw->forcefastclk;
if (!fastclk)
- wlc_clkctl_clk(wlc_hw, CLK_FAST);
+ brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
/* disable interrupts */
macintmask = brcms_intrsoff(wlc->wl);
wlc_phy_cal_init(wlc_hw->band->pi);
/* core-specific initialization */
- wlc_coreinit(wlc);
+ brcms_b_coreinit(wlc);
/* suspend the tx fifos and mute the phy for preism cac time */
if (mute)
- wlc_bmac_mute(wlc_hw, ON, PHY_MUTE_FOR_PREISM);
+ brcms_b_mute(wlc_hw, ON, PHY_MUTE_FOR_PREISM);
/* band-specific inits */
- wlc_bmac_bsinit(wlc, chanspec);
+ brcms_b_bsinit(wlc, chanspec);
/* restore macintmask */
brcms_intrsrestore(wlc->wl, macintmask);
/* restore the clk */
if (!fastclk)
- wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
+ brcms_b_clkctl_clk(wlc_hw, CLK_DYNAMIC);
}
-int wlc_bmac_up_prep(struct wlc_hw_info *wlc_hw)
+int brcms_b_up_prep(struct wlc_hw_info *wlc_hw)
{
uint coremask;
* Enable pll and xtal, initialize the power control registers,
* and force fastclock for the remainder of wlc_up().
*/
- wlc_bmac_xtal(wlc_hw, ON);
+ brcms_b_xtal(wlc_hw, ON);
ai_clkctl_init(wlc_hw->sih);
- wlc_clkctl_clk(wlc_hw, CLK_FAST);
+ brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
/*
* Configure pci/pcmcia here instead of in wlc_attach()
* Need to read the hwradio status here to cover the case where the system
* is loaded with the hw radio disabled. We do not want to bring the driver up in this case.
*/
- if (wlc_bmac_radio_read_hwdisabled(wlc_hw)) {
+ if (brcms_b_radio_read_hwdisabled(wlc_hw)) {
/* put SB PCI in down state again */
if (wlc_hw->sih->bustype == PCI_BUS)
ai_pci_down(wlc_hw->sih);
- wlc_bmac_xtal(wlc_hw, OFF);
+ brcms_b_xtal(wlc_hw, OFF);
return -ENOMEDIUM;
}
ai_pci_up(wlc_hw->sih);
/* reset the d11 core */
- wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
+ brcms_b_corereset(wlc_hw, WLC_USE_COREFLAGS);
return 0;
}
-int wlc_bmac_up_finish(struct wlc_hw_info *wlc_hw)
+int brcms_b_up_finish(struct wlc_hw_info *wlc_hw)
{
BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
wlc_phy_hw_state_upd(wlc_hw->band->pi, true);
/* FULLY enable dynamic power control and d11 core interrupt */
- wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
+ brcms_b_clkctl_clk(wlc_hw, CLK_DYNAMIC);
brcms_intrson(wlc_hw->wlc->wl);
return 0;
}
-int wlc_bmac_down_prep(struct wlc_hw_info *wlc_hw)
+int brcms_b_bmac_down_prep(struct wlc_hw_info *wlc_hw)
{
bool dev_gone;
uint callbacks = 0;
brcms_intrsoff(wlc_hw->wlc->wl);
/* ensure we're running on the pll clock again */
- wlc_clkctl_clk(wlc_hw, CLK_FAST);
+ brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
}
/* down phy at the last of this stage */
callbacks += wlc_phy_down(wlc_hw->band->pi);
return callbacks;
}
-int wlc_bmac_down_finish(struct wlc_hw_info *wlc_hw)
+int brcms_b_down_finish(struct wlc_hw_info *wlc_hw)
{
uint callbacks = 0;
bool dev_gone;
if (!wlc_hw->noreset) {
if (wlc_hw->sih->bustype == PCI_BUS)
ai_pci_down(wlc_hw->sih);
- wlc_bmac_xtal(wlc_hw, OFF);
+ brcms_b_xtal(wlc_hw, OFF);
}
}
return callbacks;
}
-void wlc_bmac_wait_for_wake(struct wlc_hw_info *wlc_hw)
+void brcms_b_wait_for_wake(struct wlc_hw_info *wlc_hw)
{
/* delay before first read of ucode state */
udelay(40);
/* wait until ucode is no longer asleep */
- SPINWAIT((wlc_bmac_read_shm(wlc_hw, M_UCODE_DBGST) ==
+ SPINWAIT((brcms_b_read_shm(wlc_hw, M_UCODE_DBGST) ==
DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly);
}
-void wlc_bmac_hw_etheraddr(struct wlc_hw_info *wlc_hw, u8 *ea)
+void brcms_b_hw_etheraddr(struct wlc_hw_info *wlc_hw, u8 *ea)
{
memcpy(ea, wlc_hw->etheraddr, ETH_ALEN);
}
-static int wlc_bmac_bandtype(struct wlc_hw_info *wlc_hw)
+static int brcms_b_bandtype(struct wlc_hw_info *wlc_hw)
{
return wlc_hw->band->bandtype;
}
/* control chip clock to save power, enable dynamic clock or force fast clock */
-static void wlc_clkctl_clk(struct wlc_hw_info *wlc_hw, uint mode)
+static void brcms_b_clkctl_clk(struct wlc_hw_info *wlc_hw, uint mode)
{
if (PMUCTL_ENAB(wlc_hw->sih)) {
/* new chips with PMU, CCS_FORCEHT will distribute the HT clock on backplane,
* WLC_BAND_ALL <--- All bands
*/
void
-wlc_bmac_mhf(struct wlc_hw_info *wlc_hw, u8 idx, u16 mask, u16 val,
+brcms_b_mhf(struct wlc_hw_info *wlc_hw, u8 idx, u16 mask, u16 val,
int bands)
{
u16 save;
*/
if (wlc_hw->clk && (band->mhfs[idx] != save)
&& (band == wlc_hw->band))
- wlc_bmac_write_shm(wlc_hw, addr[idx],
+ brcms_b_write_shm(wlc_hw, addr[idx],
(u16) band->mhfs[idx]);
}
}
}
-u16 wlc_bmac_mhf_get(struct wlc_hw_info *wlc_hw, u8 idx, int bands)
+u16 brcms_b_mhf_get(struct wlc_hw_info *wlc_hw, u8 idx, int bands)
{
struct wlc_hwband *band;
};
for (idx = 0; idx < MHFMAX; idx++) {
- wlc_bmac_write_shm(wlc_hw, addr[idx], mhfs[idx]);
+ brcms_b_write_shm(wlc_hw, addr[idx], mhfs[idx]);
}
}
wlc_hw->suspended_fifos = 0;
wlc_hw->wake_override = 0;
wlc_hw->mute_override = 0;
- wlc_bmac_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE);
+ brcms_b_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE);
}
/* set or clear maccontrol bits */
-void wlc_bmac_mctrl(struct wlc_hw_info *wlc_hw, u32 mask, u32 val)
+void brcms_b_mctrl(struct wlc_hw_info *wlc_hw, u32 mask, u32 val)
{
u32 maccontrol;
u32 new_maccontrol;
mboolset(wlc_hw->wake_override, override_bit);
wlc_mctrl_write(wlc_hw);
- wlc_bmac_wait_for_wake(wlc_hw);
+ brcms_b_wait_for_wake(wlc_hw);
return;
}
* Write a MAC address to the given match reg offset in the RXE match engine.
*/
void
-wlc_bmac_set_addrmatch(struct wlc_hw_info *wlc_hw, int match_reg_offset,
+brcms_b_set_addrmatch(struct wlc_hw_info *wlc_hw, int match_reg_offset,
const u8 *addr)
{
d11regs_t *regs;
u16 mac_m;
u16 mac_h;
- BCMMSG(wlc_hw->wlc->wiphy, "wl%d: wlc_bmac_set_addrmatch\n",
+ BCMMSG(wlc_hw->wlc->wiphy, "wl%d: brcms_b_set_addrmatch\n",
wlc_hw->unit);
regs = wlc_hw->regs;
}
void
-wlc_bmac_write_template_ram(struct wlc_hw_info *wlc_hw, int offset, int len,
+brcms_b_write_template_ram(struct wlc_hw_info *wlc_hw, int offset, int len,
void *buf)
{
d11regs_t *regs;
}
}
-void wlc_bmac_set_cwmin(struct wlc_hw_info *wlc_hw, u16 newmin)
+void brcms_b_set_cwmin(struct wlc_hw_info *wlc_hw, u16 newmin)
{
wlc_hw->band->CWmin = newmin;
W_REG(&wlc_hw->regs->objdata, newmin);
}
-void wlc_bmac_set_cwmax(struct wlc_hw_info *wlc_hw, u16 newmax)
+void brcms_b_set_cwmax(struct wlc_hw_info *wlc_hw, u16 newmax)
{
wlc_hw->band->CWmax = newmax;
W_REG(&wlc_hw->regs->objdata, newmax);
}
-void wlc_bmac_bw_set(struct wlc_hw_info *wlc_hw, u16 bw)
+void brcms_b_bw_set(struct wlc_hw_info *wlc_hw, u16 bw)
{
bool fastclk;
/* request FAST clock if not on */
fastclk = wlc_hw->forcefastclk;
if (!fastclk)
- wlc_clkctl_clk(wlc_hw, CLK_FAST);
+ brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
- wlc_bmac_phy_reset(wlc_hw);
+ brcms_b_phy_reset(wlc_hw);
wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi));
/* restore the clk */
if (!fastclk)
- wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
+ brcms_b_clkctl_clk(wlc_hw, CLK_DYNAMIC);
}
static void
{
d11regs_t *regs = wlc_hw->regs;
- wlc_bmac_write_template_ram(wlc_hw, T_BCN0_TPL_BASE, (len + 3) & ~3,
+ brcms_b_write_template_ram(wlc_hw, T_BCN0_TPL_BASE, (len + 3) & ~3,
bcn);
/* write beacon length to SCR */
- wlc_bmac_write_shm(wlc_hw, M_BCN0_FRM_BYTESZ, (u16) len);
+ brcms_b_write_shm(wlc_hw, M_BCN0_FRM_BYTESZ, (u16) len);
/* mark beacon0 valid */
OR_REG(®s->maccommand, MCMD_BCN0VLD);
}
{
d11regs_t *regs = wlc_hw->regs;
- wlc_bmac_write_template_ram(wlc_hw, T_BCN1_TPL_BASE, (len + 3) & ~3,
+ brcms_b_write_template_ram(wlc_hw, T_BCN1_TPL_BASE, (len + 3) & ~3,
bcn);
/* write beacon length to SCR */
- wlc_bmac_write_shm(wlc_hw, M_BCN1_FRM_BYTESZ, (u16) len);
+ brcms_b_write_shm(wlc_hw, M_BCN1_FRM_BYTESZ, (u16) len);
/* mark beacon1 valid */
OR_REG(®s->maccommand, MCMD_BCN1VLD);
}
/* mac is assumed to be suspended at this point */
void
-wlc_bmac_write_hw_bcntemplates(struct wlc_hw_info *wlc_hw, void *bcn, int len,
+brcms_b_write_hw_bcntemplates(struct wlc_hw_info *wlc_hw, void *bcn, int len,
bool both)
{
d11regs_t *regs = wlc_hw->regs;
}
}
-static void WLBANDINITFN(wlc_bmac_upd_synthpu) (struct wlc_hw_info *wlc_hw)
+static void WLBANDINITFN(brcms_b_upd_synthpu) (struct wlc_hw_info *wlc_hw)
{
u16 v;
struct wlc_info *wlc = wlc_hw->wlc;
v = SYNTHPU_DLY_BPHY_US;
}
- wlc_bmac_write_shm(wlc_hw, M_SYNTHPU_DLY, v);
+ brcms_b_write_shm(wlc_hw, M_SYNTHPU_DLY, v);
}
/* band-specific init */
static void
-WLBANDINITFN(wlc_bmac_bsinit) (struct wlc_info *wlc, chanspec_t chanspec)
+WLBANDINITFN(brcms_b_bsinit) (struct wlc_info *wlc, chanspec_t chanspec)
{
struct wlc_hw_info *wlc_hw = wlc->hw;
wlc_ucode_txant_set(wlc_hw);
/* cwmin is band-specific, update hardware with value for current band */
- wlc_bmac_set_cwmin(wlc_hw, wlc_hw->band->CWmin);
- wlc_bmac_set_cwmax(wlc_hw, wlc_hw->band->CWmax);
+ brcms_b_set_cwmin(wlc_hw, wlc_hw->band->CWmin);
+ brcms_b_set_cwmax(wlc_hw, wlc_hw->band->CWmax);
- wlc_bmac_update_slot_timing(wlc_hw,
+ brcms_b_update_slot_timing(wlc_hw,
BAND_5G(wlc_hw->band->
bandtype) ? true : wlc_hw->
shortslot);
/* write phytype and phyvers */
- wlc_bmac_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype);
- wlc_bmac_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev);
+ brcms_b_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype);
+ brcms_b_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev);
/* initialize the txphyctl1 rate table since shmem is shared between bands */
wlc_upd_ofdm_pctl1_table(wlc_hw);
- wlc_bmac_upd_synthpu(wlc_hw);
+ brcms_b_upd_synthpu(wlc_hw);
}
-static void wlc_bmac_core_phy_clk(struct wlc_hw_info *wlc_hw, bool clk)
+static void brcms_b_core_phy_clk(struct wlc_hw_info *wlc_hw, bool clk)
{
BCMMSG(wlc_hw->wlc->wiphy, "wl%d: clk %d\n", wlc_hw->unit, clk);
}
/* Perform a soft reset of the PHY PLL */
-void wlc_bmac_core_phypll_reset(struct wlc_hw_info *wlc_hw)
+void brcms_b_core_phypll_reset(struct wlc_hw_info *wlc_hw)
{
BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
}
/* light way to turn on phy clock without reset for NPHY only
- * refer to wlc_bmac_core_phy_clk for full version
+ * refer to brcms_b_core_phy_clk for full version
*/
-void wlc_bmac_phyclk_fgc(struct wlc_hw_info *wlc_hw, bool clk)
+void brcms_b_phyclk_fgc(struct wlc_hw_info *wlc_hw, bool clk)
{
/* support(necessary for NPHY and HYPHY) only */
if (!WLCISNPHY(wlc_hw->band))
}
-void wlc_bmac_macphyclk_set(struct wlc_hw_info *wlc_hw, bool clk)
+void brcms_b_macphyclk_set(struct wlc_hw_info *wlc_hw, bool clk)
{
if (ON == clk)
ai_core_cflags(wlc_hw->sih, SICF_MPCLKE, SICF_MPCLKE);
ai_core_cflags(wlc_hw->sih, SICF_MPCLKE, 0);
}
-void wlc_bmac_phy_reset(struct wlc_hw_info *wlc_hw)
+void brcms_b_phy_reset(struct wlc_hw_info *wlc_hw)
{
wlc_phy_t *pih = wlc_hw->band->pi;
u32 phy_bw_clkbits;
udelay(1);
/* Perform a soft reset of the PHY PLL */
- wlc_bmac_core_phypll_reset(wlc_hw);
+ brcms_b_core_phypll_reset(wlc_hw);
/* reset the PHY */
ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_PCLKE),
}
udelay(2);
- wlc_bmac_core_phy_clk(wlc_hw, ON);
+ brcms_b_core_phy_clk(wlc_hw, ON);
if (pih)
wlc_phy_anacore(pih, ON);
/* switch to and initialize new band */
static void
-WLBANDINITFN(wlc_bmac_setband) (struct wlc_hw_info *wlc_hw, uint bandunit,
+WLBANDINITFN(brcms_b_setband) (struct wlc_hw_info *wlc_hw, uint bandunit,
chanspec_t chanspec) {
struct wlc_info *wlc = wlc_hw->wlc;
u32 macintmask;
if (!wlc_hw->up)
return;
- wlc_bmac_core_phy_clk(wlc_hw, ON);
+ brcms_b_core_phy_clk(wlc_hw, ON);
/* band-specific initializations */
- wlc_bmac_bsinit(wlc, chanspec);
+ brcms_b_bsinit(wlc, chanspec);
/*
* If there are any pending software interrupt bits,
* this function could be called when driver is down and w/o clock
* it operates on different registers depending on corerev and boardflag.
*/
-bool wlc_bmac_radio_read_hwdisabled(struct wlc_hw_info *wlc_hw)
+bool brcms_b_radio_read_hwdisabled(struct wlc_hw_info *wlc_hw)
{
bool v, clk, xtal;
u32 resetbits = 0, flags = 0;
xtal = wlc_hw->sbclk;
if (!xtal)
- wlc_bmac_xtal(wlc_hw, ON);
+ brcms_b_xtal(wlc_hw, ON);
/* may need to take core out of reset first */
clk = wlc_hw->clk;
ai_core_disable(wlc_hw->sih, 0);
if (!xtal)
- wlc_bmac_xtal(wlc_hw, OFF);
+ brcms_b_xtal(wlc_hw, OFF);
return v;
}
/* Initialize just the hardware when coming out of POR or S3/S5 system states */
-void wlc_bmac_hw_up(struct wlc_hw_info *wlc_hw)
+void brcms_b_hw_up(struct wlc_hw_info *wlc_hw)
{
if (wlc_hw->wlc->pub->hw_up)
return;
* Enable pll and xtal, initialize the power control registers,
* and force fastclock for the remainder of wlc_up().
*/
- wlc_bmac_xtal(wlc_hw, ON);
+ brcms_b_xtal(wlc_hw, ON);
ai_clkctl_init(wlc_hw->sih);
- wlc_clkctl_clk(wlc_hw, CLK_FAST);
+ brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
if (wlc_hw->sih->bustype == PCI_BUS) {
ai_pci_fixcfg(wlc_hw->sih);
* clear software macintstatus for fresh new start
* one testing hack wlc_hw->noreset will bypass the d11/phy reset
*/
-void wlc_bmac_corereset(struct wlc_hw_info *wlc_hw, u32 flags)
+void brcms_b_corereset(struct wlc_hw_info *wlc_hw, u32 flags)
{
d11regs_t *regs;
uint i;
/* request FAST clock if not on */
fastclk = wlc_hw->forcefastclk;
if (!fastclk)
- wlc_clkctl_clk(wlc_hw, CLK_FAST);
+ brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
/* reset the dma engines except first time thru */
if (ai_iscoreup(wlc_hw->sih)) {
/* if noreset, just stop the psm and return */
if (wlc_hw->noreset) {
wlc_hw->wlc->macintstatus = 0; /* skip wl_dpc after down */
- wlc_bmac_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0);
+ brcms_b_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0);
return;
}
wlc_mctrl_reset(wlc_hw);
if (PMUCTL_ENAB(wlc_hw->sih))
- wlc_clkctl_clk(wlc_hw, CLK_FAST);
+ brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
- wlc_bmac_phy_reset(wlc_hw);
+ brcms_b_phy_reset(wlc_hw);
/* turn on PHY_PLL */
- wlc_bmac_core_phypll_ctl(wlc_hw, true);
+ brcms_b_core_phypll_ctl(wlc_hw, true);
/* clear sw intstatus */
wlc_hw->wlc->macintstatus = 0;
/* restore the clk setting */
if (!fastclk)
- wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
+ brcms_b_clkctl_clk(wlc_hw, CLK_DYNAMIC);
}
/* txfifo sizes needs to be modified(increased) since the newer cores
* have more memory.
*/
-static void wlc_corerev_fifofixup(struct wlc_hw_info *wlc_hw)
+static void brcms_b_corerev_fifofixup(struct wlc_hw_info *wlc_hw)
{
d11regs_t *regs = wlc_hw->regs;
u16 fifo_nu;
* need to propagate to shm location to be in sync since ucode/hw won't
* do this
*/
- wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE0,
+ brcms_b_write_shm(wlc_hw, M_FIFOSIZE0,
wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]);
- wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE1,
+ brcms_b_write_shm(wlc_hw, M_FIFOSIZE1,
wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]);
- wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE2,
+ brcms_b_write_shm(wlc_hw, M_FIFOSIZE2,
((wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO] << 8) | wlc_hw->
xmtfifo_sz[TX_AC_BK_FIFO]));
- wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE3,
+ brcms_b_write_shm(wlc_hw, M_FIFOSIZE3,
((wlc_hw->xmtfifo_sz[TX_ATIM_FIFO] << 8) | wlc_hw->
xmtfifo_sz[TX_BCMC_FIFO]));
}
* config other core registers
* init dma
*/
-static void wlc_coreinit(struct wlc_info *wlc)
+static void brcms_b_coreinit(struct wlc_info *wlc)
{
struct wlc_hw_info *wlc_hw = wlc->hw;
d11regs_t *regs;
BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
/* reset PSM */
- wlc_bmac_mctrl(wlc_hw, ~0, (MCTL_IHR_EN | MCTL_PSM_JMP_0 | MCTL_WAKE));
+ brcms_b_mctrl(wlc_hw, ~0, (MCTL_IHR_EN | MCTL_PSM_JMP_0 | MCTL_WAKE));
wlc_ucode_download(wlc_hw);
/*
/* let the PSM run to the suspended state, set mode to BSS STA */
W_REG(®s->macintstatus, -1);
- wlc_bmac_mctrl(wlc_hw, ~0,
+ brcms_b_mctrl(wlc_hw, ~0,
(MCTL_IHR_EN | MCTL_INFRA | MCTL_PSM_RUN | MCTL_WAKE));
/* wait for ucode to self-suspend after auto-init */
/* For old ucode, txfifo sizes needs to be modified(increased) */
if (fifosz_fixup == true) {
- wlc_corerev_fifofixup(wlc_hw);
+ brcms_b_corerev_fifofixup(wlc_hw);
}
/* check txfifo allocations match between ucode and driver */
- buf[TX_AC_BE_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE0);
+ buf[TX_AC_BE_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE0);
if (buf[TX_AC_BE_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]) {
i = TX_AC_BE_FIFO;
err = -1;
}
- buf[TX_AC_VI_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE1);
+ buf[TX_AC_VI_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE1);
if (buf[TX_AC_VI_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]) {
i = TX_AC_VI_FIFO;
err = -1;
}
- buf[TX_AC_BK_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE2);
+ buf[TX_AC_BK_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE2);
buf[TX_AC_VO_FIFO] = (buf[TX_AC_BK_FIFO] >> 8) & 0xff;
buf[TX_AC_BK_FIFO] &= 0xff;
if (buf[TX_AC_BK_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BK_FIFO]) {
i = TX_AC_VO_FIFO;
err = -1;
}
- buf[TX_BCMC_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE3);
+ buf[TX_BCMC_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE3);
buf[TX_ATIM_FIFO] = (buf[TX_BCMC_FIFO] >> 8) & 0xff;
buf[TX_BCMC_FIFO] &= 0xff;
if (buf[TX_BCMC_FIFO] != wlc_hw->xmtfifo_sz[TX_BCMC_FIFO]) {
/* band-specific inits done by wlc_bsinit() */
/* Set up frame burst size and antenna swap threshold init values */
- wlc_bmac_write_shm(wlc_hw, M_MBURST_SIZE, MAXTXFRAMEBURST);
- wlc_bmac_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT);
+ brcms_b_write_shm(wlc_hw, M_MBURST_SIZE, MAXTXFRAMEBURST);
+ brcms_b_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT);
/* enable one rx interrupt per received frame */
W_REG(®s->intrcvlazy[0], (1 << IRL_FC_SHIFT));
/* set the station mode (BSS STA) */
- wlc_bmac_mctrl(wlc_hw,
+ brcms_b_mctrl(wlc_hw,
(MCTL_INFRA | MCTL_DISCARD_PMQ | MCTL_AP),
(MCTL_INFRA | MCTL_DISCARD_PMQ));
W_REG(®s->intctrlregs[RX_FIFO].intmask, DEF_RXINTMASK);
/* allow the MAC to control the PHY clock (dynamic on/off) */
- wlc_bmac_macphyclk_set(wlc_hw, ON);
+ brcms_b_macphyclk_set(wlc_hw, ON);
/* program dynamic clock control fast powerup delay register */
wlc->fastpwrup_dly = ai_clkctl_fast_pwrup_delay(wlc_hw->sih);
W_REG(®s->scc_fastpwrup_dly, wlc->fastpwrup_dly);
/* tell the ucode the corerev */
- wlc_bmac_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev);
+ brcms_b_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev);
/* tell the ucode MAC capabilities */
- wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_L,
+ brcms_b_write_shm(wlc_hw, M_MACHW_CAP_L,
(u16) (wlc_hw->machwcap & 0xffff));
- wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_H,
+ brcms_b_write_shm(wlc_hw, M_MACHW_CAP_H,
(u16) ((wlc_hw->
machwcap >> 16) & 0xffff));
W_REG(®s->objdata, wlc_hw->LRL);
/* write rate fallback retry limits */
- wlc_bmac_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL);
- wlc_bmac_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL);
+ brcms_b_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL);
+ brcms_b_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL);
AND_REG(®s->ifs_ctl, 0x0FFF);
W_REG(®s->ifs_aifsn, EDCF_AIFSN_MIN);
* - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889
*/
-void wlc_bmac_switch_macfreq(struct wlc_hw_info *wlc_hw, u8 spurmode)
+void brcms_b_switch_macfreq(struct wlc_hw_info *wlc_hw, u8 spurmode)
{
d11regs_t *regs;
regs = wlc_hw->regs;
regs = wlc_hw->regs;
/* use GPIO select 0 to get all gpio signals from the gpio out reg */
- wlc_bmac_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0);
+ brcms_b_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0);
/*
* Common GPIO setup:
/* Allocate GPIOs for mimo antenna diversity feature */
if (wlc_hw->antsel_type == ANTSEL_2x3) {
/* Enable antenna diversity, use 2x3 mode */
- wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
+ brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
MHF3_ANTSEL_EN, WLC_BAND_ALL);
- wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE,
+ brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE,
MHF3_ANTSEL_MODE, WLC_BAND_ALL);
/* init superswitch control */
(BOARD_GPIO_12 | BOARD_GPIO_13));
/* Enable antenna diversity, use 2x4 mode */
- wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
+ brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
MHF3_ANTSEL_EN, WLC_BAND_ALL);
- wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0,
+ brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0,
WLC_BAND_ALL);
/* Configure the desired clock to be 4Mhz */
- wlc_bmac_write_shm(wlc_hw, M_ANTSEL_CLKDIV,
+ brcms_b_write_shm(wlc_hw, M_ANTSEL_CLKDIV,
ANTSEL_CLKDIV_4MHZ);
}
u16 mask = PHY_TXC_ANT_MASK;
/* set the Probe Response frame phy control word */
- phyctl = wlc_bmac_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS);
+ phyctl = brcms_b_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS);
phyctl = (phyctl & ~mask) | phytxant;
- wlc_bmac_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl);
+ brcms_b_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl);
/* set the Response (ACK/CTS) frame phy control word */
- phyctl = wlc_bmac_read_shm(wlc_hw, M_RSP_PCTLWD);
+ phyctl = brcms_b_read_shm(wlc_hw, M_RSP_PCTLWD);
phyctl = (phyctl & ~mask) | phytxant;
- wlc_bmac_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl);
+ brcms_b_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl);
}
-void wlc_bmac_txant_set(struct wlc_hw_info *wlc_hw, u16 phytxant)
+void brcms_b_txant_set(struct wlc_hw_info *wlc_hw, u16 phytxant)
{
/* update sw state */
wlc_hw->bmac_phytxant = phytxant;
}
-u16 wlc_bmac_get_txant(struct wlc_hw_info *wlc_hw)
+u16 brcms_b_get_txant(struct wlc_hw_info *wlc_hw)
{
return (u16) wlc_hw->wlc->stf->txant;
}
-void wlc_bmac_antsel_type_set(struct wlc_hw_info *wlc_hw, u8 antsel_type)
+void brcms_b_antsel_type_set(struct wlc_hw_info *wlc_hw, u8 antsel_type)
{
wlc_hw->antsel_type = antsel_type;
wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type);
}
-void wlc_bmac_fifoerrors(struct wlc_hw_info *wlc_hw)
+void brcms_b_fifoerrors(struct wlc_hw_info *wlc_hw)
{
bool fatal = false;
uint unit;
W_REG(&wlc_hw->regs->macintmask, wlc->macintmask);
}
-static void wlc_bmac_mute(struct wlc_hw_info *wlc_hw, bool on, mbool flags)
+static void brcms_b_mute(struct wlc_hw_info *wlc_hw, bool on, mbool flags)
{
u8 null_ether_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
if (on) {
/* suspend tx fifos */
- wlc_bmac_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO);
- wlc_bmac_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO);
- wlc_bmac_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO);
- wlc_bmac_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO);
+ brcms_b_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO);
+ brcms_b_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO);
+ brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO);
+ brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO);
/* zero the address match register so we do not send ACKs */
- wlc_bmac_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
+ brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
null_ether_addr);
} else {
/* resume tx fifos */
if (!wlc_hw->wlc->tx_suspended) {
- wlc_bmac_tx_fifo_resume(wlc_hw, TX_DATA_FIFO);
+ brcms_b_tx_fifo_resume(wlc_hw, TX_DATA_FIFO);
}
- wlc_bmac_tx_fifo_resume(wlc_hw, TX_CTL_FIFO);
- wlc_bmac_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO);
- wlc_bmac_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO);
+ brcms_b_tx_fifo_resume(wlc_hw, TX_CTL_FIFO);
+ brcms_b_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO);
+ brcms_b_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO);
/* Restore address */
- wlc_bmac_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
+ brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
wlc_hw->etheraddr);
}
wlc_ucode_mute_override_clear(wlc_hw);
}
-int wlc_bmac_xmtfifo_sz_get(struct wlc_hw_info *wlc_hw, uint fifo, uint *blocks)
+int brcms_b_xmtfifo_sz_get(struct wlc_hw_info *wlc_hw, uint fifo, uint *blocks)
{
if (fifo >= NFIFO)
return -EINVAL;
return 0;
}
-/* wlc_bmac_tx_fifo_suspended:
+/* brcms_b_tx_fifo_suspended:
* Check the MAC's tx suspend status for a tx fifo.
*
* When the MAC acknowledges a tx suspend, it indicates that no more
* be pulling data into a tx fifo, by the time the MAC acks the suspend
* request.
*/
-static bool wlc_bmac_tx_fifo_suspended(struct wlc_hw_info *wlc_hw, uint tx_fifo)
+static bool brcms_b_tx_fifo_suspended(struct wlc_hw_info *wlc_hw, uint tx_fifo)
{
/* check that a suspend has been requested and is no longer pending */
return false;
}
-static void wlc_bmac_tx_fifo_suspend(struct wlc_hw_info *wlc_hw, uint tx_fifo)
+static void brcms_b_tx_fifo_suspend(struct wlc_hw_info *wlc_hw, uint tx_fifo)
{
u8 fifo = 1 << tx_fifo;
}
}
-static void wlc_bmac_tx_fifo_resume(struct wlc_hw_info *wlc_hw, uint tx_fifo)
+static void brcms_b_tx_fifo_resume(struct wlc_hw_info *wlc_hw, uint tx_fifo)
{
/* BMAC_NOTE: WLC_TX_FIFO_ENAB is done in wlc_dpc() for DMA case but need to be done
* here for PIO otherwise the watchdog will catch the inconsistency and fire
}
static bool
-wlc_bmac_dotxstatus(struct wlc_hw_info *wlc_hw, tx_status_t *txs, u32 s2)
+brcms_b_dotxstatus(struct wlc_hw_info *wlc_hw, tx_status_t *txs, u32 s2)
{
/* discard intermediate indications for ucode with one legitimate case:
* e.g. if "useRTS" is set. ucode did a successful rts/cts exchange, but the subsequent
* Return true if more tx status need to be processed. false otherwise.
*/
static bool
-wlc_bmac_txstatus(struct wlc_hw_info *wlc_hw, bool bound, bool *fatal)
+brcms_b_txstatus(struct wlc_hw_info *wlc_hw, bool bound, bool *fatal)
{
bool morepending = false;
struct wlc_info *wlc = wlc_hw->wlc;
txs->phyerr = (s2 & TXS_PTX_MASK) >> TXS_PTX_SHIFT;
txs->lasttxtime = 0;
- *fatal = wlc_bmac_dotxstatus(wlc_hw, txs, s2);
+ *fatal = brcms_b_dotxstatus(wlc_hw, txs, s2);
/* !give others some time to run! */
if (++n >= max_tx_num)
}
WARN_ON(mi & MI_MACSSPNDD);
- wlc_bmac_mctrl(wlc_hw, MCTL_EN_MAC, 0);
+ brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, 0);
SPINWAIT(!(R_REG(®s->macintstatus) & MI_MACSSPNDD),
WLC_MAX_MAC_SUSPEND);
WARN_ON(mc & MCTL_EN_MAC);
WARN_ON(!(mc & MCTL_PSM_RUN));
- wlc_bmac_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC);
+ brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC);
W_REG(®s->macintstatus, MI_MACSSPNDD);
mc = R_REG(®s->maccontrol);
for (i = 0; i < ARRAY_SIZE(rates); i++) {
rate = rates[i];
- entry_ptr = wlc_bmac_ofdm_ratetable_offset(wlc_hw, rate);
+ entry_ptr = brcms_b_ofdm_ratetable_offset(wlc_hw, rate);
/* read the SHM Rate Table entry OFDM PCTL1 values */
pctl1 =
- wlc_bmac_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS);
+ brcms_b_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS);
/* modify the value */
pctl1 &= ~PHY_TXC1_MODE_MASK;
pctl1 |= (wlc_hw->hw_stf_ss_opmode << PHY_TXC1_MODE_SHIFT);
/* Update the SHM Rate Table entry OFDM PCTL1 values */
- wlc_bmac_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS,
+ brcms_b_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS,
pctl1);
}
}
-static u16 wlc_bmac_ofdm_ratetable_offset(struct wlc_hw_info *wlc_hw, u8 rate)
+static u16 brcms_b_ofdm_ratetable_offset(struct wlc_hw_info *wlc_hw, u8 rate)
{
uint i;
u8 plcp_rate = 0;
/* Find the SHM pointer to the rate table entry by looking in the
* Direct-map Table
*/
- return 2 * wlc_bmac_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2));
+ return 2 * brcms_b_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2));
}
-void wlc_bmac_band_stf_ss_set(struct wlc_hw_info *wlc_hw, u8 stf_mode)
+void brcms_b_band_stf_ss_set(struct wlc_hw_info *wlc_hw, u8 stf_mode)
{
wlc_hw->hw_stf_ss_opmode = stf_mode;
}
void
-wlc_bmac_read_tsf(struct wlc_hw_info *wlc_hw, u32 *tsf_l_ptr,
+brcms_b_read_tsf(struct wlc_hw_info *wlc_hw, u32 *tsf_l_ptr,
u32 *tsf_h_ptr)
{
d11regs_t *regs = wlc_hw->regs;
return;
}
-static bool wlc_bmac_validate_chip_access(struct wlc_hw_info *wlc_hw)
+static bool brcms_b_validate_chip_access(struct wlc_hw_info *wlc_hw)
{
d11regs_t *regs;
u32 w, val;
#define PHYPLL_WAIT_US 100000
-void wlc_bmac_core_phypll_ctl(struct wlc_hw_info *wlc_hw, bool on)
+void brcms_b_core_phypll_ctl(struct wlc_hw_info *wlc_hw, bool on)
{
d11regs_t *regs;
u32 tmp;
wlc_phy_anacore(wlc_hw->band->pi, OFF);
/* turn off PHYPLL to save power */
- wlc_bmac_core_phypll_ctl(wlc_hw, false);
+ brcms_b_core_phypll_ctl(wlc_hw, false);
/* No need to set wlc->pub->radio_active = OFF
* because this function needs down capability and
}
/* power both the pll and external oscillator on/off */
-static void wlc_bmac_xtal(struct wlc_hw_info *wlc_hw, bool want)
+static void brcms_b_xtal(struct wlc_hw_info *wlc_hw, bool want)
{
BCMMSG(wlc_hw->wlc->wiphy, "wl%d: want %d\n", wlc_hw->unit, want);
dma_rxreclaim(wlc_hw->di[RX_FIFO]);
}
-u16 wlc_bmac_read_shm(struct wlc_hw_info *wlc_hw, uint offset)
+u16 brcms_b_read_shm(struct wlc_hw_info *wlc_hw, uint offset)
{
- return wlc_bmac_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL);
+ return brcms_b_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL);
}
-void wlc_bmac_write_shm(struct wlc_hw_info *wlc_hw, uint offset, u16 v)
+void brcms_b_write_shm(struct wlc_hw_info *wlc_hw, uint offset, u16 v)
{
- wlc_bmac_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL);
+ brcms_b_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL);
}
static u16
-wlc_bmac_read_objmem(struct wlc_hw_info *wlc_hw, uint offset, u32 sel)
+brcms_b_read_objmem(struct wlc_hw_info *wlc_hw, uint offset, u32 sel)
{
d11regs_t *regs = wlc_hw->regs;
volatile u16 *objdata_lo = (volatile u16 *)®s->objdata;
}
static void
-wlc_bmac_write_objmem(struct wlc_hw_info *wlc_hw, uint offset, u16 v, u32 sel)
+brcms_b_write_objmem(struct wlc_hw_info *wlc_hw, uint offset, u16 v, u32 sel)
{
d11regs_t *regs = wlc_hw->regs;
volatile u16 *objdata_lo = (volatile u16 *)®s->objdata;
* 'sel' selects the type of memory
*/
void
-wlc_bmac_copyto_objmem(struct wlc_hw_info *wlc_hw, uint offset, const void *buf,
+brcms_b_copyto_objmem(struct wlc_hw_info *wlc_hw, uint offset, const void *buf,
int len, u32 sel)
{
u16 v;
for (i = 0; i < len; i += 2) {
v = p[i] | (p[i + 1] << 8);
- wlc_bmac_write_objmem(wlc_hw, offset + i, v, sel);
+ brcms_b_write_objmem(wlc_hw, offset + i, v, sel);
}
}
* 'sel' selects the type of memory
*/
void
-wlc_bmac_copyfrom_objmem(struct wlc_hw_info *wlc_hw, uint offset, void *buf,
+brcms_b_copyfrom_objmem(struct wlc_hw_info *wlc_hw, uint offset, void *buf,
int len, u32 sel)
{
u16 v;
return;
for (i = 0; i < len; i += 2) {
- v = wlc_bmac_read_objmem(wlc_hw, offset + i, sel);
+ v = brcms_b_read_objmem(wlc_hw, offset + i, sel);
p[i] = v & 0xFF;
p[i + 1] = (v >> 8) & 0xFF;
}
}
-void wlc_bmac_copyfrom_vars(struct wlc_hw_info *wlc_hw, char **buf, uint *len)
+void brcms_b_copyfrom_vars(struct wlc_hw_info *wlc_hw, char **buf, uint *len)
{
BCMMSG(wlc_hw->wlc->wiphy, "nvram vars totlen=%d\n",
wlc_hw->vars_size);
*len = wlc_hw->vars_size;
}
-void wlc_bmac_retrylimit_upd(struct wlc_hw_info *wlc_hw, u16 SRL, u16 LRL)
+void brcms_b_retrylimit_upd(struct wlc_hw_info *wlc_hw, u16 SRL, u16 LRL)
{
wlc_hw->SRL = SRL;
wlc_hw->LRL = LRL;
}
}
-void wlc_bmac_pllreq(struct wlc_hw_info *wlc_hw, bool set, mbool req_bit)
+void brcms_b_pllreq(struct wlc_hw_info *wlc_hw, bool set, mbool req_bit)
{
if (set) {
if (mboolisset(wlc_hw->pllreq, req_bit))
if (mboolisset(wlc_hw->pllreq, WLC_PLLREQ_FLIP)) {
if (!wlc_hw->sbclk) {
- wlc_bmac_xtal(wlc_hw, ON);
+ brcms_b_xtal(wlc_hw, ON);
}
}
} else {
if (mboolisset(wlc_hw->pllreq, WLC_PLLREQ_FLIP)) {
if (wlc_hw->sbclk) {
- wlc_bmac_xtal(wlc_hw, OFF);
+ brcms_b_xtal(wlc_hw, OFF);
}
}
}
return;
}
-u16 wlc_bmac_rate_shm_offset(struct wlc_hw_info *wlc_hw, u8 rate)
+u16 brcms_b_rate_shm_offset(struct wlc_hw_info *wlc_hw, u8 rate)
{
u16 table_ptr;
u8 phy_rate, index;
/* Find the SHM pointer to the rate table entry by looking in the
* Direct-map Table
*/
- return 2 * wlc_bmac_read_shm(wlc_hw, table_ptr + (index * 2));
+ return 2 * brcms_b_read_shm(wlc_hw, table_ptr + (index * 2));
}
-void wlc_bmac_antsel_set(struct wlc_hw_info *wlc_hw, u32 antsel_avail)
+void brcms_b_antsel_set(struct wlc_hw_info *wlc_hw, u32 antsel_avail)
{
wlc_hw->antsel_avail = antsel_avail;
}
*/
/* To inform the ucode of the last mcast frame posted so that it can clear moredata bit */
-#define BCMCFID(wlc, fid) wlc_bmac_write_shm((wlc)->hw, M_BCMC_FID, (fid))
+#define BCMCFID(wlc, fid) brcms_b_write_shm((wlc)->hw, M_BCMC_FID, (fid))
#define WLC_WAR16165(wlc) (wlc->pub->sih->bustype == PCI_BUS && \
(!AP_ENAB(wlc->pub)) && (wlc->war16165))
memset((char *)wlc->core->macstat_snapshot, 0,
sizeof(macstat_t));
- wlc_bmac_reset(wlc->hw);
+ brcms_b_reset(wlc->hw);
}
void wlc_fatal_error(struct wlc_info *wlc)
else
chanspec = wlc_init_chanspec(wlc);
- wlc_bmac_init(wlc->hw, chanspec, mute);
+ brcms_b_init(wlc->hw, chanspec, mute);
/* update beacon listen interval */
wlc_bcn_li_upd(wlc);
awake_before = ((v1 & MCTL_WAKE) || ((v1 & MCTL_HPS) == 0));
if (!awake_before)
- wlc_bmac_wait_for_wake(wlc->hw);
+ brcms_b_wait_for_wake(wlc->hw);
}
WLAN_CAPABILITY_SHORT_SLOT_TIME;
}
- wlc_bmac_set_shortslot(wlc->hw, shortslot);
+ brcms_b_set_shortslot(wlc->hw, shortslot);
}
static u8 wlc_local_constraint_qdbm(struct wlc_info *wlc)
CHSPEC_CHANNEL(chanspec));
return;
}
- /* BMAC_NOTE: should the setband call come after the wlc_bmac_chanspec() ?
- * if the setband updates (wlc_bsinit) use low level calls to inspect and
- * set state, the state inspected may be from the wrong band, or the
- * following wlc_bmac_set_chanspec() may undo the work.
+ /*
+ * should the setband call come after the
+ * brcms_b_chanspec() ? if the setband updates
+ * (wlc_bsinit) use low level calls to inspect and
+ * set state, the state inspected may be from the wrong
+ * band, or the following brcms_b_set_chanspec() may
+ * undo the work.
*/
wlc_setband(wlc, bandunit);
}
static bool wlc_state_bmac_sync(struct wlc_info *wlc)
{
- wlc_bmac_state_t state_bmac;
+ brcms_b_state_t state_bmac;
- if (wlc_bmac_state_get(wlc->hw, &state_bmac) != 0)
+ if (brcms_b_state_get(wlc->hw, &state_bmac) != 0)
return false;
wlc->machwcap = state_bmac.machwcap;
* low level attach steps(all hw accesses go
* inside, no more in rest of the attach)
*/
- err = wlc_bmac_attach(wlc, vendor, device, unit, piomode, regsva,
+ err = brcms_b_attach(wlc, vendor, device, unit, piomode, regsva,
bustype, btparam);
if (err)
goto fail;
pub->phy_11ncapable = WLC_PHY_11N_CAP(wlc->band);
/* propagate *vars* from BMAC driver to high driver */
- wlc_bmac_copyfrom_vars(wlc->hw, &pub->vars, &wlc->vars_size);
+ brcms_b_copyfrom_vars(wlc->hw, &pub->vars, &wlc->vars_size);
/* set maximum allowed duty cycle */
wlc->core->txavail[i] = wlc->hw->txavail[i];
}
- wlc_bmac_hw_etheraddr(wlc->hw, wlc->perm_etheraddr);
+ brcms_b_hw_etheraddr(wlc->hw, wlc->perm_etheraddr);
memcpy(&pub->cur_etheraddr, &wlc->perm_etheraddr, ETH_ALEN);
if ((wlc->pub->sih->chip) == BCM43235_CHIP_ID) {
if ((getintvar(wlc->pub->vars, "aa2g") == 7) ||
(getintvar(wlc->pub->vars, "aa5g") == 7)) {
- wlc_bmac_antsel_set(wlc->hw, 1);
+ brcms_b_antsel_set(wlc->hw, 1);
}
} else {
- wlc_bmac_antsel_set(wlc->hw, wlc->asi->antsel_avail);
+ brcms_b_antsel_set(wlc->hw, wlc->asi->antsel_avail);
}
if (perr)
BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
- callbacks += wlc_bmac_detach(wlc);
+ callbacks += brcms_b_detach(wlc);
/* delete software timers */
if (!wlc_radio_monitor_stop(wlc))
if (wlc->pub->wlfeatureflag & WL_SWFL_NOHWRADIO || wlc->pub->hw_off)
return;
- if (wlc_bmac_radio_read_hwdisabled(wlc->hw)) {
+ if (brcms_b_radio_read_hwdisabled(wlc->hw)) {
mboolset(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE);
} else {
mboolclr(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE);
if (wlc->pub->radio_disabled)
return;
- wlc_bmac_watchdog(wlc);
+ brcms_b_watchdog(wlc);
/* occasionally sample mac stat counters to detect 16-bit counter wrap */
if ((wlc->pub->now % SW_TIMER_MAC_STAT_UPD) == 0)
return -ENOMEDIUM;
if (!wlc->pub->hw_up) {
- wlc_bmac_hw_up(wlc->hw);
+ brcms_b_hw_up(wlc->hw);
wlc->pub->hw_up = true;
}
* if radio is disabled, abort up, lower power, start radio timer and return 0(for NDIS)
* don't call radio_update to avoid looping wlc_up.
*
- * wlc_bmac_up_prep() returns either 0 or -BCME_RADIOOFF only
+ * brcms_b_up_prep() returns either 0 or -BCME_RADIOOFF only
*/
if (!wlc->pub->radio_disabled) {
- int status = wlc_bmac_up_prep(wlc->hw);
+ int status = brcms_b_up_prep(wlc->hw);
if (status == -ENOMEDIUM) {
if (!mboolisset
(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE)) {
return 0;
}
- /* wlc_bmac_up_prep has done wlc_corereset(). so clk is on, set it */
+ /* brcms_b_up_prep has done wlc_corereset(). so clk is on, set it */
wlc->clk = true;
wlc_radio_monitor_stop(wlc);
wlc_enable_mac(wlc);
}
- wlc_bmac_up_finish(wlc->hw);
+ brcms_b_up_finish(wlc->hw);
/* other software states up after ISR is running */
/* start APs that were to be brought up but are not up yet */
/* in between, mpc could try to bring down again.. */
wlc->going_down = true;
- callbacks += wlc_bmac_down_prep(wlc->hw);
+ callbacks += brcms_b_bmac_down_prep(wlc->hw);
dev_gone = DEVICEREMOVED(wlc);
brcmu_pktq_flush(&qi->q, true, NULL, NULL);
}
- callbacks += wlc_bmac_down_finish(wlc->hw);
+ callbacks += brcms_b_down_finish(wlc->hw);
- /* wlc_bmac_down_finish has done wlc_coredisable(). so clk is off */
+ /* brcms_b_down_finish has done wlc_coredisable(). so clk is off */
wlc->clk = false;
wlc->going_down = false;
int ac;
wlc->SRL = (u16) val;
- wlc_bmac_retrylimit_upd(wlc->hw, wlc->SRL, wlc->LRL);
+ brcms_b_retrylimit_upd(wlc->hw, wlc->SRL, wlc->LRL);
for (ac = 0; ac < AC_COUNT; ac++) {
WLC_WME_RETRY_SHORT_SET(wlc, ac, wlc->SRL);
int ac;
wlc->LRL = (u16) val;
- wlc_bmac_retrylimit_upd(wlc->hw, wlc->SRL, wlc->LRL);
+ brcms_b_retrylimit_upd(wlc->hw, wlc->SRL, wlc->LRL);
for (ac = 0; ac < AC_COUNT; ac++) {
WLC_WME_RETRY_LONG_SET(wlc, ac, wlc->LRL);
#endif /* BCMDBG */
/* Read mac stats from contiguous shared memory */
- wlc_bmac_copyfrom_shm(wlc->hw, M_UCODE_MACSTAT,
- &macstats, sizeof(macstat_t));
+ brcms_b_copyfrom_shm(wlc->hw, M_UCODE_MACSTAT,
+ &macstats, sizeof(macstat_t));
#ifdef BCMDBG
/* check for rx fifo 0 overflow */
static u16 wlc_rate_shm_offset(struct wlc_info *wlc, u8 rate)
{
- return wlc_bmac_rate_shm_offset(wlc->hw, rate);
+ return brcms_b_rate_shm_offset(wlc->hw, rate);
}
/* Callback for device removed */
/* Bump up pending count for if not using rpc. If rpc is used, this will be handled
- * in wlc_bmac_txfifo()
+ * in brcms_b_txfifo()
*/
if (commit) {
TXPKTPENDINC(wlc, fifo, txpktpend);
* |<---------- tsf_h ----------->||<--- tsf_l -->||<-RxTSFTime ->|
*
* The RxTSFTime are the lowest 16 bits and provided by the ucode. The
- * tsf_l is filled in by wlc_bmac_recv, which is done earlier in the
+ * tsf_l is filled in by brcms_b_recv, which is done earlier in the
* receive call sequence after rx interrupt. Only the higher 16 bits
* are used. Finally, the tsf_h is read from the tsf register.
*/
u32 tsf_h, tsf_l;
u16 rx_tsf_0_15, rx_tsf_16_31;
- wlc_bmac_read_tsf(wlc->hw, &tsf_l, &tsf_h);
+ brcms_b_read_tsf(wlc->hw, &tsf_l, &tsf_h);
rx_tsf_16_31 = (u16)(tsf_l >> 16);
rx_tsf_0_15 = rxh->rxhdr.RxTSFTime;
wlc_suspend_mac_and_wait(wlc);
/* write the probe response into the template region */
- wlc_bmac_write_template_ram(wlc->hw, T_PRS_TPL_BASE,
+ brcms_b_write_template_ram(wlc->hw, T_PRS_TPL_BASE,
(len + 3) & ~3, prb_resp);
/* write the length of the probe response frame (+PLCP/-FCS) */
*/
u16 wlc_read_shm(struct wlc_info *wlc, uint offset)
{
- return wlc_bmac_read_shm(wlc->hw, offset);
+ return brcms_b_read_shm(wlc->hw, offset);
}
/* Write a single u16 to shared memory.
*/
void wlc_write_shm(struct wlc_info *wlc, uint offset, u16 v)
{
- wlc_bmac_write_shm(wlc->hw, offset, v);
+ brcms_b_write_shm(wlc->hw, offset, v);
}
/* Copy a buffer to shared memory.
if (len <= 0 || (offset & 1) || (len & 1))
return;
- wlc_bmac_copyto_objmem(wlc->hw, offset, buf, len, OBJADDR_SHM_SEL);
+ brcms_b_copyto_objmem(wlc->hw, offset, buf, len, OBJADDR_SHM_SEL);
}
/* wrapper BMAC functions to for HIGH driver access */
void wlc_mctrl(struct wlc_info *wlc, u32 mask, u32 val)
{
- wlc_bmac_mctrl(wlc->hw, mask, val);
+ brcms_b_mctrl(wlc->hw, mask, val);
}
void wlc_mhf(struct wlc_info *wlc, u8 idx, u16 mask, u16 val, int bands)
{
- wlc_bmac_mhf(wlc->hw, idx, mask, val, bands);
+ brcms_b_mhf(wlc->hw, idx, mask, val, bands);
}
int wlc_xmtfifo_sz_get(struct wlc_info *wlc, uint fifo, uint *blocks)
{
- return wlc_bmac_xmtfifo_sz_get(wlc->hw, fifo, blocks);
+ return brcms_b_xmtfifo_sz_get(wlc->hw, fifo, blocks);
}
void wlc_write_template_ram(struct wlc_info *wlc, int offset, int len,
void *buf)
{
- wlc_bmac_write_template_ram(wlc->hw, offset, len, buf);
+ brcms_b_write_template_ram(wlc->hw, offset, len, buf);
}
void wlc_write_hw_bcntemplates(struct wlc_info *wlc, void *bcn, int len,
bool both)
{
- wlc_bmac_write_hw_bcntemplates(wlc->hw, bcn, len, both);
+ brcms_b_write_hw_bcntemplates(wlc->hw, bcn, len, both);
}
void
wlc_set_addrmatch(struct wlc_info *wlc, int match_reg_offset,
const u8 *addr)
{
- wlc_bmac_set_addrmatch(wlc->hw, match_reg_offset, addr);
+ brcms_b_set_addrmatch(wlc->hw, match_reg_offset, addr);
if (match_reg_offset == RCM_BSSID_OFFSET)
memcpy(wlc->cfg->BSSID, addr, ETH_ALEN);
}
void wlc_pllreq(struct wlc_info *wlc, bool set, mbool req_bit)
{
- wlc_bmac_pllreq(wlc->hw, set, req_bit);
+ brcms_b_pllreq(wlc->hw, set, req_bit);
}
void wlc_reset_bmac_done(struct wlc_info *wlc)
projects / GitHub / MotorolaMobilityLLC / kernel-slsi.git / commitdiff