drm/i915: set FDI RX TU size to match transmit size

This allows FDI error checking to work.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 358c30127f1ab8ef1d052571a6fcc94c560afe8e..c31a64daf479a2f3eeeff6aa4638a16bf4268d31 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1857,12 +1857,18 @@ static void ironlake_fdi_enable(struct drm_crtc *crtc)
        int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
        int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
        int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
+       int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
        u32 temp;
        u32 pipe_bpc;
+       u32 tx_size;
 
        temp = I915_READ(pipeconf_reg);
        pipe_bpc = temp & PIPE_BPC_MASK;
 
+       /* Write the TU size bits so error detection works */
+       tx_size = I915_READ(data_m1_reg) & TU_SIZE_MASK;
+       I915_WRITE(FDI_RXA_TUSIZE1, tx_size);
+
        /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
        temp = I915_READ(fdi_rx_reg);
        /*