ARM: socfpga: dts: Correct the parent clock for l3_sp_clk and dbg_clk

The l3_sp_clk's parent should be the l3_mp_clk. This will account for
the extra divider that is present for the l3_mp_clk.

The dbg_clk's parent should be the dbg_at_clk. This will account for
the extra divider that is present for the dbg_at_clk.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>

diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 1e3c833dfbd26176d0081292678206bd71a89eff..7860935ae3a2034443946b4eb36487dce956e920 100644 (file)
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -318,7 +318,7 @@
                                        l3_sp_clk: l3_sp_clk {
                                                #clock-cells = <0>;
                                                compatible = "altr,socfpga-gate-clk";
-                                               clocks = <&mainclk>;
+                                               clocks = <&l3_mp_clk>;
                                                div-reg = <0x64 2 2>;
                                        };
 
@@ -349,7 +349,7 @@
                                        dbg_clk: dbg_clk {
                                                #clock-cells = <0>;
                                                compatible = "altr,socfpga-gate-clk";
-                                               clocks = <&dbg_base_clk>;
+                                               clocks = <&dbg_at_clk>;
                                                div-reg = <0x68 2 2>;
                                                clk-gate = <0x60 5>;
                                        };