drm/nouveau/therm: make sure the temperature settings are sane on nv84+
authorMartin Peres <martin.peres@free.fr>
Sun, 24 Aug 2014 21:15:10 +0000 (23:15 +0200)
committerBen Skeggs <bskeggs@redhat.com>
Mon, 15 Sep 2014 12:25:02 +0000 (22:25 +1000)
One of my nv92 has a calibrated internal sensor but it displays 0°C
as the default values use sw calibration values to force the temperature
to 0.

Since we cannot read the temperature from the adt7473 present on this board,
let's re-enable the internal reading!

Signed-off-by: Martin Peres <martin.peres@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drivers/gpu/drm/nouveau/core/subdev/therm/nv84.c
drivers/gpu/drm/nouveau/core/subdev/therm/nva3.c
drivers/gpu/drm/nouveau/core/subdev/therm/nvd0.c
drivers/gpu/drm/nouveau/core/subdev/therm/priv.h

index 1d15c52fad0c3030e4a2c103a2a69b3529aa1b19..38b16d92f420708559368fc9b4dabcba42533928 100644 (file)
@@ -24,6 +24,7 @@
  */
 
 #include "priv.h"
+#include <subdev/fuse.h>
 
 struct nv84_therm_priv {
        struct nouveau_therm_priv base;
@@ -35,6 +36,19 @@ nv84_temp_get(struct nouveau_therm *therm)
        return nv_rd32(therm, 0x20400);
 }
 
+void
+nv84_sensor_setup(struct nouveau_therm *therm)
+{
+       struct nouveau_fuse *fuse = nouveau_fuse(therm);
+
+       /* enable temperature reading for cards with insane defaults */
+       if (nv_ro32(fuse, 0x1a8) == 1) {
+               nv_mask(therm, 0x20008, 0x80008000, 0x80000000);
+               nv_mask(therm, 0x2000c, 0x80000003, 0x00000000);
+               mdelay(20); /* wait for the temperature to stabilize */
+       }
+}
+
 static void
 nv84_therm_program_alarms(struct nouveau_therm *therm)
 {
@@ -170,6 +184,21 @@ nv84_therm_intr(struct nouveau_subdev *subdev)
        spin_unlock_irqrestore(&priv->sensor.alarm_program_lock, flags);
 }
 
+static int
+nv84_therm_init(struct nouveau_object *object)
+{
+       struct nv84_therm_priv *priv = (void *)object;
+       int ret;
+
+       ret = nouveau_therm_init(&priv->base.base);
+       if (ret)
+               return ret;
+
+       nv84_sensor_setup(&priv->base.base);
+
+       return 0;
+}
+
 static int
 nv84_therm_ctor(struct nouveau_object *parent,
                struct nouveau_object *engine,
@@ -228,7 +257,7 @@ nv84_therm_oclass = {
        .ofuncs = &(struct nouveau_ofuncs) {
                .ctor = nv84_therm_ctor,
                .dtor = _nouveau_therm_dtor,
-               .init = _nouveau_therm_init,
+               .init = nv84_therm_init,
                .fini = nv84_therm_fini,
        },
 };
index 0478b2e3fb1de76ee34e40a56e0d6209ffff1d60..7893357a7e9f474c1d777527933406a27c4f3330 100644 (file)
@@ -51,6 +51,8 @@ nva3_therm_init(struct nouveau_object *object)
        if (ret)
                return ret;
 
+       nv84_sensor_setup(&priv->base.base);
+
        /* enable fan tach, count revolutions per-second */
        nv_mask(priv, 0x00e720, 0x00000003, 0x00000002);
        if (tach->func != DCB_GPIO_UNUSED) {
index 04bb84fab170650cce1a23da5ff636249b6d1a62..b70f7cc649b87a8973456ca4a5f4f3bd28f4f3b6 100644 (file)
@@ -150,6 +150,8 @@ nvd0_therm_ctor(struct nouveau_object *parent,
        if (ret)
                return ret;
 
+       nv84_sensor_setup(&priv->base.base);
+
        priv->base.base.pwm_ctrl = nvd0_fan_pwm_ctrl;
        priv->base.base.pwm_get = nvd0_fan_pwm_get;
        priv->base.base.pwm_set = nvd0_fan_pwm_set;
index 4262d1d7a13d767bfa7e7a64d2e480527a39ff0d..7dba8c281a0b3fe8a19ec2d93bb38c104f811ec7 100644 (file)
@@ -145,6 +145,7 @@ int nv50_fan_pwm_get(struct nouveau_therm *, int, u32 *, u32 *);
 int nv50_fan_pwm_set(struct nouveau_therm *, int, u32, u32);
 int nv50_fan_pwm_clock(struct nouveau_therm *, int);
 int nv84_temp_get(struct nouveau_therm *therm);
+void nv84_sensor_setup(struct nouveau_therm *therm);
 int nv84_therm_fini(struct nouveau_object *object, bool suspend);
 
 int nva3_therm_fan_sense(struct nouveau_therm *);