drm/i915: HSW_BLC_PWM2_CTL doesn't exist on BDW

So don't write it, otherwise we will trigger unclaimed register
errors.

Testcase: igt/pm_rpm/rte
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 9064dd9805cd63f42f10343fdb7f64e103866006..06566d6c328fed531d1da8b0bf4b229425c8e966 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7326,8 +7326,9 @@ static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
        WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
        WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
             "CPU PWM1 enabled\n");
-       WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
-            "CPU PWM2 enabled\n");
+       if (IS_HASWELL(dev))
+               WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
+                    "CPU PWM2 enabled\n");
        WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
             "PCH PWM1 enabled\n");
        WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,