msm: iomap: Addresses and IRQs for 2nd GFX core IOMMU
authorStepan Moskovchenko <stepanm@codeaurora.org>
Sat, 13 Nov 2010 03:29:48 +0000 (19:29 -0800)
committerDaniel Walker <dwalker@codeaurora.org>
Tue, 30 Nov 2010 21:53:45 +0000 (13:53 -0800)
Add register addresses and IRQ numbers for the IOMMU used
for the second 2D graphics core.

Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
arch/arm/mach-msm/include/mach/irqs-8x60.h
arch/arm/mach-msm/include/mach/msm_iomap-8x60.h

index 36074cfc9ad287ef5bd2a2d90cb0f10e0ee1446f..f65841c74c0b9c9e9d1d23201361cc398771ee9e 100644 (file)
 #define GSBI11_QUP_IRQ                         (GIC_SPI_START + 194)
 #define INT_UART12DM_IRQ                       (GIC_SPI_START + 195)
 #define GSBI12_QUP_IRQ                         (GIC_SPI_START + 196)
-/*SPI 197 to 216 arent used in 8x60*/
+
+/*SPI 197 to 209 arent used in 8x60*/
+#define SMMU_GFX2D1_CB_SC_SECURE_IRQ            (GIC_SPI_START + 210)
+#define SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ        (GIC_SPI_START + 211)
+
+/*SPI 212 to 216 arent used in 8x60*/
 #define SMPSS_SPARE_1                          (GIC_SPI_START + 217)
 #define SMPSS_SPARE_2                          (GIC_SPI_START + 218)
 #define SMPSS_SPARE_3                          (GIC_SPI_START + 219)
index 45bab50e3ee6c1a46d23bf3f02a1b373173baf93..7c43a9bff1a9bf17df822109c97e9c807b94b7cf 100644 (file)
@@ -98,4 +98,7 @@
 #define MSM_IOMMU_GFX2D0_PHYS  0x07D00000
 #define MSM_IOMMU_GFX2D0_SIZE  SZ_1M
 
+#define MSM_IOMMU_GFX2D1_PHYS  0x07E00000
+#define MSM_IOMMU_GFX2D1_SIZE  SZ_1M
+
 #endif