The OSC_FREQ field of the OSC_CTRL register uses the value 12 for an
oscillator frequency of 26 MHz, not 260 MHz. This isn't really critical
because I don't think boards with such an oscillator have ever existed,
much less been supported upstream.
Signed-off-by: Thierry Reding <treding@nvidia.com>
[5] = 38400000,
[8] = 12000000,
[9] = 48000000,
- [12] = 260000000,
+ [12] = 26000000,
};
#define MASK(x) (BIT(x) - 1)
[5] = 38400000,
[8] = 12000000,
[9] = 48000000,
- [12] = 260000000,
+ [12] = 26000000,
};
static struct div_nmp pllxc_nmp = {
[5] = 38400000,
[8] = 12000000,
[9] = 48000000,
- [12] = 260000000,
+ [12] = 26000000,
};
static struct tegra_devclk devclks[] __initdata = {