Merge branch 'linus' into oprofile

Conflicts:
	arch/x86/kernel/apic_32.c
	include/linux/pci_ids.h

diff --cc arch/x86/kernel/apic_32.c
index 0ff576d026a4870ae0933933f95262334a4ea544,a91c57cb666a3c752295875ac4ff14298502f5b7..21c831d96af3d8f8ef63e6403f56fd0e71f5730c
--- 1/arch/x86/kernel/apic_32.c
--- 2/arch/x86/kernel/apic_32.c
+++ b/arch/x86/kernel/apic_32.c
@@@ -240,6 -290,36 +290,40 @@@ static void __setup_APIC_LVTT(unsigned 
                apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
  }
  
+ /*
+  * Setup extended LVT, AMD specific (K8, family 10h)
+  *
+  * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
+  * MCE interrupts are supported. Thus MCE offset must be set to 0.
++ *
++ * If mask=1, the LVT entry does not generate interrupts while mask=0
++ * enables the vector. See also the BKDGs.
+  */
+ 
+ #define APIC_EILVT_LVTOFF_MCE 0
+ #define APIC_EILVT_LVTOFF_IBS 1
+ 
+ static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)
+ {
+       unsigned long reg = (lvt_off << 4) + APIC_EILVT0;
+       unsigned int  v   = (mask << 16) | (msg_type << 8) | vector;
+ 
+       apic_write(reg, v);
+ }
+ 
+ u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask)
+ {
+       setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask);
+       return APIC_EILVT_LVTOFF_MCE;
+ }
+ 
+ u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)
+ {
+       setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);
+       return APIC_EILVT_LVTOFF_IBS;
+ }
++EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs);
+ 
  /*
   * Program the next event, relative to now
   */

diff --cc arch/x86/kernel/apic_64.c
Simple merge