ARM: EXYNOS: DT Support for SATA and SATA PHY
authorVasanth Ananthan <vasanthananthan@gmail.com>
Tue, 20 Nov 2012 12:02:11 +0000 (21:02 +0900)
committerKukjin Kim <kgene.kim@samsung.com>
Tue, 20 Nov 2012 12:02:17 +0000 (21:02 +0900)
This patch adds Device Nodes for SATA and SATA PHY device.

Signed-off-by: Vasanth Ananthan <vasanth.a@samsung.com>
[kgene.kim@samsung.com: removed address definitions as per comments]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Documentation/devicetree/bindings/ata/exynos-sata-phy.txt [new file with mode: 0644]
Documentation/devicetree/bindings/ata/exynos-sata.txt [new file with mode: 0644]
arch/arm/boot/dts/exynos5250-smdk5250.dts
arch/arm/boot/dts/exynos5250.dtsi
arch/arm/mach-exynos/mach-exynos5-dt.c

diff --git a/Documentation/devicetree/bindings/ata/exynos-sata-phy.txt b/Documentation/devicetree/bindings/ata/exynos-sata-phy.txt
new file mode 100644 (file)
index 0000000..37824fa
--- /dev/null
@@ -0,0 +1,14 @@
+* Samsung SATA PHY Controller
+
+SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
+Each SATA PHY controller should have its own node.
+
+Required properties:
+- compatible        : compatible list, contains "samsung,exynos5-sata-phy"
+- reg               : <registers mapping>
+
+Example:
+        sata@ffe07000 {
+                compatible = "samsung,exynos5-sata-phy";
+                reg = <0xffe07000 0x1000>;
+        };
diff --git a/Documentation/devicetree/bindings/ata/exynos-sata.txt b/Documentation/devicetree/bindings/ata/exynos-sata.txt
new file mode 100644 (file)
index 0000000..0849f10
--- /dev/null
@@ -0,0 +1,17 @@
+* Samsung AHCI SATA Controller
+
+SATA nodes are defined to describe on-chip Serial ATA controllers.
+Each SATA controller should have its own node.
+
+Required properties:
+- compatible        : compatible list, contains "samsung,exynos5-sata"
+- interrupts        : <interrupt mapping for SATA IRQ>
+- reg               : <registers mapping>
+- samsung,sata-freq : <frequency in MHz>
+
+Example:
+        sata@ffe08000 {
+                compatible = "samsung,exynos5-sata";
+                reg = <0xffe08000 0x1000>;
+                interrupts = <115>;
+        };
index 21d4ccdb0a5aa9a5067cc110588ebe98ba10d29e..3f8c2ab1d0388c11ae481b49a5dfefb93c320991 100644 (file)
                };
        };
 
+       i2c@121D0000 {
+               samsung,i2c-sda-delay = <100>;
+               samsung,i2c-max-bus-freq = <40000>;
+               samsung,i2c-slave-addr = <0x38>;
+
+               sata-phy {
+                       compatible = "samsung,sata-phy";
+                       reg = <0x38>;
+               };
+       };
+
+       sata@122F0000 {
+               samsung,sata-freq = <66>;
+       };
+
        i2c@12C80000 {
                status = "disabled";
        };
index 670dfdb01a09c66aa2b5c0e3c6c923304e7a61bd..e913525a48142945b1a2220edbf0d78bfc6f9d43 100644 (file)
                interrupts = <0 54 0>;
        };
 
+       sata@122F0000 {
+               compatible = "samsung,exynos5-sata-ahci";
+               reg = <0x122F0000 0x1ff>;
+               interrupts = <0 115 0>;
+       };
+
+       sata-phy@12170000 {
+               compatible = "samsung,exynos5-sata-phy";
+               reg = <0x12170000 0x1ff>;
+       };
+
        i2c@12C60000 {
                compatible = "samsung,s3c2440-i2c";
                reg = <0x12C60000 0x100>;
                #size-cells = <0>;
        };
 
+       i2c@121D0000 {
+                compatible = "samsung,exynos5-sata-phy-i2c";
+                reg = <0x121D0000 0x100>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+       };
+
        spi_0: spi@12d20000 {
                compatible = "samsung,exynos4210-spi";
                reg = <0x12d20000 0x100>;
index 4c0f3369abdfa41b974fd7ac063c7db647d9a119..a88c19f5efccd0f60e6b0e6561661685e2195391 100644 (file)
@@ -64,6 +64,12 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
                                "exynos4210-spi.1", NULL),
        OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI2,
                                "exynos4210-spi.2", NULL),
+       OF_DEV_AUXDATA("samsung,exynos5-sata-ahci", 0x122F0000,
+                               "exynos5-sata", NULL),
+       OF_DEV_AUXDATA("samsung,exynos5-sata-phy", 0x12170000,
+                               "exynos5-sata-phy", NULL),
+       OF_DEV_AUXDATA("samsung,exynos5-sata-phy-i2c", 0x121D0000,
+                               "exynos5-sata-phy-i2c", NULL),
        OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
        OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
        OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),