drm/amdgpu: add SMU 7.1.1 register headers
authorAlex Deucher <alexander.deucher@amd.com>
Thu, 16 Apr 2015 19:30:46 +0000 (15:30 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 4 Jun 2015 01:03:05 +0000 (21:03 -0400)
These are register headers for the SMU (System Management Unit)
block on the GPU.

Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Jammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_d.h [new file with mode: 0644]
drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_enum.h [new file with mode: 0644]
drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h [new file with mode: 0644]

diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_d.h
new file mode 100644 (file)
index 0000000..3014d4a
--- /dev/null
@@ -0,0 +1,1123 @@
+/*
+ * SMU_7_1_1 Register documentation
+ *
+ * Copyright (C) 2014  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef SMU_7_1_1_D_H
+#define SMU_7_1_1_D_H
+
+#define mmGCK_SMC_IND_INDEX                                                     0x80
+#define mmGCK0_GCK_SMC_IND_INDEX                                                0x80
+#define mmGCK1_GCK_SMC_IND_INDEX                                                0x82
+#define mmGCK2_GCK_SMC_IND_INDEX                                                0x84
+#define mmGCK3_GCK_SMC_IND_INDEX                                                0x86
+#define mmGCK_SMC_IND_DATA                                                      0x81
+#define mmGCK0_GCK_SMC_IND_DATA                                                 0x81
+#define mmGCK1_GCK_SMC_IND_DATA                                                 0x83
+#define mmGCK2_GCK_SMC_IND_DATA                                                 0x85
+#define mmGCK3_GCK_SMC_IND_DATA                                                 0x87
+#define ixCG_DCLK_CNTL                                                          0xc050009c
+#define ixCG_DCLK_STATUS                                                        0xc05000a0
+#define ixCG_VCLK_CNTL                                                          0xc05000a4
+#define ixCG_VCLK_STATUS                                                        0xc05000a8
+#define ixCG_ECLK_CNTL                                                          0xc05000ac
+#define ixCG_ECLK_STATUS                                                        0xc05000b0
+#define ixCG_ACLK_CNTL                                                          0xc05000dc
+#define ixGCK_DFS_BYPASS_CNTL                                                   0xc0500118
+#define ixCG_SPLL_FUNC_CNTL                                                     0xc0500140
+#define ixCG_SPLL_FUNC_CNTL_2                                                   0xc0500144
+#define ixCG_SPLL_FUNC_CNTL_3                                                   0xc0500148
+#define ixCG_SPLL_FUNC_CNTL_4                                                   0xc050014c
+#define ixCG_SPLL_FUNC_CNTL_5                                                   0xc0500150
+#define ixCG_SPLL_FUNC_CNTL_6                                                   0xc0500154
+#define ixCG_SPLL_FUNC_CNTL_7                                                   0xc0500158
+#define ixSPLL_CNTL_MODE                                                        0xc0500160
+#define ixCG_SPLL_SPREAD_SPECTRUM                                               0xc0500164
+#define ixCG_SPLL_SPREAD_SPECTRUM_2                                             0xc0500168
+#define ixMPLL_BYPASSCLK_SEL                                                    0xc050019c
+#define ixCG_CLKPIN_CNTL                                                        0xc05001a0
+#define ixCG_CLKPIN_CNTL_2                                                      0xc05001a4
+#define ixCG_CLKPIN_CNTL_DC                                                     0xc0500204
+#define ixTHM_CLK_CNTL                                                          0xc05001a8
+#define ixMISC_CLK_CTRL                                                         0xc05001ac
+#define ixGCK_PLL_TEST_CNTL                                                     0xc05001c0
+#define ixGCK_PLL_TEST_CNTL_2                                                   0xc05001c4
+#define ixGCK_ADFS_CLK_BYPASS_CNTL1                                             0xc05001c8
+#define mmSMC_IND_INDEX                                                         0x80
+#define mmSMC0_SMC_IND_INDEX                                                    0x80
+#define mmSMC1_SMC_IND_INDEX                                                    0x82
+#define mmSMC2_SMC_IND_INDEX                                                    0x84
+#define mmSMC3_SMC_IND_INDEX                                                    0x86
+#define mmSMC_IND_DATA                                                          0x81
+#define mmSMC0_SMC_IND_DATA                                                     0x81
+#define mmSMC1_SMC_IND_DATA                                                     0x83
+#define mmSMC2_SMC_IND_DATA                                                     0x85
+#define mmSMC3_SMC_IND_DATA                                                     0x87
+#define mmSMC_IND_INDEX_0                                                       0x80
+#define mmSMC_IND_DATA_0                                                        0x81
+#define mmSMC_IND_INDEX_1                                                       0x82
+#define mmSMC_IND_DATA_1                                                        0x83
+#define mmSMC_IND_INDEX_2                                                       0x84
+#define mmSMC_IND_DATA_2                                                        0x85
+#define mmSMC_IND_INDEX_3                                                       0x86
+#define mmSMC_IND_DATA_3                                                        0x87
+#define mmSMC_IND_INDEX_4                                                       0x88
+#define mmSMC_IND_DATA_4                                                        0x89
+#define mmSMC_IND_INDEX_5                                                       0x8a
+#define mmSMC_IND_DATA_5                                                        0x8b
+#define mmSMC_IND_INDEX_6                                                       0x8c
+#define mmSMC_IND_DATA_6                                                        0x8d
+#define mmSMC_IND_INDEX_7                                                       0x8e
+#define mmSMC_IND_DATA_7                                                        0x8f
+#define mmSMC_IND_ACCESS_CNTL                                                   0x92
+#define mmSMC_MESSAGE_0                                                         0x94
+#define mmSMC_RESP_0                                                            0x95
+#define mmSMC_MESSAGE_1                                                         0x96
+#define mmSMC_RESP_1                                                            0x97
+#define mmSMC_MESSAGE_2                                                         0x98
+#define mmSMC_RESP_2                                                            0x99
+#define mmSMC_MESSAGE_3                                                         0x9a
+#define mmSMC_RESP_3                                                            0x9b
+#define mmSMC_MESSAGE_4                                                         0x9c
+#define mmSMC_RESP_4                                                            0x9d
+#define mmSMC_MESSAGE_5                                                         0x9e
+#define mmSMC_RESP_5                                                            0x9f
+#define mmSMC_MESSAGE_6                                                         0xa0
+#define mmSMC_RESP_6                                                            0xa1
+#define mmSMC_MESSAGE_7                                                         0xa2
+#define mmSMC_RESP_7                                                            0xa3
+#define mmSMC_MSG_ARG_0                                                         0xa4
+#define mmSMC_MSG_ARG_1                                                         0xa5
+#define mmSMC_MSG_ARG_2                                                         0xa6
+#define mmSMC_MSG_ARG_3                                                         0xa7
+#define mmSMC_MSG_ARG_4                                                         0xa8
+#define mmSMC_MSG_ARG_5                                                         0xa9
+#define mmSMC_MSG_ARG_6                                                         0xaa
+#define mmSMC_MSG_ARG_7                                                         0xab
+#define mmSMC_MESSAGE_8                                                         0xb5
+#define mmSMC_RESP_8                                                            0xb6
+#define mmSMC_MESSAGE_9                                                         0xb7
+#define mmSMC_RESP_9                                                            0xb8
+#define mmSMC_MESSAGE_10                                                        0xb9
+#define mmSMC_RESP_10                                                           0xba
+#define mmSMC_MESSAGE_11                                                        0xbb
+#define mmSMC_RESP_11                                                           0xbc
+#define mmSMC_MSG_ARG_8                                                         0xbd
+#define mmSMC_MSG_ARG_9                                                         0xbe
+#define mmSMC_MSG_ARG_10                                                        0xbf
+#define mmSMC_MSG_ARG_11                                                        0x93
+#define ixSMC_SYSCON_RESET_CNTL                                                 0x80000000
+#define ixSMC_SYSCON_CLOCK_CNTL_0                                               0x80000004
+#define ixSMC_SYSCON_CLOCK_CNTL_1                                               0x80000008
+#define ixSMC_SYSCON_CLOCK_CNTL_2                                               0x8000000c
+#define ixSMC_SYSCON_MISC_CNTL                                                  0x80000010
+#define ixSMC_SYSCON_MSG_ARG_0                                                  0x80000068
+#define ixSMC_PC_C                                                              0x80000370
+#define ixSMC_SCRATCH9                                                          0x80000424
+#define mmGPIOPAD_SW_INT_STAT                                                   0x180
+#define mmGPIOPAD_STRENGTH                                                      0x181
+#define mmGPIOPAD_MASK                                                          0x182
+#define mmGPIOPAD_A                                                             0x183
+#define mmGPIOPAD_EN                                                            0x184
+#define mmGPIOPAD_Y                                                             0x185
+#define mmGPIOPAD_PINSTRAPS                                                     0x186
+#define mmGPIOPAD_INT_STAT_EN                                                   0x187
+#define mmGPIOPAD_INT_STAT                                                      0x188
+#define mmGPIOPAD_INT_STAT_AK                                                   0x189
+#define mmGPIOPAD_INT_EN                                                        0x18a
+#define mmGPIOPAD_INT_TYPE                                                      0x18b
+#define mmGPIOPAD_INT_POLARITY                                                  0x18c
+#define mmGPIOPAD_EXTERN_TRIG_CNTL                                              0x18d
+#define mmGPIOPAD_RCVR_SEL                                                      0x191
+#define mmGPIOPAD_PU_EN                                                         0x192
+#define mmGPIOPAD_PD_EN                                                         0x193
+#define mmCG_FPS_CNT                                                            0x1b6
+#define mmSMU_IND_INDEX_0                                                       0x1a6
+#define mmSMU_IND_DATA_0                                                        0x1a7
+#define mmSMU_IND_INDEX_1                                                       0x1a8
+#define mmSMU_IND_DATA_1                                                        0x1a9
+#define mmSMU_IND_INDEX_2                                                       0x1aa
+#define mmSMU_IND_DATA_2                                                        0x1ab
+#define mmSMU_IND_INDEX_3                                                       0x1ac
+#define mmSMU_IND_DATA_3                                                        0x1ad
+#define mmSMU_IND_INDEX_4                                                       0x1ae
+#define mmSMU_IND_DATA_4                                                        0x1af
+#define mmSMU_IND_INDEX_5                                                       0x1b0
+#define mmSMU_IND_DATA_5                                                        0x1b1
+#define mmSMU_IND_INDEX_6                                                       0x1b2
+#define mmSMU_IND_DATA_6                                                        0x1b3
+#define mmSMU_IND_INDEX_7                                                       0x1b4
+#define mmSMU_IND_DATA_7                                                        0x1b5
+#define mmSMU_SMC_IND_INDEX                                                     0x80
+#define mmSMU0_SMU_SMC_IND_INDEX                                                0x80
+#define mmSMU1_SMU_SMC_IND_INDEX                                                0x82
+#define mmSMU2_SMU_SMC_IND_INDEX                                                0x84
+#define mmSMU3_SMU_SMC_IND_INDEX                                                0x86
+#define mmSMU_SMC_IND_DATA                                                      0x81
+#define mmSMU0_SMU_SMC_IND_DATA                                                 0x81
+#define mmSMU1_SMU_SMC_IND_DATA                                                 0x83
+#define mmSMU2_SMU_SMC_IND_DATA                                                 0x85
+#define mmSMU3_SMU_SMC_IND_DATA                                                 0x87
+#define ixRCU_UC_EVENTS                                                         0xc0000004
+#define ixRCU_MISC_CTRL                                                         0xc0000010
+#define ixCC_RCU_FUSES                                                          0xc00c0000
+#define ixCC_SMU_MISC_FUSES                                                     0xc00c0004
+#define ixCC_SCLK_VID_FUSES                                                     0xc00c0008
+#define ixCC_GIO_IOCCFG_FUSES                                                   0xc00c000c
+#define ixCC_GIO_IOC_FUSES                                                      0xc00c0010
+#define ixCC_SMU_TST_EFUSE1_MISC                                                0xc00c001c
+#define ixCC_TST_ID_STRAPS                                                      0xc00c0020
+#define ixCC_FCTRL_FUSES                                                        0xc00c0024
+#define ixCC_HARVEST_FUSES                                                      0xc00c0028
+#define ixSMU_MAIN_PLL_OP_FREQ                                                  0xe0003020
+#define ixSMU_STATUS                                                            0xe0003088
+#define ixSMU_FIRMWARE                                                          0xe00030a4
+#define ixSMU_INPUT_DATA                                                        0xe00030b8
+#define ixSMU_EFUSE_0                                                           0xc0100000
+#define ixMCARB_DRAM_TIMING_TABLE_1                                             0x33018
+#define ixMCARB_DRAM_TIMING_TABLE_2                                             0x3301c
+#define ixMCARB_DRAM_TIMING_TABLE_3                                             0x33020
+#define ixMCARB_DRAM_TIMING_TABLE_4                                             0x33024
+#define ixMCARB_DRAM_TIMING_TABLE_5                                             0x33028
+#define ixMCARB_DRAM_TIMING_TABLE_6                                             0x3302c
+#define ixMCARB_DRAM_TIMING_TABLE_7                                             0x33030
+#define ixMCARB_DRAM_TIMING_TABLE_8                                             0x33034
+#define ixMCARB_DRAM_TIMING_TABLE_9                                             0x33038
+#define ixMCARB_DRAM_TIMING_TABLE_10                                            0x3303c
+#define ixMCARB_DRAM_TIMING_TABLE_11                                            0x33040
+#define ixMCARB_DRAM_TIMING_TABLE_12                                            0x33044
+#define ixMCARB_DRAM_TIMING_TABLE_13                                            0x33048
+#define ixMCARB_DRAM_TIMING_TABLE_14                                            0x3304c
+#define ixMCARB_DRAM_TIMING_TABLE_15                                            0x33050
+#define ixMCARB_DRAM_TIMING_TABLE_16                                            0x33054
+#define ixMCARB_DRAM_TIMING_TABLE_17                                            0x33058
+#define ixMCARB_DRAM_TIMING_TABLE_18                                            0x3305c
+#define ixMCARB_DRAM_TIMING_TABLE_19                                            0x33060
+#define ixMCARB_DRAM_TIMING_TABLE_20                                            0x33064
+#define ixMCARB_DRAM_TIMING_TABLE_21                                            0x33068
+#define ixMCARB_DRAM_TIMING_TABLE_22                                            0x3306c
+#define ixMCARB_DRAM_TIMING_TABLE_23                                            0x33070
+#define ixMCARB_DRAM_TIMING_TABLE_24                                            0x33074
+#define ixMCARB_DRAM_TIMING_TABLE_25                                            0x33078
+#define ixMCARB_DRAM_TIMING_TABLE_26                                            0x3307c
+#define ixMCARB_DRAM_TIMING_TABLE_27                                            0x33080
+#define ixMCARB_DRAM_TIMING_TABLE_28                                            0x33084
+#define ixMCARB_DRAM_TIMING_TABLE_29                                            0x33088
+#define ixMCARB_DRAM_TIMING_TABLE_30                                            0x3308c
+#define ixMCARB_DRAM_TIMING_TABLE_31                                            0x33090
+#define ixMCARB_DRAM_TIMING_TABLE_32                                            0x33094
+#define ixMCARB_DRAM_TIMING_TABLE_33                                            0x33098
+#define ixMCARB_DRAM_TIMING_TABLE_34                                            0x3309c
+#define ixMCARB_DRAM_TIMING_TABLE_35                                            0x330a0
+#define ixMCARB_DRAM_TIMING_TABLE_36                                            0x330a4
+#define ixMCARB_DRAM_TIMING_TABLE_37                                            0x330a8
+#define ixMCARB_DRAM_TIMING_TABLE_38                                            0x330ac
+#define ixMCARB_DRAM_TIMING_TABLE_39                                            0x330b0
+#define ixMCARB_DRAM_TIMING_TABLE_40                                            0x330b4
+#define ixMCARB_DRAM_TIMING_TABLE_41                                            0x330b8
+#define ixMCARB_DRAM_TIMING_TABLE_42                                            0x330bc
+#define ixMCARB_DRAM_TIMING_TABLE_43                                            0x330c0
+#define ixMCARB_DRAM_TIMING_TABLE_44                                            0x330c4
+#define ixMCARB_DRAM_TIMING_TABLE_45                                            0x330c8
+#define ixMCARB_DRAM_TIMING_TABLE_46                                            0x330cc
+#define ixMCARB_DRAM_TIMING_TABLE_47                                            0x330d0
+#define ixMCARB_DRAM_TIMING_TABLE_48                                            0x330d4
+#define ixMCARB_DRAM_TIMING_TABLE_49                                            0x330d8
+#define ixMCARB_DRAM_TIMING_TABLE_50                                            0x330dc
+#define ixMCARB_DRAM_TIMING_TABLE_51                                            0x330e0
+#define ixMCARB_DRAM_TIMING_TABLE_52                                            0x330e4
+#define ixMCARB_DRAM_TIMING_TABLE_53                                            0x330e8
+#define ixMCARB_DRAM_TIMING_TABLE_54                                            0x330ec
+#define ixMCARB_DRAM_TIMING_TABLE_55                                            0x330f0
+#define ixMCARB_DRAM_TIMING_TABLE_56                                            0x330f4
+#define ixMCARB_DRAM_TIMING_TABLE_57                                            0x330f8
+#define ixMCARB_DRAM_TIMING_TABLE_58                                            0x330fc
+#define ixMCARB_DRAM_TIMING_TABLE_59                                            0x33100
+#define ixMCARB_DRAM_TIMING_TABLE_60                                            0x33104
+#define ixMCARB_DRAM_TIMING_TABLE_61                                            0x33108
+#define ixMCARB_DRAM_TIMING_TABLE_62                                            0x3310c
+#define ixMCARB_DRAM_TIMING_TABLE_63                                            0x33110
+#define ixMCARB_DRAM_TIMING_TABLE_64                                            0x33114
+#define ixMCARB_DRAM_TIMING_TABLE_65                                            0x33118
+#define ixMCARB_DRAM_TIMING_TABLE_66                                            0x3311c
+#define ixMCARB_DRAM_TIMING_TABLE_67                                            0x33120
+#define ixMCARB_DRAM_TIMING_TABLE_68                                            0x33124
+#define ixMCARB_DRAM_TIMING_TABLE_69                                            0x33128
+#define ixMCARB_DRAM_TIMING_TABLE_70                                            0x3312c
+#define ixMCARB_DRAM_TIMING_TABLE_71                                            0x33130
+#define ixMCARB_DRAM_TIMING_TABLE_72                                            0x33134
+#define ixMCARB_DRAM_TIMING_TABLE_73                                            0x33138
+#define ixMCARB_DRAM_TIMING_TABLE_74                                            0x3313c
+#define ixMCARB_DRAM_TIMING_TABLE_75                                            0x33140
+#define ixMCARB_DRAM_TIMING_TABLE_76                                            0x33144
+#define ixMCARB_DRAM_TIMING_TABLE_77                                            0x33148
+#define ixMCARB_DRAM_TIMING_TABLE_78                                            0x3314c
+#define ixMCARB_DRAM_TIMING_TABLE_79                                            0x33150
+#define ixMCARB_DRAM_TIMING_TABLE_80                                            0x33154
+#define ixMCARB_DRAM_TIMING_TABLE_81                                            0x33158
+#define ixMCARB_DRAM_TIMING_TABLE_82                                            0x3315c
+#define ixMCARB_DRAM_TIMING_TABLE_83                                            0x33160
+#define ixMCARB_DRAM_TIMING_TABLE_84                                            0x33164
+#define ixMCARB_DRAM_TIMING_TABLE_85                                            0x33168
+#define ixMCARB_DRAM_TIMING_TABLE_86                                            0x3316c
+#define ixMCARB_DRAM_TIMING_TABLE_87                                            0x33170
+#define ixMCARB_DRAM_TIMING_TABLE_88                                            0x33174
+#define ixMCARB_DRAM_TIMING_TABLE_89                                            0x33178
+#define ixMCARB_DRAM_TIMING_TABLE_90                                            0x3317c
+#define ixMCARB_DRAM_TIMING_TABLE_91                                            0x33180
+#define ixMCARB_DRAM_TIMING_TABLE_92                                            0x33184
+#define ixMCARB_DRAM_TIMING_TABLE_93                                            0x33188
+#define ixMCARB_DRAM_TIMING_TABLE_94                                            0x3318c
+#define ixMCARB_DRAM_TIMING_TABLE_95                                            0x33190
+#define ixMCARB_DRAM_TIMING_TABLE_96                                            0x33194
+#define ixMC_REGISTERS_TABLE_1                                                  0x33198
+#define ixMC_REGISTERS_TABLE_2                                                  0x3319c
+#define ixMC_REGISTERS_TABLE_3                                                  0x331a0
+#define ixMC_REGISTERS_TABLE_4                                                  0x331a4
+#define ixMC_REGISTERS_TABLE_5                                                  0x331a8
+#define ixMC_REGISTERS_TABLE_6                                                  0x331ac
+#define ixMC_REGISTERS_TABLE_7                                                  0x331b0
+#define ixMC_REGISTERS_TABLE_8                                                  0x331b4
+#define ixMC_REGISTERS_TABLE_9                                                  0x331b8
+#define ixMC_REGISTERS_TABLE_10                                                 0x331bc
+#define ixMC_REGISTERS_TABLE_11                                                 0x331c0
+#define ixMC_REGISTERS_TABLE_12                                                 0x331c4
+#define ixMC_REGISTERS_TABLE_13                                                 0x331c8
+#define ixMC_REGISTERS_TABLE_14                                                 0x331cc
+#define ixMC_REGISTERS_TABLE_15                                                 0x331d0
+#define ixMC_REGISTERS_TABLE_16                                                 0x331d4
+#define ixMC_REGISTERS_TABLE_17                                                 0x331d8
+#define ixMC_REGISTERS_TABLE_18                                                 0x331dc
+#define ixMC_REGISTERS_TABLE_19                                                 0x331e0
+#define ixMC_REGISTERS_TABLE_20                                                 0x331e4
+#define ixMC_REGISTERS_TABLE_21                                                 0x331e8
+#define ixMC_REGISTERS_TABLE_22                                                 0x331ec
+#define ixMC_REGISTERS_TABLE_23                                                 0x331f0
+#define ixMC_REGISTERS_TABLE_24                                                 0x331f4
+#define ixMC_REGISTERS_TABLE_25                                                 0x331f8
+#define ixMC_REGISTERS_TABLE_26                                                 0x331fc
+#define ixMC_REGISTERS_TABLE_27                                                 0x33200
+#define ixMC_REGISTERS_TABLE_28                                                 0x33204
+#define ixMC_REGISTERS_TABLE_29                                                 0x33208
+#define ixMC_REGISTERS_TABLE_30                                                 0x3320c
+#define ixMC_REGISTERS_TABLE_31                                                 0x33210
+#define ixMC_REGISTERS_TABLE_32                                                 0x33214
+#define ixMC_REGISTERS_TABLE_33                                                 0x33218
+#define ixMC_REGISTERS_TABLE_34                                                 0x3321c
+#define ixMC_REGISTERS_TABLE_35                                                 0x33220
+#define ixMC_REGISTERS_TABLE_36                                                 0x33224
+#define ixMC_REGISTERS_TABLE_37                                                 0x33228
+#define ixMC_REGISTERS_TABLE_38                                                 0x3322c
+#define ixMC_REGISTERS_TABLE_39                                                 0x33230
+#define ixMC_REGISTERS_TABLE_40                                                 0x33234
+#define ixMC_REGISTERS_TABLE_41                                                 0x33238
+#define ixMC_REGISTERS_TABLE_42                                                 0x3323c
+#define ixMC_REGISTERS_TABLE_43                                                 0x33240
+#define ixMC_REGISTERS_TABLE_44                                                 0x33244
+#define ixMC_REGISTERS_TABLE_45                                                 0x33248
+#define ixMC_REGISTERS_TABLE_46                                                 0x3324c
+#define ixMC_REGISTERS_TABLE_47                                                 0x33250
+#define ixMC_REGISTERS_TABLE_48                                                 0x33254
+#define ixMC_REGISTERS_TABLE_49                                                 0x33258
+#define ixMC_REGISTERS_TABLE_50                                                 0x3325c
+#define ixMC_REGISTERS_TABLE_51                                                 0x33260
+#define ixMC_REGISTERS_TABLE_52                                                 0x33264
+#define ixMC_REGISTERS_TABLE_53                                                 0x33268
+#define ixMC_REGISTERS_TABLE_54                                                 0x3326c
+#define ixMC_REGISTERS_TABLE_55                                                 0x33270
+#define ixMC_REGISTERS_TABLE_56                                                 0x33274
+#define ixMC_REGISTERS_TABLE_57                                                 0x33278
+#define ixMC_REGISTERS_TABLE_58                                                 0x3327c
+#define ixMC_REGISTERS_TABLE_59                                                 0x33280
+#define ixMC_REGISTERS_TABLE_60                                                 0x33284
+#define ixMC_REGISTERS_TABLE_61                                                 0x33288
+#define ixMC_REGISTERS_TABLE_62                                                 0x3328c
+#define ixMC_REGISTERS_TABLE_63                                                 0x33290
+#define ixMC_REGISTERS_TABLE_64                                                 0x33294
+#define ixMC_REGISTERS_TABLE_65                                                 0x33298
+#define ixMC_REGISTERS_TABLE_66                                                 0x3329c
+#define ixMC_REGISTERS_TABLE_67                                                 0x332a0
+#define ixMC_REGISTERS_TABLE_68                                                 0x332a4
+#define ixMC_REGISTERS_TABLE_69                                                 0x332a8
+#define ixMC_REGISTERS_TABLE_70                                                 0x332ac
+#define ixMC_REGISTERS_TABLE_71                                                 0x332b0
+#define ixMC_REGISTERS_TABLE_72                                                 0x332b4
+#define ixMC_REGISTERS_TABLE_73                                                 0x332b8
+#define ixMC_REGISTERS_TABLE_74                                                 0x332bc
+#define ixMC_REGISTERS_TABLE_75                                                 0x332c0
+#define ixMC_REGISTERS_TABLE_76                                                 0x332c4
+#define ixMC_REGISTERS_TABLE_77                                                 0x332c8
+#define ixMC_REGISTERS_TABLE_78                                                 0x332cc
+#define ixMC_REGISTERS_TABLE_79                                                 0x332d0
+#define ixMC_REGISTERS_TABLE_80                                                 0x332d4
+#define ixMC_REGISTERS_TABLE_81                                                 0x332d8
+#define ixDPM_TABLE_1                                                           0x332dc
+#define ixDPM_TABLE_2                                                           0x332e0
+#define ixDPM_TABLE_3                                                           0x332e4
+#define ixDPM_TABLE_4                                                           0x332e8
+#define ixDPM_TABLE_5                                                           0x332ec
+#define ixDPM_TABLE_6                                                           0x332f0
+#define ixDPM_TABLE_7                                                           0x332f4
+#define ixDPM_TABLE_8                                                           0x332f8
+#define ixDPM_TABLE_9                                                           0x332fc
+#define ixDPM_TABLE_10                                                          0x33300
+#define ixDPM_TABLE_11                                                          0x33304
+#define ixDPM_TABLE_12                                                          0x33308
+#define ixDPM_TABLE_13                                                          0x3330c
+#define ixDPM_TABLE_14                                                          0x33310
+#define ixDPM_TABLE_15                                                          0x33314
+#define ixDPM_TABLE_16                                                          0x33318
+#define ixDPM_TABLE_17                                                          0x3331c
+#define ixDPM_TABLE_18                                                          0x33320
+#define ixDPM_TABLE_19                                                          0x33324
+#define ixDPM_TABLE_20                                                          0x33328
+#define ixDPM_TABLE_21                                                          0x3332c
+#define ixDPM_TABLE_22                                                          0x33330
+#define ixDPM_TABLE_23                                                          0x33334
+#define ixDPM_TABLE_24                                                          0x33338
+#define ixDPM_TABLE_25                                                          0x3333c
+#define ixDPM_TABLE_26                                                          0x33340
+#define ixDPM_TABLE_27                                                          0x33344
+#define ixDPM_TABLE_28                                                          0x33348
+#define ixDPM_TABLE_29                                                          0x3334c
+#define ixDPM_TABLE_30                                                          0x33350
+#define ixDPM_TABLE_31                                                          0x33354
+#define ixDPM_TABLE_32                                                          0x33358
+#define ixDPM_TABLE_33                                                          0x3335c
+#define ixDPM_TABLE_34                                                          0x33360
+#define ixDPM_TABLE_35                                                          0x33364
+#define ixDPM_TABLE_36                                                          0x33368
+#define ixDPM_TABLE_37                                                          0x3336c
+#define ixDPM_TABLE_38                                                          0x33370
+#define ixDPM_TABLE_39                                                          0x33374
+#define ixDPM_TABLE_40                                                          0x33378
+#define ixDPM_TABLE_41                                                          0x3337c
+#define ixDPM_TABLE_42                                                          0x33380
+#define ixDPM_TABLE_43                                                          0x33384
+#define ixDPM_TABLE_44                                                          0x33388
+#define ixDPM_TABLE_45                                                          0x3338c
+#define ixDPM_TABLE_46                                                          0x33390
+#define ixDPM_TABLE_47                                                          0x33394
+#define ixDPM_TABLE_48                                                          0x33398
+#define ixDPM_TABLE_49                                                          0x3339c
+#define ixDPM_TABLE_50                                                          0x333a0
+#define ixDPM_TABLE_51                                                          0x333a4
+#define ixDPM_TABLE_52                                                          0x333a8
+#define ixDPM_TABLE_53                                                          0x333ac
+#define ixDPM_TABLE_54                                                          0x333b0
+#define ixDPM_TABLE_55                                                          0x333b4
+#define ixDPM_TABLE_56                                                          0x333b8
+#define ixDPM_TABLE_57                                                          0x333bc
+#define ixDPM_TABLE_58                                                          0x333c0
+#define ixDPM_TABLE_59                                                          0x333c4
+#define ixDPM_TABLE_60                                                          0x333c8
+#define ixDPM_TABLE_61                                                          0x333cc
+#define ixDPM_TABLE_62                                                          0x333d0
+#define ixDPM_TABLE_63                                                          0x333d4
+#define ixDPM_TABLE_64                                                          0x333d8
+#define ixDPM_TABLE_65                                                          0x333dc
+#define ixDPM_TABLE_66                                                          0x333e0
+#define ixDPM_TABLE_67                                                          0x333e4
+#define ixDPM_TABLE_68                                                          0x333e8
+#define ixDPM_TABLE_69                                                          0x333ec
+#define ixDPM_TABLE_70                                                          0x333f0
+#define ixDPM_TABLE_71                                                          0x333f4
+#define ixDPM_TABLE_72                                                          0x333f8
+#define ixDPM_TABLE_73                                                          0x333fc
+#define ixDPM_TABLE_74                                                          0x33400
+#define ixDPM_TABLE_75                                                          0x33404
+#define ixDPM_TABLE_76                                                          0x33408
+#define ixDPM_TABLE_77                                                          0x3340c
+#define ixDPM_TABLE_78                                                          0x33410
+#define ixDPM_TABLE_79                                                          0x33414
+#define ixDPM_TABLE_80                                                          0x33418
+#define ixDPM_TABLE_81                                                          0x3341c
+#define ixDPM_TABLE_82                                                          0x33420
+#define ixDPM_TABLE_83                                                          0x33424
+#define ixDPM_TABLE_84                                                          0x33428
+#define ixDPM_TABLE_85                                                          0x3342c
+#define ixDPM_TABLE_86                                                          0x33430
+#define ixDPM_TABLE_87                                                          0x33434
+#define ixDPM_TABLE_88                                                          0x33438
+#define ixDPM_TABLE_89                                                          0x3343c
+#define ixDPM_TABLE_90                                                          0x33440
+#define ixDPM_TABLE_91                                                          0x33444
+#define ixDPM_TABLE_92                                                          0x33448
+#define ixDPM_TABLE_93                                                          0x3344c
+#define ixDPM_TABLE_94                                                          0x33450
+#define ixDPM_TABLE_95                                                          0x33454
+#define ixDPM_TABLE_96                                                          0x33458
+#define ixDPM_TABLE_97                                                          0x3345c
+#define ixDPM_TABLE_98                                                          0x33460
+#define ixDPM_TABLE_99                                                          0x33464
+#define ixDPM_TABLE_100                                                         0x33468
+#define ixDPM_TABLE_101                                                         0x3346c
+#define ixDPM_TABLE_102                                                         0x33470
+#define ixDPM_TABLE_103                                                         0x33474
+#define ixDPM_TABLE_104                                                         0x33478
+#define ixDPM_TABLE_105                                                         0x3347c
+#define ixDPM_TABLE_106                                                         0x33480
+#define ixDPM_TABLE_107                                                         0x33484
+#define ixDPM_TABLE_108                                                         0x33488
+#define ixDPM_TABLE_109                                                         0x3348c
+#define ixDPM_TABLE_110                                                         0x33490
+#define ixDPM_TABLE_111                                                         0x33494
+#define ixDPM_TABLE_112                                                         0x33498
+#define ixDPM_TABLE_113                                                         0x3349c
+#define ixDPM_TABLE_114                                                         0x334a0
+#define ixDPM_TABLE_115                                                         0x334a4
+#define ixDPM_TABLE_116                                                         0x334a8
+#define ixDPM_TABLE_117                                                         0x334ac
+#define ixDPM_TABLE_118                                                         0x334b0
+#define ixDPM_TABLE_119                                                         0x334b4
+#define ixDPM_TABLE_120                                                         0x334b8
+#define ixDPM_TABLE_121                                                         0x334bc
+#define ixDPM_TABLE_122                                                         0x334c0
+#define ixDPM_TABLE_123                                                         0x334c4
+#define ixDPM_TABLE_124                                                         0x334c8
+#define ixDPM_TABLE_125                                                         0x334cc
+#define ixDPM_TABLE_126                                                         0x334d0
+#define ixDPM_TABLE_127                                                         0x334d4
+#define ixDPM_TABLE_128                                                         0x334d8
+#define ixDPM_TABLE_129                                                         0x334dc
+#define ixDPM_TABLE_130                                                         0x334e0
+#define ixDPM_TABLE_131                                                         0x334e4
+#define ixDPM_TABLE_132                                                         0x334e8
+#define ixDPM_TABLE_133                                                         0x334ec
+#define ixDPM_TABLE_134                                                         0x334f0
+#define ixDPM_TABLE_135                                                         0x334f4
+#define ixDPM_TABLE_136                                                         0x334f8
+#define ixDPM_TABLE_137                                                         0x334fc
+#define ixDPM_TABLE_138                                                         0x33500
+#define ixDPM_TABLE_139                                                         0x33504
+#define ixDPM_TABLE_140                                                         0x33508
+#define ixDPM_TABLE_141                                                         0x3350c
+#define ixDPM_TABLE_142                                                         0x33510
+#define ixDPM_TABLE_143                                                         0x33514
+#define ixDPM_TABLE_144                                                         0x33518
+#define ixDPM_TABLE_145                                                         0x3351c
+#define ixDPM_TABLE_146                                                         0x33520
+#define ixDPM_TABLE_147                                                         0x33524
+#define ixDPM_TABLE_148                                                         0x33528
+#define ixDPM_TABLE_149                                                         0x3352c
+#define ixDPM_TABLE_150                                                         0x33530
+#define ixDPM_TABLE_151                                                         0x33534
+#define ixDPM_TABLE_152                                                         0x33538
+#define ixDPM_TABLE_153                                                         0x3353c
+#define ixDPM_TABLE_154                                                         0x33540
+#define ixDPM_TABLE_155                                                         0x33544
+#define ixDPM_TABLE_156                                                         0x33548
+#define ixDPM_TABLE_157                                                         0x3354c
+#define ixDPM_TABLE_158                                                         0x33550
+#define ixDPM_TABLE_159                                                         0x33554
+#define ixDPM_TABLE_160                                                         0x33558
+#define ixDPM_TABLE_161                                                         0x3355c
+#define ixDPM_TABLE_162                                                         0x33560
+#define ixDPM_TABLE_163                                                         0x33564
+#define ixDPM_TABLE_164                                                         0x33568
+#define ixDPM_TABLE_165                                                         0x3356c
+#define ixDPM_TABLE_166                                                         0x33570
+#define ixDPM_TABLE_167                                                         0x33574
+#define ixDPM_TABLE_168                                                         0x33578
+#define ixDPM_TABLE_169                                                         0x3357c
+#define ixDPM_TABLE_170                                                         0x33580
+#define ixDPM_TABLE_171                                                         0x33584
+#define ixDPM_TABLE_172                                                         0x33588
+#define ixDPM_TABLE_173                                                         0x3358c
+#define ixDPM_TABLE_174                                                         0x33590
+#define ixDPM_TABLE_175                                                         0x33594
+#define ixDPM_TABLE_176                                                         0x33598
+#define ixDPM_TABLE_177                                                         0x3359c
+#define ixDPM_TABLE_178                                                         0x335a0
+#define ixDPM_TABLE_179                                                         0x335a4
+#define ixDPM_TABLE_180                                                         0x335a8
+#define ixDPM_TABLE_181                                                         0x335ac
+#define ixDPM_TABLE_182                                                         0x335b0
+#define ixDPM_TABLE_183                                                         0x335b4
+#define ixDPM_TABLE_184                                                         0x335b8
+#define ixDPM_TABLE_185                                                         0x335bc
+#define ixDPM_TABLE_186                                                         0x335c0
+#define ixDPM_TABLE_187                                                         0x335c4
+#define ixDPM_TABLE_188                                                         0x335c8
+#define ixDPM_TABLE_189                                                         0x335cc
+#define ixDPM_TABLE_190                                                         0x335d0
+#define ixDPM_TABLE_191                                                         0x335d4
+#define ixDPM_TABLE_192                                                         0x335d8
+#define ixDPM_TABLE_193                                                         0x335dc
+#define ixDPM_TABLE_194                                                         0x335e0
+#define ixDPM_TABLE_195                                                         0x335e4
+#define ixDPM_TABLE_196                                                         0x335e8
+#define ixDPM_TABLE_197                                                         0x335ec
+#define ixDPM_TABLE_198                                                         0x335f0
+#define ixDPM_TABLE_199                                                         0x335f4
+#define ixDPM_TABLE_200                                                         0x335f8
+#define ixDPM_TABLE_201                                                         0x335fc
+#define ixDPM_TABLE_202                                                         0x33600
+#define ixDPM_TABLE_203                                                         0x33604
+#define ixDPM_TABLE_204                                                         0x33608
+#define ixDPM_TABLE_205                                                         0x3360c
+#define ixDPM_TABLE_206                                                         0x33610
+#define ixDPM_TABLE_207                                                         0x33614
+#define ixDPM_TABLE_208                                                         0x33618
+#define ixDPM_TABLE_209                                                         0x3361c
+#define ixDPM_TABLE_210                                                         0x33620
+#define ixDPM_TABLE_211                                                         0x33624
+#define ixDPM_TABLE_212                                                         0x33628
+#define ixDPM_TABLE_213                                                         0x3362c
+#define ixDPM_TABLE_214                                                         0x33630
+#define ixDPM_TABLE_215                                                         0x33634
+#define ixDPM_TABLE_216                                                         0x33638
+#define ixDPM_TABLE_217                                                         0x3363c
+#define ixDPM_TABLE_218                                                         0x33640
+#define ixDPM_TABLE_219                                                         0x33644
+#define ixDPM_TABLE_220                                                         0x33648
+#define ixDPM_TABLE_221                                                         0x3364c
+#define ixDPM_TABLE_222                                                         0x33650
+#define ixDPM_TABLE_223                                                         0x33654
+#define ixDPM_TABLE_224                                                         0x33658
+#define ixDPM_TABLE_225                                                         0x3365c
+#define ixDPM_TABLE_226                                                         0x33660
+#define ixDPM_TABLE_227                                                         0x33664
+#define ixDPM_TABLE_228                                                         0x33668
+#define ixDPM_TABLE_229                                                         0x3366c
+#define ixDPM_TABLE_230                                                         0x33670
+#define ixDPM_TABLE_231                                                         0x33674
+#define ixDPM_TABLE_232                                                         0x33678
+#define ixDPM_TABLE_233                                                         0x3367c
+#define ixDPM_TABLE_234                                                         0x33680
+#define ixDPM_TABLE_235                                                         0x33684
+#define ixDPM_TABLE_236                                                         0x33688
+#define ixDPM_TABLE_237                                                         0x3368c
+#define ixDPM_TABLE_238                                                         0x33690
+#define ixDPM_TABLE_239                                                         0x33694
+#define ixDPM_TABLE_240                                                         0x33698
+#define ixDPM_TABLE_241                                                         0x3369c
+#define ixDPM_TABLE_242                                                         0x336a0
+#define ixDPM_TABLE_243                                                         0x336a4
+#define ixDPM_TABLE_244                                                         0x336a8
+#define ixDPM_TABLE_245                                                         0x336ac
+#define ixDPM_TABLE_246                                                         0x336b0
+#define ixDPM_TABLE_247                                                         0x336b4
+#define ixDPM_TABLE_248                                                         0x336b8
+#define ixDPM_TABLE_249                                                         0x336bc
+#define ixDPM_TABLE_250                                                         0x336c0
+#define ixDPM_TABLE_251                                                         0x336c4
+#define ixDPM_TABLE_252                                                         0x336c8
+#define ixDPM_TABLE_253                                                         0x336cc
+#define ixDPM_TABLE_254                                                         0x336d0
+#define ixDPM_TABLE_255                                                         0x336d4
+#define ixDPM_TABLE_256                                                         0x336d8
+#define ixDPM_TABLE_257                                                         0x336dc
+#define ixDPM_TABLE_258                                                         0x336e0
+#define ixDPM_TABLE_259                                                         0x336e4
+#define ixDPM_TABLE_260                                                         0x336e8
+#define ixDPM_TABLE_261                                                         0x336ec
+#define ixDPM_TABLE_262                                                         0x336f0
+#define ixDPM_TABLE_263                                                         0x336f4
+#define ixDPM_TABLE_264                                                         0x336f8
+#define ixDPM_TABLE_265                                                         0x336fc
+#define ixDPM_TABLE_266                                                         0x33700
+#define ixDPM_TABLE_267                                                         0x33704
+#define ixDPM_TABLE_268                                                         0x33708
+#define ixDPM_TABLE_269                                                         0x3370c
+#define ixDPM_TABLE_270                                                         0x33710
+#define ixDPM_TABLE_271                                                         0x33714
+#define ixDPM_TABLE_272                                                         0x33718
+#define ixDPM_TABLE_273                                                         0x3371c
+#define ixDPM_TABLE_274                                                         0x33720
+#define ixDPM_TABLE_275                                                         0x33724
+#define ixDPM_TABLE_276                                                         0x33728
+#define ixDPM_TABLE_277                                                         0x3372c
+#define ixDPM_TABLE_278                                                         0x33730
+#define ixDPM_TABLE_279                                                         0x33734
+#define ixDPM_TABLE_280                                                         0x33738
+#define ixDPM_TABLE_281                                                         0x3373c
+#define ixDPM_TABLE_282                                                         0x33740
+#define ixDPM_TABLE_283                                                         0x33744
+#define ixDPM_TABLE_284                                                         0x33748
+#define ixDPM_TABLE_285                                                         0x3374c
+#define ixDPM_TABLE_286                                                         0x33750
+#define ixDPM_TABLE_287                                                         0x33754
+#define ixDPM_TABLE_288                                                         0x33758
+#define ixDPM_TABLE_289                                                         0x3375c
+#define ixDPM_TABLE_290                                                         0x33760
+#define ixDPM_TABLE_291                                                         0x33764
+#define ixDPM_TABLE_292                                                         0x33768
+#define ixDPM_TABLE_293                                                         0x3376c
+#define ixDPM_TABLE_294                                                         0x33770
+#define ixDPM_TABLE_295                                                         0x33774
+#define ixDPM_TABLE_296                                                         0x33778
+#define ixDPM_TABLE_297                                                         0x3377c
+#define ixDPM_TABLE_298                                                         0x33780
+#define ixDPM_TABLE_299                                                         0x33784
+#define ixDPM_TABLE_300                                                         0x33788
+#define ixDPM_TABLE_301                                                         0x3378c
+#define ixDPM_TABLE_302                                                         0x33790
+#define ixDPM_TABLE_303                                                         0x33794
+#define ixDPM_TABLE_304                                                         0x33798
+#define ixDPM_TABLE_305                                                         0x3379c
+#define ixDPM_TABLE_306                                                         0x337a0
+#define ixDPM_TABLE_307                                                         0x337a4
+#define ixDPM_TABLE_308                                                         0x337a8
+#define ixDPM_TABLE_309                                                         0x337ac
+#define ixDPM_TABLE_310                                                         0x337b0
+#define ixDPM_TABLE_311                                                         0x337b4
+#define ixDPM_TABLE_312                                                         0x337b8
+#define ixDPM_TABLE_313                                                         0x337bc
+#define ixDPM_TABLE_314                                                         0x337c0
+#define ixDPM_TABLE_315                                                         0x337c4
+#define ixDPM_TABLE_316                                                         0x337c8
+#define ixDPM_TABLE_317                                                         0x337cc
+#define ixDPM_TABLE_318                                                         0x337d0
+#define ixDPM_TABLE_319                                                         0x337d4
+#define ixDPM_TABLE_320                                                         0x337d8
+#define ixDPM_TABLE_321                                                         0x337dc
+#define ixDPM_TABLE_322                                                         0x337e0
+#define ixDPM_TABLE_323                                                         0x337e4
+#define ixDPM_TABLE_324                                                         0x337e8
+#define ixDPM_TABLE_325                                                         0x337ec
+#define ixDPM_TABLE_326                                                         0x337f0
+#define ixDPM_TABLE_327                                                         0x337f4
+#define ixDPM_TABLE_328                                                         0x337f8
+#define ixDPM_TABLE_329                                                         0x337fc
+#define ixDPM_TABLE_330                                                         0x33800
+#define ixDPM_TABLE_331                                                         0x33804
+#define ixDPM_TABLE_332                                                         0x33808
+#define ixDPM_TABLE_333                                                         0x3380c
+#define ixDPM_TABLE_334                                                         0x33810
+#define ixDPM_TABLE_335                                                         0x33814
+#define ixDPM_TABLE_336                                                         0x33818
+#define ixDPM_TABLE_337                                                         0x3381c
+#define ixDPM_TABLE_338                                                         0x33820
+#define ixDPM_TABLE_339                                                         0x33824
+#define ixDPM_TABLE_340                                                         0x33828
+#define ixDPM_TABLE_341                                                         0x3382c
+#define ixDPM_TABLE_342                                                         0x33830
+#define ixDPM_TABLE_343                                                         0x33834
+#define ixDPM_TABLE_344                                                         0x33838
+#define ixDPM_TABLE_345                                                         0x3383c
+#define ixDPM_TABLE_346                                                         0x33840
+#define ixDPM_TABLE_347                                                         0x33844
+#define ixDPM_TABLE_348                                                         0x33848
+#define ixDPM_TABLE_349                                                         0x3384c
+#define ixDPM_TABLE_350                                                         0x33850
+#define ixDPM_TABLE_351                                                         0x33854
+#define ixDPM_TABLE_352                                                         0x33858
+#define ixDPM_TABLE_353                                                         0x3385c
+#define ixDPM_TABLE_354                                                         0x33860
+#define ixDPM_TABLE_355                                                         0x33864
+#define ixDPM_TABLE_356                                                         0x33868
+#define ixDPM_TABLE_357                                                         0x3386c
+#define ixDPM_TABLE_358                                                         0x33870
+#define ixDPM_TABLE_359                                                         0x33874
+#define ixDPM_TABLE_360                                                         0x33878
+#define ixDPM_TABLE_361                                                         0x3387c
+#define ixDPM_TABLE_362                                                         0x33880
+#define ixDPM_TABLE_363                                                         0x33884
+#define ixDPM_TABLE_364                                                         0x33888
+#define ixDPM_TABLE_365                                                         0x3388c
+#define ixDPM_TABLE_366                                                         0x33890
+#define ixDPM_TABLE_367                                                         0x33894
+#define ixDPM_TABLE_368                                                         0x33898
+#define ixDPM_TABLE_369                                                         0x3389c
+#define ixDPM_TABLE_370                                                         0x338a0
+#define ixSOFT_REGISTERS_TABLE_1                                                0x338c8
+#define ixSOFT_REGISTERS_TABLE_2                                                0x338cc
+#define ixSOFT_REGISTERS_TABLE_3                                                0x338d0
+#define ixSOFT_REGISTERS_TABLE_4                                                0x338d4
+#define ixSOFT_REGISTERS_TABLE_5                                                0x338d8
+#define ixSOFT_REGISTERS_TABLE_6                                                0x338dc
+#define ixSOFT_REGISTERS_TABLE_7                                                0x338e0
+#define ixSOFT_REGISTERS_TABLE_8                                                0x338e4
+#define ixSOFT_REGISTERS_TABLE_9                                                0x338e8
+#define ixSOFT_REGISTERS_TABLE_10                                               0x338ec
+#define ixSOFT_REGISTERS_TABLE_11                                               0x338f0
+#define ixSOFT_REGISTERS_TABLE_12                                               0x338f4
+#define ixSOFT_REGISTERS_TABLE_13                                               0x338f8
+#define ixSOFT_REGISTERS_TABLE_14                                               0x338fc
+#define ixSOFT_REGISTERS_TABLE_15                                               0x33900
+#define ixSOFT_REGISTERS_TABLE_16                                               0x33904
+#define ixSOFT_REGISTERS_TABLE_17                                               0x33908
+#define ixSOFT_REGISTERS_TABLE_18                                               0x3390c
+#define ixSOFT_REGISTERS_TABLE_19                                               0x33910
+#define ixSOFT_REGISTERS_TABLE_20                                               0x33914
+#define ixSOFT_REGISTERS_TABLE_21                                               0x33918
+#define ixSOFT_REGISTERS_TABLE_22                                               0x3391c
+#define ixSOFT_REGISTERS_TABLE_23                                               0x33920
+#define ixSOFT_REGISTERS_TABLE_24                                               0x33924
+#define ixSOFT_REGISTERS_TABLE_25                                               0x33928
+#define ixSOFT_REGISTERS_TABLE_26                                               0x3392c
+#define ixSOFT_REGISTERS_TABLE_27                                               0x33930
+#define ixSOFT_REGISTERS_TABLE_28                                               0x33934
+#define ixSOFT_REGISTERS_TABLE_29                                               0x33938
+#define ixFIRMWARE_FLAGS                                                        0x33000
+#define ixTDC_STATUS                                                            0x33004
+#define ixTDC_MV_AVERAGE                                                        0x33008
+#define ixTDC_VRM_LIMIT                                                         0x3300c
+#define ixFEATURE_STATUS                                                        0x33010
+#define ixENTITY_TEMPERATURES_1                                                 0x33014
+#define ixPM_FUSES_1                                                            0x3394c
+#define ixPM_FUSES_2                                                            0x33950
+#define ixPM_FUSES_3                                                            0x33954
+#define ixPM_FUSES_4                                                            0x33958
+#define ixPM_FUSES_5                                                            0x3395c
+#define ixPM_FUSES_6                                                            0x33960
+#define ixPM_FUSES_7                                                            0x33964
+#define ixPM_FUSES_8                                                            0x33968
+#define ixPM_FUSES_9                                                            0x3396c
+#define ixPM_FUSES_10                                                           0x33970
+#define ixPM_FUSES_11                                                           0x33974
+#define ixPM_FUSES_12                                                           0x33978
+#define ixPM_FUSES_13                                                           0x3397c
+#define ixPM_FUSES_14                                                           0x33980
+#define ixPM_FUSES_15                                                           0x33984
+#define ixPM_FUSES_16                                                           0x33988
+#define ixPM_FUSES_17                                                           0x3398c
+#define ixPM_FUSES_18                                                           0x33990
+#define ixPM_FUSES_19                                                           0x33994
+#define ixPM_FUSES_20                                                           0x33998
+#define ixPM_FUSES_21                                                           0x3399c
+#define ixSMU_PM_STATUS_0                                                       0x33e00
+#define ixSMU_PM_STATUS_1                                                       0x33e04
+#define ixSMU_PM_STATUS_2                                                       0x33e08
+#define ixSMU_PM_STATUS_3                                                       0x33e0c
+#define ixSMU_PM_STATUS_4                                                       0x33e10
+#define ixSMU_PM_STATUS_5                                                       0x33e14
+#define ixSMU_PM_STATUS_6                                                       0x33e18
+#define ixSMU_PM_STATUS_7                                                       0x33e1c
+#define ixSMU_PM_STATUS_8                                                       0x33e20
+#define ixSMU_PM_STATUS_9                                                       0x33e24
+#define ixSMU_PM_STATUS_10                                                      0x33e28
+#define ixSMU_PM_STATUS_11                                                      0x33e2c
+#define ixSMU_PM_STATUS_12                                                      0x33e30
+#define ixSMU_PM_STATUS_13                                                      0x33e34
+#define ixSMU_PM_STATUS_14                                                      0x33e38
+#define ixSMU_PM_STATUS_15                                                      0x33e3c
+#define ixSMU_PM_STATUS_16                                                      0x33e40
+#define ixSMU_PM_STATUS_17                                                      0x33e44
+#define ixSMU_PM_STATUS_18                                                      0x33e48
+#define ixSMU_PM_STATUS_19                                                      0x33e4c
+#define ixSMU_PM_STATUS_20                                                      0x33e50
+#define ixSMU_PM_STATUS_21                                                      0x33e54
+#define ixSMU_PM_STATUS_22                                                      0x33e58
+#define ixSMU_PM_STATUS_23                                                      0x33e5c
+#define ixSMU_PM_STATUS_24                                                      0x33e60
+#define ixSMU_PM_STATUS_25                                                      0x33e64
+#define ixSMU_PM_STATUS_26                                                      0x33e68
+#define ixSMU_PM_STATUS_27                                                      0x33e6c
+#define ixSMU_PM_STATUS_28                                                      0x33e70
+#define ixSMU_PM_STATUS_29                                                      0x33e74
+#define ixSMU_PM_STATUS_30                                                      0x33e78
+#define ixSMU_PM_STATUS_31                                                      0x33e7c
+#define ixSMU_PM_STATUS_32                                                      0x33e80
+#define ixSMU_PM_STATUS_33                                                      0x33e84
+#define ixSMU_PM_STATUS_34                                                      0x33e88
+#define ixSMU_PM_STATUS_35                                                      0x33e8c
+#define ixSMU_PM_STATUS_36                                                      0x33e90
+#define ixSMU_PM_STATUS_37                                                      0x33e94
+#define ixSMU_PM_STATUS_38                                                      0x33e98
+#define ixSMU_PM_STATUS_39                                                      0x33e9c
+#define ixSMU_PM_STATUS_40                                                      0x33ea0
+#define ixSMU_PM_STATUS_41                                                      0x33ea4
+#define ixSMU_PM_STATUS_42                                                      0x33ea8
+#define ixSMU_PM_STATUS_43                                                      0x33eac
+#define ixSMU_PM_STATUS_44                                                      0x33eb0
+#define ixSMU_PM_STATUS_45                                                      0x33eb4
+#define ixSMU_PM_STATUS_46                                                      0x33eb8
+#define ixSMU_PM_STATUS_47                                                      0x33ebc
+#define ixSMU_PM_STATUS_48                                                      0x33ec0
+#define ixSMU_PM_STATUS_49                                                      0x33ec4
+#define ixSMU_PM_STATUS_50                                                      0x33ec8
+#define ixSMU_PM_STATUS_51                                                      0x33ecc
+#define ixSMU_PM_STATUS_52                                                      0x33ed0
+#define ixSMU_PM_STATUS_53                                                      0x33ed4
+#define ixSMU_PM_STATUS_54                                                      0x33ed8
+#define ixSMU_PM_STATUS_55                                                      0x33edc
+#define ixSMU_PM_STATUS_56                                                      0x33ee0
+#define ixSMU_PM_STATUS_57                                                      0x33ee4
+#define ixSMU_PM_STATUS_58                                                      0x33ee8
+#define ixSMU_PM_STATUS_59                                                      0x33eec
+#define ixSMU_PM_STATUS_60                                                      0x33ef0
+#define ixSMU_PM_STATUS_61                                                      0x33ef4
+#define ixSMU_PM_STATUS_62                                                      0x33ef8
+#define ixSMU_PM_STATUS_63                                                      0x33efc
+#define ixSMU_PM_STATUS_64                                                      0x33f00
+#define ixSMU_PM_STATUS_65                                                      0x33f04
+#define ixSMU_PM_STATUS_66                                                      0x33f08
+#define ixSMU_PM_STATUS_67                                                      0x33f0c
+#define ixSMU_PM_STATUS_68                                                      0x33f10
+#define ixSMU_PM_STATUS_69                                                      0x33f14
+#define ixSMU_PM_STATUS_70                                                      0x33f18
+#define ixSMU_PM_STATUS_71                                                      0x33f1c
+#define ixSMU_PM_STATUS_72                                                      0x33f20
+#define ixSMU_PM_STATUS_73                                                      0x33f24
+#define ixSMU_PM_STATUS_74                                                      0x33f28
+#define ixSMU_PM_STATUS_75                                                      0x33f2c
+#define ixSMU_PM_STATUS_76                                                      0x33f30
+#define ixSMU_PM_STATUS_77                                                      0x33f34
+#define ixSMU_PM_STATUS_78                                                      0x33f38
+#define ixSMU_PM_STATUS_79                                                      0x33f3c
+#define ixSMU_PM_STATUS_80                                                      0x33f40
+#define ixSMU_PM_STATUS_81                                                      0x33f44
+#define ixSMU_PM_STATUS_82                                                      0x33f48
+#define ixSMU_PM_STATUS_83                                                      0x33f4c
+#define ixSMU_PM_STATUS_84                                                      0x33f50
+#define ixSMU_PM_STATUS_85                                                      0x33f54
+#define ixSMU_PM_STATUS_86                                                      0x33f58
+#define ixSMU_PM_STATUS_87                                                      0x33f5c
+#define ixSMU_PM_STATUS_88                                                      0x33f60
+#define ixSMU_PM_STATUS_89                                                      0x33f64
+#define ixSMU_PM_STATUS_90                                                      0x33f68
+#define ixSMU_PM_STATUS_91                                                      0x33f6c
+#define ixSMU_PM_STATUS_92                                                      0x33f70
+#define ixSMU_PM_STATUS_93                                                      0x33f74
+#define ixSMU_PM_STATUS_94                                                      0x33f78
+#define ixSMU_PM_STATUS_95                                                      0x33f7c
+#define ixSMU_PM_STATUS_96                                                      0x33f80
+#define ixSMU_PM_STATUS_97                                                      0x33f84
+#define ixSMU_PM_STATUS_98                                                      0x33f88
+#define ixSMU_PM_STATUS_99                                                      0x33f8c
+#define ixSMU_PM_STATUS_100                                                     0x33f90
+#define ixSMU_PM_STATUS_101                                                     0x33f94
+#define ixSMU_PM_STATUS_102                                                     0x33f98
+#define ixSMU_PM_STATUS_103                                                     0x33f9c
+#define ixSMU_PM_STATUS_104                                                     0x33fa0
+#define ixSMU_PM_STATUS_105                                                     0x33fa4
+#define ixSMU_PM_STATUS_106                                                     0x33fa8
+#define ixSMU_PM_STATUS_107                                                     0x33fac
+#define ixSMU_PM_STATUS_108                                                     0x33fb0
+#define ixSMU_PM_STATUS_109                                                     0x33fb4
+#define ixSMU_PM_STATUS_110                                                     0x33fb8
+#define ixSMU_PM_STATUS_111                                                     0x33fbc
+#define ixSMU_PM_STATUS_112                                                     0x33fc0
+#define ixSMU_PM_STATUS_113                                                     0x33fc4
+#define ixSMU_PM_STATUS_114                                                     0x33fc8
+#define ixSMU_PM_STATUS_115                                                     0x33fcc
+#define ixSMU_PM_STATUS_116                                                     0x33fd0
+#define ixSMU_PM_STATUS_117                                                     0x33fd4
+#define ixSMU_PM_STATUS_118                                                     0x33fd8
+#define ixSMU_PM_STATUS_119                                                     0x33fdc
+#define ixSMU_PM_STATUS_120                                                     0x33fe0
+#define ixSMU_PM_STATUS_121                                                     0x33fe4
+#define ixSMU_PM_STATUS_122                                                     0x33fe8
+#define ixSMU_PM_STATUS_123                                                     0x33fec
+#define ixSMU_PM_STATUS_124                                                     0x33ff0
+#define ixSMU_PM_STATUS_125                                                     0x33ff4
+#define ixSMU_PM_STATUS_126                                                     0x33ff8
+#define ixSMU_PM_STATUS_127                                                     0x33ffc
+#define ixCG_THERMAL_INT_ENA                                                    0xc2100024
+#define ixCG_THERMAL_INT_CTRL                                                   0xc2100028
+#define ixCG_THERMAL_INT_STATUS                                                 0xc210002c
+#define ixCG_THERMAL_CTRL                                                       0xc0300004
+#define ixCG_THERMAL_STATUS                                                     0xc0300008
+#define ixCG_THERMAL_INT                                                        0xc030000c
+#define ixCG_MULT_THERMAL_CTRL                                                  0xc0300010
+#define ixCG_MULT_THERMAL_STATUS                                                0xc0300014
+#define ixCG_FDO_CTRL0                                                          0xc0300064
+#define ixCG_FDO_CTRL1                                                          0xc0300068
+#define ixCG_FDO_CTRL2                                                          0xc030006c
+#define ixCG_TACH_CTRL                                                          0xc0300070
+#define ixCG_TACH_STATUS                                                        0xc0300074
+#define ixCC_THM_STRAPS0                                                        0xc0300080
+#define ixTHM_TMON0_RDIL0_DATA                                                  0xc0300100
+#define ixTHM_TMON0_RDIL1_DATA                                                  0xc0300104
+#define ixTHM_TMON0_RDIL2_DATA                                                  0xc0300108
+#define ixTHM_TMON0_RDIL3_DATA                                                  0xc030010c
+#define ixTHM_TMON0_RDIL4_DATA                                                  0xc0300110
+#define ixTHM_TMON0_RDIL5_DATA                                                  0xc0300114
+#define ixTHM_TMON0_RDIL6_DATA                                                  0xc0300118
+#define ixTHM_TMON0_RDIL7_DATA                                                  0xc030011c
+#define ixTHM_TMON0_RDIL8_DATA                                                  0xc0300120
+#define ixTHM_TMON0_RDIL9_DATA                                                  0xc0300124
+#define ixTHM_TMON0_RDIL10_DATA                                                 0xc0300128
+#define ixTHM_TMON0_RDIL11_DATA                                                 0xc030012c
+#define ixTHM_TMON0_RDIL12_DATA                                                 0xc0300130
+#define ixTHM_TMON0_RDIL13_DATA                                                 0xc0300134
+#define ixTHM_TMON0_RDIL14_DATA                                                 0xc0300138
+#define ixTHM_TMON0_RDIL15_DATA                                                 0xc030013c
+#define ixTHM_TMON0_RDIR0_DATA                                                  0xc0300140
+#define ixTHM_TMON0_RDIR1_DATA                                                  0xc0300144
+#define ixTHM_TMON0_RDIR2_DATA                                                  0xc0300148
+#define ixTHM_TMON0_RDIR3_DATA                                                  0xc030014c
+#define ixTHM_TMON0_RDIR4_DATA                                                  0xc0300150
+#define ixTHM_TMON0_RDIR5_DATA                                                  0xc0300154
+#define ixTHM_TMON0_RDIR6_DATA                                                  0xc0300158
+#define ixTHM_TMON0_RDIR7_DATA                                                  0xc030015c
+#define ixTHM_TMON0_RDIR8_DATA                                                  0xc0300160
+#define ixTHM_TMON0_RDIR9_DATA                                                  0xc0300164
+#define ixTHM_TMON0_RDIR10_DATA                                                 0xc0300168
+#define ixTHM_TMON0_RDIR11_DATA                                                 0xc030016c
+#define ixTHM_TMON0_RDIR12_DATA                                                 0xc0300170
+#define ixTHM_TMON0_RDIR13_DATA                                                 0xc0300174
+#define ixTHM_TMON0_RDIR14_DATA                                                 0xc0300178
+#define ixTHM_TMON0_RDIR15_DATA                                                 0xc030017c
+#define ixTHM_TMON0_INT_DATA                                                    0xc0300300
+#define ixTHM_TMON0_DEBUG                                                       0xc0300310
+#define ixTHM_TMON0_STATUS                                                      0xc0300320
+#define ixGENERAL_PWRMGT                                                        0xc0200000
+#define ixCNB_PWRMGT_CNTL                                                       0xc0200004
+#define ixSCLK_PWRMGT_CNTL                                                      0xc0200008
+#define ixTARGET_AND_CURRENT_PROFILE_INDEX                                      0xc0200014
+#define ixPWR_PCC_CONTROL                                                       0xc0200018
+#define ixPWR_PCC_GPIO_SELECT                                                   0xc020001c
+#define ixCG_FREQ_TRAN_VOTING_0                                                 0xc02001a8
+#define ixCG_FREQ_TRAN_VOTING_1                                                 0xc02001ac
+#define ixCG_FREQ_TRAN_VOTING_2                                                 0xc02001b0
+#define ixCG_FREQ_TRAN_VOTING_3                                                 0xc02001b4
+#define ixCG_FREQ_TRAN_VOTING_4                                                 0xc02001b8
+#define ixCG_FREQ_TRAN_VOTING_5                                                 0xc02001bc
+#define ixCG_FREQ_TRAN_VOTING_6                                                 0xc02001c0
+#define ixCG_FREQ_TRAN_VOTING_7                                                 0xc02001c4
+#define ixPLL_TEST_CNTL                                                         0xc020003c
+#define ixCG_STATIC_SCREEN_PARAMETER                                            0xc0200044
+#define ixCG_DISPLAY_GAP_CNTL                                                   0xc0200060
+#define ixCG_DISPLAY_GAP_CNTL2                                                  0xc0200230
+#define ixCG_ACPI_CNTL                                                          0xc0200064
+#define ixSCLK_DEEP_SLEEP_CNTL                                                  0xc0200080
+#define ixSCLK_DEEP_SLEEP_CNTL2                                                 0xc0200084
+#define ixSCLK_DEEP_SLEEP_CNTL3                                                 0xc020009c
+#define ixSCLK_DEEP_SLEEP_MISC_CNTL                                             0xc0200088
+#define ixLCLK_DEEP_SLEEP_CNTL                                                  0xc020008c
+#define ixLCLK_DEEP_SLEEP_CNTL2                                                 0xc0200310
+#define ixTARGET_AND_CURRENT_PROFILE_INDEX_1                                    0xc02000f0
+#define ixCG_ULV_PARAMETER                                                      0xc020015c
+#define ixSCLK_MIN_DIV                                                          0xc02003ac
+#define ixPWR_DISP_TIMER_0_CONTROL                                              0xc0200390
+#define ixPWR_DISP_TIMER_1_CONTROL                                              0xc020037c
+#define ixPWR_DISP_TIMER_2_CONTROL                                              0xc02003d0
+#define ixPWR_DISP_TIMER_3_CONTROL                                              0xc02003d4
+#define ixPWR_DISP_TIMER_4_CONTROL                                              0xc02003d8
+#define ixPWR_DISP_TIMER_5_CONTROL                                              0xc02003dc
+#define ixPWR_DISP_TIMER_6_CONTROL                                              0xc02003e0
+#define ixPWR_DISP_TIMER_7_CONTROL                                              0xc02003e4
+#define ixPWR_DISP_TIMER_8_CONTROL                                              0xc02003e8
+#define ixPWR_DISP_TIMER_9_CONTROL                                              0xc02003ec
+#define ixPWR_DISP_TIMER_10_CONTROL                                             0xc02003f0
+#define ixPWR_DISP_TIMER_11_CONTROL                                             0xc02003f4
+#define ixPWR_DISP_TIMER_12_CONTROL                                             0xc02003f8
+#define ixPWR_DISP_TIMER_13_CONTROL                                             0xc02003fc
+#define ixPWR_DISP_TIMER_14_CONTROL                                             0xc0200074
+#define ixPWR_DISP_TIMER_15_CONTROL                                             0xc0200078
+#define ixPWR_DISP_TIMER_CONTROL2                                               0xc0200378
+#define ixVDDGFX_IDLE_PARAMETER                                                 0xc020036c
+#define ixVDDGFX_IDLE_CONTROL                                                   0xc0200370
+#define ixVDDGFX_IDLE_EXIT                                                      0xc0200374
+#define ixLCAC_MC0_CNTL                                                         0xc0400130
+#define ixLCAC_MC0_OVR_SEL                                                      0xc0400134
+#define ixLCAC_MC0_OVR_VAL                                                      0xc0400138
+#define ixLCAC_MC1_CNTL                                                         0xc040013c
+#define ixLCAC_MC1_OVR_SEL                                                      0xc0400140
+#define ixLCAC_MC1_OVR_VAL                                                      0xc0400144
+#define ixLCAC_MC2_CNTL                                                         0xc0400148
+#define ixLCAC_MC2_OVR_SEL                                                      0xc040014c
+#define ixLCAC_MC2_OVR_VAL                                                      0xc0400150
+#define ixLCAC_MC3_CNTL                                                         0xc0400154
+#define ixLCAC_MC3_OVR_SEL                                                      0xc0400158
+#define ixLCAC_MC3_OVR_VAL                                                      0xc040015c
+#define ixLCAC_CPL_CNTL                                                         0xc0400160
+#define ixLCAC_CPL_OVR_SEL                                                      0xc0400164
+#define ixLCAC_CPL_OVR_VAL                                                      0xc0400168
+#define mmROM_SMC_IND_INDEX                                                     0x80
+#define mmROM0_ROM_SMC_IND_INDEX                                                0x80
+#define mmROM1_ROM_SMC_IND_INDEX                                                0x82
+#define mmROM2_ROM_SMC_IND_INDEX                                                0x84
+#define mmROM3_ROM_SMC_IND_INDEX                                                0x86
+#define mmROM_SMC_IND_DATA                                                      0x81
+#define mmROM0_ROM_SMC_IND_DATA                                                 0x81
+#define mmROM1_ROM_SMC_IND_DATA                                                 0x83
+#define mmROM2_ROM_SMC_IND_DATA                                                 0x85
+#define mmROM3_ROM_SMC_IND_DATA                                                 0x87
+#define ixROM_CNTL                                                              0xc0600000
+#define ixPAGE_MIRROR_CNTL                                                      0xc0600004
+#define ixROM_STATUS                                                            0xc0600008
+#define ixCGTT_ROM_CLK_CTRL0                                                    0xc060000c
+#define ixROM_INDEX                                                             0xc0600010
+#define ixROM_DATA                                                              0xc0600014
+#define ixROM_START                                                             0xc0600018
+#define ixROM_SW_CNTL                                                           0xc060001c
+#define ixROM_SW_STATUS                                                         0xc0600020
+#define ixROM_SW_COMMAND                                                        0xc0600024
+#define ixROM_SW_DATA_1                                                         0xc0600028
+#define ixROM_SW_DATA_2                                                         0xc060002c
+#define ixROM_SW_DATA_3                                                         0xc0600030
+#define ixROM_SW_DATA_4                                                         0xc0600034
+#define ixROM_SW_DATA_5                                                         0xc0600038
+#define ixROM_SW_DATA_6                                                         0xc060003c
+#define ixROM_SW_DATA_7                                                         0xc0600040
+#define ixROM_SW_DATA_8                                                         0xc0600044
+#define ixROM_SW_DATA_9                                                         0xc0600048
+#define ixROM_SW_DATA_10                                                        0xc060004c
+#define ixROM_SW_DATA_11                                                        0xc0600050
+#define ixROM_SW_DATA_12                                                        0xc0600054
+#define ixROM_SW_DATA_13                                                        0xc0600058
+#define ixROM_SW_DATA_14                                                        0xc060005c
+#define ixROM_SW_DATA_15                                                        0xc0600060
+#define ixROM_SW_DATA_16                                                        0xc0600064
+#define ixROM_SW_DATA_17                                                        0xc0600068
+#define ixROM_SW_DATA_18                                                        0xc060006c
+#define ixROM_SW_DATA_19                                                        0xc0600070
+#define ixROM_SW_DATA_20                                                        0xc0600074
+#define ixROM_SW_DATA_21                                                        0xc0600078
+#define ixROM_SW_DATA_22                                                        0xc060007c
+#define ixROM_SW_DATA_23                                                        0xc0600080
+#define ixROM_SW_DATA_24                                                        0xc0600084
+#define ixROM_SW_DATA_25                                                        0xc0600088
+#define ixROM_SW_DATA_26                                                        0xc060008c
+#define ixROM_SW_DATA_27                                                        0xc0600090
+#define ixROM_SW_DATA_28                                                        0xc0600094
+#define ixROM_SW_DATA_29                                                        0xc0600098
+#define ixROM_SW_DATA_30                                                        0xc060009c
+#define ixROM_SW_DATA_31                                                        0xc06000a0
+#define ixROM_SW_DATA_32                                                        0xc06000a4
+#define ixROM_SW_DATA_33                                                        0xc06000a8
+#define ixROM_SW_DATA_34                                                        0xc06000ac
+#define ixROM_SW_DATA_35                                                        0xc06000b0
+#define ixROM_SW_DATA_36                                                        0xc06000b4
+#define ixROM_SW_DATA_37                                                        0xc06000b8
+#define ixROM_SW_DATA_38                                                        0xc06000bc
+#define ixROM_SW_DATA_39                                                        0xc06000c0
+#define ixROM_SW_DATA_40                                                        0xc06000c4
+#define ixROM_SW_DATA_41                                                        0xc06000c8
+#define ixROM_SW_DATA_42                                                        0xc06000cc
+#define ixROM_SW_DATA_43                                                        0xc06000d0
+#define ixROM_SW_DATA_44                                                        0xc06000d4
+#define ixROM_SW_DATA_45                                                        0xc06000d8
+#define ixROM_SW_DATA_46                                                        0xc06000dc
+#define ixROM_SW_DATA_47                                                        0xc06000e0
+#define ixROM_SW_DATA_48                                                        0xc06000e4
+#define ixROM_SW_DATA_49                                                        0xc06000e8
+#define ixROM_SW_DATA_50                                                        0xc06000ec
+#define ixROM_SW_DATA_51                                                        0xc06000f0
+#define ixROM_SW_DATA_52                                                        0xc06000f4
+#define ixROM_SW_DATA_53                                                        0xc06000f8
+#define ixROM_SW_DATA_54                                                        0xc06000fc
+#define ixROM_SW_DATA_55                                                        0xc0600100
+#define ixROM_SW_DATA_56                                                        0xc0600104
+#define ixROM_SW_DATA_57                                                        0xc0600108
+#define ixROM_SW_DATA_58                                                        0xc060010c
+#define ixROM_SW_DATA_59                                                        0xc0600110
+#define ixROM_SW_DATA_60                                                        0xc0600114
+#define ixROM_SW_DATA_61                                                        0xc0600118
+#define ixROM_SW_DATA_62                                                        0xc060011c
+#define ixROM_SW_DATA_63                                                        0xc0600120
+#define ixROM_SW_DATA_64                                                        0xc0600124
+
+#endif /* SMU_7_1_1_D_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_enum.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_enum.h
new file mode 100644 (file)
index 0000000..c1a7aba
--- /dev/null
@@ -0,0 +1,1205 @@
+/*
+ * SMU_7_1_1 Register documentation
+ *
+ * Copyright (C) 2014  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef SMU_7_1_1_ENUM_H
+#define SMU_7_1_1_ENUM_H
+
+#define CG_SRBM_START_ADDR                        0x600
+#define CG_SRBM_END_ADDR                          0x8ff
+#define RCU_CCF_DWORDS0                           0x80
+#define RCU_CCF_BITS0                             0x1000
+#define RCU_CCF_DWORDS1                           0x0
+#define RCU_CCF_BITS1                             0x0
+#define RCU_SAM_BYTES                             0x0
+#define RCU_SAM_RTL_BYTES                         0x0
+#define RCU_SMU_BYTES                             0x0
+#define RCU_SMU_RTL_BYTES                         0x0
+#define SFP_CHAIN_ADDR                            0x0
+#define SFP_BYTES                                 0x80
+#define SFP_SADR                                  0x180
+#define SFP_EADR                                  0x1ff
+#define SAMU_KEY_CHAIN_ADR                        0x0
+#define SAMU_KEY_SADR                             0x0
+#define SAMU_KEY_EADR                             0x0
+#define SMU_KEY_CHAIN_ADR                         0x0
+#define SMU_KEY_SADR                              0x0
+#define SMU_KEY_EADR                              0x0
+#define SMC_MSG_TEST                              0x1
+#define SMC_MSG_PHY_LN_OFF                        0x2
+#define SMC_MSG_PHY_LN_ON                         0x3
+#define SMC_MSG_DDI_PHY_OFF                       0x4
+#define SMC_MSG_DDI_PHY_ON                        0x5
+#define SMC_MSG_CASCADE_PLL_OFF                   0x6
+#define SMC_MSG_CASCADE_PLL_ON                    0x7
+#define SMC_MSG_PWR_OFF_x16                       0x8
+#define SMC_MSG_CONFIG_LCLK_DPM                   0x9
+#define SMC_MSG_FLUSH_DATA_CACHE                  0xa
+#define SMC_MSG_FLUSH_INSTRUCTION_CACHE           0xb
+#define SMC_MSG_CONFIG_VPC_ACCUMULATOR            0xc
+#define SMC_MSG_CONFIG_BAPM                       0xd
+#define SMC_MSG_CONFIG_TDC_LIMIT                  0xe
+#define SMC_MSG_CONFIG_LPMx                       0xf
+#define SMC_MSG_CONFIG_HTC_LIMIT                  0x10
+#define SMC_MSG_CONFIG_THERMAL_CNTL               0x11
+#define SMC_MSG_CONFIG_VOLTAGE_CNTL               0x12
+#define SMC_MSG_CONFIG_TDP_CNTL                   0x13
+#define SMC_MSG_EN_PM_CNTL                        0x14
+#define SMC_MSG_DIS_PM_CNTL                       0x15
+#define SMC_MSG_CONFIG_NBDPM                      0x16
+#define SMC_MSG_CONFIG_LOADLINE                   0x17
+#define SMC_MSG_ADJUST_LOADLINE                   0x18
+#define SMC_MSG_RESET                             0x20
+#define SMC_MSG_VOLTAGE                           0x25
+#define SMC_VERSION_MAJOR                         0x7
+#define SMC_VERSION_MINOR                         0x0
+#define SMC_HEADER_SIZE                           0x40
+#define ROM_SIGNATURE                             0xaa55
+typedef enum SurfaceEndian {
+       ENDIAN_NONE                                      = 0x0,
+       ENDIAN_8IN16                                     = 0x1,
+       ENDIAN_8IN32                                     = 0x2,
+       ENDIAN_8IN64                                     = 0x3,
+} SurfaceEndian;
+typedef enum ArrayMode {
+       ARRAY_LINEAR_GENERAL                             = 0x0,
+       ARRAY_LINEAR_ALIGNED                             = 0x1,
+       ARRAY_1D_TILED_THIN1                             = 0x2,
+       ARRAY_1D_TILED_THICK                             = 0x3,
+       ARRAY_2D_TILED_THIN1                             = 0x4,
+       ARRAY_PRT_TILED_THIN1                            = 0x5,
+       ARRAY_PRT_2D_TILED_THIN1                         = 0x6,
+       ARRAY_2D_TILED_THICK                             = 0x7,
+       ARRAY_2D_TILED_XTHICK                            = 0x8,
+       ARRAY_PRT_TILED_THICK                            = 0x9,
+       ARRAY_PRT_2D_TILED_THICK                         = 0xa,
+       ARRAY_PRT_3D_TILED_THIN1                         = 0xb,
+       ARRAY_3D_TILED_THIN1                             = 0xc,
+       ARRAY_3D_TILED_THICK                             = 0xd,
+       ARRAY_3D_TILED_XTHICK                            = 0xe,
+       ARRAY_PRT_3D_TILED_THICK                         = 0xf,
+} ArrayMode;
+typedef enum PipeTiling {
+       CONFIG_1_PIPE                                    = 0x0,
+       CONFIG_2_PIPE                                    = 0x1,
+       CONFIG_4_PIPE                                    = 0x2,
+       CONFIG_8_PIPE                                    = 0x3,
+} PipeTiling;
+typedef enum BankTiling {
+       CONFIG_4_BANK                                    = 0x0,
+       CONFIG_8_BANK                                    = 0x1,
+} BankTiling;
+typedef enum GroupInterleave {
+       CONFIG_256B_GROUP                                = 0x0,
+       CONFIG_512B_GROUP                                = 0x1,
+} GroupInterleave;
+typedef enum RowTiling {
+       CONFIG_1KB_ROW                                   = 0x0,
+       CONFIG_2KB_ROW                                   = 0x1,
+       CONFIG_4KB_ROW                                   = 0x2,
+       CONFIG_8KB_ROW                                   = 0x3,
+       CONFIG_1KB_ROW_OPT                               = 0x4,
+       CONFIG_2KB_ROW_OPT                               = 0x5,
+       CONFIG_4KB_ROW_OPT                               = 0x6,
+       CONFIG_8KB_ROW_OPT                               = 0x7,
+} RowTiling;
+typedef enum BankSwapBytes {
+       CONFIG_128B_SWAPS                                = 0x0,
+       CONFIG_256B_SWAPS                                = 0x1,
+       CONFIG_512B_SWAPS                                = 0x2,
+       CONFIG_1KB_SWAPS                                 = 0x3,
+} BankSwapBytes;
+typedef enum SampleSplitBytes {
+       CONFIG_1KB_SPLIT                                 = 0x0,
+       CONFIG_2KB_SPLIT                                 = 0x1,
+       CONFIG_4KB_SPLIT                                 = 0x2,
+       CONFIG_8KB_SPLIT                                 = 0x3,
+} SampleSplitBytes;
+typedef enum NumPipes {
+       ADDR_CONFIG_1_PIPE                               = 0x0,
+       ADDR_CONFIG_2_PIPE                               = 0x1,
+       ADDR_CONFIG_4_PIPE                               = 0x2,
+       ADDR_CONFIG_8_PIPE                               = 0x3,
+} NumPipes;
+typedef enum PipeInterleaveSize {
+       ADDR_CONFIG_PIPE_INTERLEAVE_256B                 = 0x0,
+       ADDR_CONFIG_PIPE_INTERLEAVE_512B                 = 0x1,
+} PipeInterleaveSize;
+typedef enum BankInterleaveSize {
+       ADDR_CONFIG_BANK_INTERLEAVE_1                    = 0x0,
+       ADDR_CONFIG_BANK_INTERLEAVE_2                    = 0x1,
+       ADDR_CONFIG_BANK_INTERLEAVE_4                    = 0x2,
+       ADDR_CONFIG_BANK_INTERLEAVE_8                    = 0x3,
+} BankInterleaveSize;
+typedef enum NumShaderEngines {
+       ADDR_CONFIG_1_SHADER_ENGINE                      = 0x0,
+       ADDR_CONFIG_2_SHADER_ENGINE                      = 0x1,
+} NumShaderEngines;
+typedef enum ShaderEngineTileSize {
+       ADDR_CONFIG_SE_TILE_16                           = 0x0,
+       ADDR_CONFIG_SE_TILE_32                           = 0x1,
+} ShaderEngineTileSize;
+typedef enum NumGPUs {
+       ADDR_CONFIG_1_GPU                                = 0x0,
+       ADDR_CONFIG_2_GPU                                = 0x1,
+       ADDR_CONFIG_4_GPU                                = 0x2,
+} NumGPUs;
+typedef enum MultiGPUTileSize {
+       ADDR_CONFIG_GPU_TILE_16                          = 0x0,
+       ADDR_CONFIG_GPU_TILE_32                          = 0x1,
+       ADDR_CONFIG_GPU_TILE_64                          = 0x2,
+       ADDR_CONFIG_GPU_TILE_128                         = 0x3,
+} MultiGPUTileSize;
+typedef enum RowSize {
+       ADDR_CONFIG_1KB_ROW                              = 0x0,
+       ADDR_CONFIG_2KB_ROW                              = 0x1,
+       ADDR_CONFIG_4KB_ROW                              = 0x2,
+} RowSize;
+typedef enum NumLowerPipes {
+       ADDR_CONFIG_1_LOWER_PIPES                        = 0x0,
+       ADDR_CONFIG_2_LOWER_PIPES                        = 0x1,
+} NumLowerPipes;
+typedef enum DebugBlockId {
+       DBG_CLIENT_BLKID_RESERVED                        = 0x0,
+       DBG_CLIENT_BLKID_dbg                             = 0x1,
+       DBG_CLIENT_BLKID_uvdu_0                          = 0x2,
+       DBG_CLIENT_BLKID_uvdu_1                          = 0x3,
+       DBG_CLIENT_BLKID_uvdu_2                          = 0x4,
+       DBG_CLIENT_BLKID_uvdu_3                          = 0x5,
+       DBG_CLIENT_BLKID_uvdu_4                          = 0x6,
+       DBG_CLIENT_BLKID_uvdu_5                          = 0x7,
+       DBG_CLIENT_BLKID_uvdu_6                          = 0x8,
+       DBG_CLIENT_BLKID_uvdb_0                          = 0x9,
+       DBG_CLIENT_BLKID_uvdc_0                          = 0xa,
+       DBG_CLIENT_BLKID_uvdc_1                          = 0xb,
+       DBG_CLIENT_BLKID_uvdf_0                          = 0xc,
+       DBG_CLIENT_BLKID_uvdf_1                          = 0xd,
+       DBG_CLIENT_BLKID_uvdm_0                          = 0xe,
+       DBG_CLIENT_BLKID_uvdm_1                          = 0xf,
+       DBG_CLIENT_BLKID_uvdm_2                          = 0x10,
+       DBG_CLIENT_BLKID_uvdm_3                          = 0x11,
+       DBG_CLIENT_BLKID_vcea_0                          = 0x12,
+       DBG_CLIENT_BLKID_vcea_1                          = 0x13,
+       DBG_CLIENT_BLKID_vcea_2                          = 0x14,
+       DBG_CLIENT_BLKID_vcea_3                          = 0x15,
+       DBG_CLIENT_BLKID_vceb_0                          = 0x16,
+       DBG_CLIENT_BLKID_vcec_0                          = 0x17,
+       DBG_CLIENT_BLKID_dco                             = 0x18,
+       DBG_CLIENT_BLKID_xdma                            = 0x19,
+       DBG_CLIENT_BLKID_dci_pg                          = 0x1a,
+       DBG_CLIENT_BLKID_smu_0                           = 0x1b,
+       DBG_CLIENT_BLKID_smu_1                           = 0x1c,
+       DBG_CLIENT_BLKID_smu_2                           = 0x1d,
+       DBG_CLIENT_BLKID_gck                             = 0x1e,
+       DBG_CLIENT_BLKID_tmonw0                          = 0x1f,
+       DBG_CLIENT_BLKID_tmonw1                          = 0x20,
+       DBG_CLIENT_BLKID_grbm                            = 0x21,
+       DBG_CLIENT_BLKID_rlc                             = 0x22,
+       DBG_CLIENT_BLKID_ds0                             = 0x23,
+       DBG_CLIENT_BLKID_cpg_0                           = 0x24,
+       DBG_CLIENT_BLKID_cpg_1                           = 0x25,
+       DBG_CLIENT_BLKID_cpc_0                           = 0x26,
+       DBG_CLIENT_BLKID_cpc_1                           = 0x27,
+       DBG_CLIENT_BLKID_cpf_0                           = 0x28,
+       DBG_CLIENT_BLKID_cpf_1                           = 0x29,
+       DBG_CLIENT_BLKID_scf0                            = 0x2a,
+       DBG_CLIENT_BLKID_scf1                            = 0x2b,
+       DBG_CLIENT_BLKID_scf2                            = 0x2c,
+       DBG_CLIENT_BLKID_scf3                            = 0x2d,
+       DBG_CLIENT_BLKID_pc0                             = 0x2e,
+       DBG_CLIENT_BLKID_pc1                             = 0x2f,
+       DBG_CLIENT_BLKID_pc2                             = 0x30,
+       DBG_CLIENT_BLKID_pc3                             = 0x31,
+       DBG_CLIENT_BLKID_vgt0                            = 0x32,
+       DBG_CLIENT_BLKID_vgt1                            = 0x33,
+       DBG_CLIENT_BLKID_vgt2                            = 0x34,
+       DBG_CLIENT_BLKID_vgt3                            = 0x35,
+       DBG_CLIENT_BLKID_sx00                            = 0x36,
+       DBG_CLIENT_BLKID_sx10                            = 0x37,
+       DBG_CLIENT_BLKID_sx20                            = 0x38,
+       DBG_CLIENT_BLKID_sx30                            = 0x39,
+       DBG_CLIENT_BLKID_cb001                           = 0x3a,
+       DBG_CLIENT_BLKID_cb200                           = 0x3b,
+       DBG_CLIENT_BLKID_cb201                           = 0x3c,
+       DBG_CLIENT_BLKID_cbr0                            = 0x3d,
+       DBG_CLIENT_BLKID_cb000                           = 0x3e,
+       DBG_CLIENT_BLKID_cb101                           = 0x3f,
+       DBG_CLIENT_BLKID_cb300                           = 0x40,
+       DBG_CLIENT_BLKID_cb301                           = 0x41,
+       DBG_CLIENT_BLKID_cbr1                            = 0x42,
+       DBG_CLIENT_BLKID_cb100                           = 0x43,
+       DBG_CLIENT_BLKID_ia0                             = 0x44,
+       DBG_CLIENT_BLKID_ia1                             = 0x45,
+       DBG_CLIENT_BLKID_bci0                            = 0x46,
+       DBG_CLIENT_BLKID_bci1                            = 0x47,
+       DBG_CLIENT_BLKID_bci2                            = 0x48,
+       DBG_CLIENT_BLKID_bci3                            = 0x49,
+       DBG_CLIENT_BLKID_pa0                             = 0x4a,
+       DBG_CLIENT_BLKID_pa1                             = 0x4b,
+       DBG_CLIENT_BLKID_spim0                           = 0x4c,
+       DBG_CLIENT_BLKID_spim1                           = 0x4d,
+       DBG_CLIENT_BLKID_spim2                           = 0x4e,
+       DBG_CLIENT_BLKID_spim3                           = 0x4f,
+       DBG_CLIENT_BLKID_sdma                            = 0x50,
+       DBG_CLIENT_BLKID_ih                              = 0x51,
+       DBG_CLIENT_BLKID_sem                             = 0x52,
+       DBG_CLIENT_BLKID_srbm                            = 0x53,
+       DBG_CLIENT_BLKID_hdp                             = 0x54,
+       DBG_CLIENT_BLKID_acp_0                           = 0x55,
+       DBG_CLIENT_BLKID_acp_1                           = 0x56,
+       DBG_CLIENT_BLKID_sam                             = 0x57,
+       DBG_CLIENT_BLKID_mcc0                            = 0x58,
+       DBG_CLIENT_BLKID_mcc1                            = 0x59,
+       DBG_CLIENT_BLKID_mcc2                            = 0x5a,
+       DBG_CLIENT_BLKID_mcc3                            = 0x5b,
+       DBG_CLIENT_BLKID_mcd0                            = 0x5c,
+       DBG_CLIENT_BLKID_mcd1                            = 0x5d,
+       DBG_CLIENT_BLKID_mcd2                            = 0x5e,
+       DBG_CLIENT_BLKID_mcd3                            = 0x5f,
+       DBG_CLIENT_BLKID_mcb                             = 0x60,
+       DBG_CLIENT_BLKID_vmc                             = 0x61,
+       DBG_CLIENT_BLKID_gmcon                           = 0x62,
+       DBG_CLIENT_BLKID_gdc_0                           = 0x63,
+       DBG_CLIENT_BLKID_gdc_1                           = 0x64,
+       DBG_CLIENT_BLKID_gdc_2                           = 0x65,
+       DBG_CLIENT_BLKID_gdc_3                           = 0x66,
+       DBG_CLIENT_BLKID_gdc_4                           = 0x67,
+       DBG_CLIENT_BLKID_gdc_5                           = 0x68,
+       DBG_CLIENT_BLKID_gdc_6                           = 0x69,
+       DBG_CLIENT_BLKID_gdc_7                           = 0x6a,
+       DBG_CLIENT_BLKID_gdc_8                           = 0x6b,
+       DBG_CLIENT_BLKID_gdc_9                           = 0x6c,
+       DBG_CLIENT_BLKID_gdc_10                          = 0x6d,
+       DBG_CLIENT_BLKID_gdc_11                          = 0x6e,
+       DBG_CLIENT_BLKID_gdc_12                          = 0x6f,
+       DBG_CLIENT_BLKID_gdc_13                          = 0x70,
+       DBG_CLIENT_BLKID_gdc_14                          = 0x71,
+       DBG_CLIENT_BLKID_gdc_15                          = 0x72,
+       DBG_CLIENT_BLKID_gdc_16                          = 0x73,
+       DBG_CLIENT_BLKID_gdc_17                          = 0x74,
+       DBG_CLIENT_BLKID_gdc_18                          = 0x75,
+       DBG_CLIENT_BLKID_gdc_19                          = 0x76,
+       DBG_CLIENT_BLKID_gdc_20                          = 0x77,
+       DBG_CLIENT_BLKID_gdc_21                          = 0x78,
+       DBG_CLIENT_BLKID_gdc_22                          = 0x79,
+       DBG_CLIENT_BLKID_gdc_23                          = 0x7a,
+       DBG_CLIENT_BLKID_gdc_24                          = 0x7b,
+       DBG_CLIENT_BLKID_gdc_25                          = 0x7c,
+       DBG_CLIENT_BLKID_gdc_26                          = 0x7d,
+       DBG_CLIENT_BLKID_gdc_27                          = 0x7e,
+       DBG_CLIENT_BLKID_gdc_28                          = 0x7f,
+       DBG_CLIENT_BLKID_wd                              = 0x80,
+       DBG_CLIENT_BLKID_sdma_0                          = 0x81,
+       DBG_CLIENT_BLKID_sdma_1                          = 0x82,
+       DBG_CLIENT_BLKID_sammsp                          = 0x83,
+       DBG_CLIENT_BLKID_dci_0                           = 0x84,
+       DBG_CLIENT_BLKID_dccg0_0                         = 0x85,
+       DBG_CLIENT_BLKID_dcfe01_0                        = 0x86,
+       DBG_CLIENT_BLKID_dcfe02_0                        = 0x87,
+       DBG_CLIENT_BLKID_dcfe03_0                        = 0x88,
+       DBG_CLIENT_BLKID_dccg0_1                         = 0x89,
+} DebugBlockId;
+typedef enum DebugBlockId_OLD {
+       DBG_BLOCK_ID_RESERVED                            = 0x0,
+       DBG_BLOCK_ID_DBG                                 = 0x1,
+       DBG_BLOCK_ID_VMC                                 = 0x2,
+       DBG_BLOCK_ID_PDMA                                = 0x3,
+       DBG_BLOCK_ID_CG                                  = 0x4,
+       DBG_BLOCK_ID_SRBM                                = 0x5,
+       DBG_BLOCK_ID_GRBM                                = 0x6,
+       DBG_BLOCK_ID_RLC                                 = 0x7,
+       DBG_BLOCK_ID_CSC                                 = 0x8,
+       DBG_BLOCK_ID_SEM                                 = 0x9,
+       DBG_BLOCK_ID_IH                                  = 0xa,
+       DBG_BLOCK_ID_SC                                  = 0xb,
+       DBG_BLOCK_ID_SQ                                  = 0xc,
+       DBG_BLOCK_ID_AVP                                 = 0xd,
+       DBG_BLOCK_ID_GMCON                               = 0xe,
+       DBG_BLOCK_ID_SMU                                 = 0xf,
+       DBG_BLOCK_ID_DMA0                                = 0x10,
+       DBG_BLOCK_ID_DMA1                                = 0x11,
+       DBG_BLOCK_ID_SPIM                                = 0x12,
+       DBG_BLOCK_ID_GDS                                 = 0x13,
+       DBG_BLOCK_ID_SPIS                                = 0x14,
+       DBG_BLOCK_ID_UNUSED0                             = 0x15,
+       DBG_BLOCK_ID_PA0                                 = 0x16,
+       DBG_BLOCK_ID_PA1                                 = 0x17,
+       DBG_BLOCK_ID_CP0                                 = 0x18,
+       DBG_BLOCK_ID_CP1                                 = 0x19,
+       DBG_BLOCK_ID_CP2                                 = 0x1a,
+       DBG_BLOCK_ID_UNUSED1                             = 0x1b,
+       DBG_BLOCK_ID_UVDU                                = 0x1c,
+       DBG_BLOCK_ID_UVDM                                = 0x1d,
+       DBG_BLOCK_ID_VCE                                 = 0x1e,
+       DBG_BLOCK_ID_UNUSED2                             = 0x1f,
+       DBG_BLOCK_ID_VGT0                                = 0x20,
+       DBG_BLOCK_ID_VGT1                                = 0x21,
+       DBG_BLOCK_ID_IA                                  = 0x22,
+       DBG_BLOCK_ID_UNUSED3                             = 0x23,
+       DBG_BLOCK_ID_SCT0                                = 0x24,
+       DBG_BLOCK_ID_SCT1                                = 0x25,
+       DBG_BLOCK_ID_SPM0                                = 0x26,
+       DBG_BLOCK_ID_SPM1                                = 0x27,
+       DBG_BLOCK_ID_TCAA                                = 0x28,
+       DBG_BLOCK_ID_TCAB                                = 0x29,
+       DBG_BLOCK_ID_TCCA                                = 0x2a,
+       DBG_BLOCK_ID_TCCB                                = 0x2b,
+       DBG_BLOCK_ID_MCC0                                = 0x2c,
+       DBG_BLOCK_ID_MCC1                                = 0x2d,
+       DBG_BLOCK_ID_MCC2                                = 0x2e,
+       DBG_BLOCK_ID_MCC3                                = 0x2f,
+       DBG_BLOCK_ID_SX0                                 = 0x30,
+       DBG_BLOCK_ID_SX1                                 = 0x31,
+       DBG_BLOCK_ID_SX2                                 = 0x32,
+       DBG_BLOCK_ID_SX3                                 = 0x33,
+       DBG_BLOCK_ID_UNUSED4                             = 0x34,
+       DBG_BLOCK_ID_UNUSED5                             = 0x35,
+       DBG_BLOCK_ID_UNUSED6                             = 0x36,
+       DBG_BLOCK_ID_UNUSED7                             = 0x37,
+       DBG_BLOCK_ID_PC0                                 = 0x38,
+       DBG_BLOCK_ID_PC1                                 = 0x39,
+       DBG_BLOCK_ID_UNUSED8                             = 0x3a,
+       DBG_BLOCK_ID_UNUSED9                             = 0x3b,
+       DBG_BLOCK_ID_UNUSED10                            = 0x3c,
+       DBG_BLOCK_ID_UNUSED11                            = 0x3d,
+       DBG_BLOCK_ID_MCB                                 = 0x3e,
+       DBG_BLOCK_ID_UNUSED12                            = 0x3f,
+       DBG_BLOCK_ID_SCB0                                = 0x40,
+       DBG_BLOCK_ID_SCB1                                = 0x41,
+       DBG_BLOCK_ID_UNUSED13                            = 0x42,
+       DBG_BLOCK_ID_UNUSED14                            = 0x43,
+       DBG_BLOCK_ID_SCF0                                = 0x44,
+       DBG_BLOCK_ID_SCF1                                = 0x45,
+       DBG_BLOCK_ID_UNUSED15                            = 0x46,
+       DBG_BLOCK_ID_UNUSED16                            = 0x47,
+       DBG_BLOCK_ID_BCI0                                = 0x48,
+       DBG_BLOCK_ID_BCI1                                = 0x49,
+       DBG_BLOCK_ID_BCI2                                = 0x4a,
+       DBG_BLOCK_ID_BCI3                                = 0x4b,
+       DBG_BLOCK_ID_UNUSED17                            = 0x4c,
+       DBG_BLOCK_ID_UNUSED18                            = 0x4d,
+       DBG_BLOCK_ID_UNUSED19                            = 0x4e,
+       DBG_BLOCK_ID_UNUSED20                            = 0x4f,
+       DBG_BLOCK_ID_CB00                                = 0x50,
+       DBG_BLOCK_ID_CB01                                = 0x51,
+       DBG_BLOCK_ID_CB02                                = 0x52,
+       DBG_BLOCK_ID_CB03                                = 0x53,
+       DBG_BLOCK_ID_CB04                                = 0x54,
+       DBG_BLOCK_ID_UNUSED21                            = 0x55,
+       DBG_BLOCK_ID_UNUSED22                            = 0x56,
+       DBG_BLOCK_ID_UNUSED23                            = 0x57,
+       DBG_BLOCK_ID_CB10                                = 0x58,
+       DBG_BLOCK_ID_CB11                                = 0x59,
+       DBG_BLOCK_ID_CB12                                = 0x5a,
+       DBG_BLOCK_ID_CB13                                = 0x5b,
+       DBG_BLOCK_ID_CB14                                = 0x5c,
+       DBG_BLOCK_ID_UNUSED24                            = 0x5d,
+       DBG_BLOCK_ID_UNUSED25                            = 0x5e,
+       DBG_BLOCK_ID_UNUSED26                            = 0x5f,
+       DBG_BLOCK_ID_TCP0                                = 0x60,
+       DBG_BLOCK_ID_TCP1                                = 0x61,
+       DBG_BLOCK_ID_TCP2                                = 0x62,
+       DBG_BLOCK_ID_TCP3                                = 0x63,
+       DBG_BLOCK_ID_TCP4                                = 0x64,
+       DBG_BLOCK_ID_TCP5                                = 0x65,
+       DBG_BLOCK_ID_TCP6                                = 0x66,
+       DBG_BLOCK_ID_TCP7                                = 0x67,
+       DBG_BLOCK_ID_TCP8                                = 0x68,
+       DBG_BLOCK_ID_TCP9                                = 0x69,
+       DBG_BLOCK_ID_TCP10                               = 0x6a,
+       DBG_BLOCK_ID_TCP11                               = 0x6b,
+       DBG_BLOCK_ID_TCP12                               = 0x6c,
+       DBG_BLOCK_ID_TCP13                               = 0x6d,
+       DBG_BLOCK_ID_TCP14                               = 0x6e,
+       DBG_BLOCK_ID_TCP15                               = 0x6f,
+       DBG_BLOCK_ID_TCP16                               = 0x70,
+       DBG_BLOCK_ID_TCP17                               = 0x71,
+       DBG_BLOCK_ID_TCP18                               = 0x72,
+       DBG_BLOCK_ID_TCP19                               = 0x73,
+       DBG_BLOCK_ID_TCP20                               = 0x74,
+       DBG_BLOCK_ID_TCP21                               = 0x75,
+       DBG_BLOCK_ID_TCP22                               = 0x76,
+       DBG_BLOCK_ID_TCP23                               = 0x77,
+       DBG_BLOCK_ID_TCP_RESERVED0                       = 0x78,
+       DBG_BLOCK_ID_TCP_RESERVED1                       = 0x79,
+       DBG_BLOCK_ID_TCP_RESERVED2                       = 0x7a,
+       DBG_BLOCK_ID_TCP_RESERVED3                       = 0x7b,
+       DBG_BLOCK_ID_TCP_RESERVED4                       = 0x7c,
+       DBG_BLOCK_ID_TCP_RESERVED5                       = 0x7d,
+       DBG_BLOCK_ID_TCP_RESERVED6                       = 0x7e,
+       DBG_BLOCK_ID_TCP_RESERVED7                       = 0x7f,
+       DBG_BLOCK_ID_DB00                                = 0x80,
+       DBG_BLOCK_ID_DB01                                = 0x81,
+       DBG_BLOCK_ID_DB02                                = 0x82,
+       DBG_BLOCK_ID_DB03                                = 0x83,
+       DBG_BLOCK_ID_DB04                                = 0x84,
+       DBG_BLOCK_ID_UNUSED27                            = 0x85,
+       DBG_BLOCK_ID_UNUSED28                            = 0x86,
+       DBG_BLOCK_ID_UNUSED29                            = 0x87,
+       DBG_BLOCK_ID_DB10                                = 0x88,
+       DBG_BLOCK_ID_DB11                                = 0x89,
+       DBG_BLOCK_ID_DB12                                = 0x8a,
+       DBG_BLOCK_ID_DB13                                = 0x8b,
+       DBG_BLOCK_ID_DB14                                = 0x8c,
+       DBG_BLOCK_ID_UNUSED30                            = 0x8d,
+       DBG_BLOCK_ID_UNUSED31                            = 0x8e,
+       DBG_BLOCK_ID_UNUSED32                            = 0x8f,
+       DBG_BLOCK_ID_TCC0                                = 0x90,
+       DBG_BLOCK_ID_TCC1                                = 0x91,
+       DBG_BLOCK_ID_TCC2                                = 0x92,
+       DBG_BLOCK_ID_TCC3                                = 0x93,
+       DBG_BLOCK_ID_TCC4                                = 0x94,
+       DBG_BLOCK_ID_TCC5                                = 0x95,
+       DBG_BLOCK_ID_TCC6                                = 0x96,
+       DBG_BLOCK_ID_TCC7                                = 0x97,
+       DBG_BLOCK_ID_SPS00                               = 0x98,
+       DBG_BLOCK_ID_SPS01                               = 0x99,
+       DBG_BLOCK_ID_SPS02                               = 0x9a,
+       DBG_BLOCK_ID_SPS10                               = 0x9b,
+       DBG_BLOCK_ID_SPS11                               = 0x9c,
+       DBG_BLOCK_ID_SPS12                               = 0x9d,
+       DBG_BLOCK_ID_UNUSED33                            = 0x9e,
+       DBG_BLOCK_ID_UNUSED34                            = 0x9f,
+       DBG_BLOCK_ID_TA00                                = 0xa0,
+       DBG_BLOCK_ID_TA01                                = 0xa1,
+       DBG_BLOCK_ID_TA02                                = 0xa2,
+       DBG_BLOCK_ID_TA03                                = 0xa3,
+       DBG_BLOCK_ID_TA04                                = 0xa4,
+       DBG_BLOCK_ID_TA05                                = 0xa5,
+       DBG_BLOCK_ID_TA06                                = 0xa6,
+       DBG_BLOCK_ID_TA07                                = 0xa7,
+       DBG_BLOCK_ID_TA08                                = 0xa8,
+       DBG_BLOCK_ID_TA09                                = 0xa9,
+       DBG_BLOCK_ID_TA0A                                = 0xaa,
+       DBG_BLOCK_ID_TA0B                                = 0xab,
+       DBG_BLOCK_ID_UNUSED35                            = 0xac,
+       DBG_BLOCK_ID_UNUSED36                            = 0xad,
+       DBG_BLOCK_ID_UNUSED37                            = 0xae,
+       DBG_BLOCK_ID_UNUSED38                            = 0xaf,
+       DBG_BLOCK_ID_TA10                                = 0xb0,
+       DBG_BLOCK_ID_TA11                                = 0xb1,
+       DBG_BLOCK_ID_TA12                                = 0xb2,
+       DBG_BLOCK_ID_TA13                                = 0xb3,
+       DBG_BLOCK_ID_TA14                                = 0xb4,
+       DBG_BLOCK_ID_TA15                                = 0xb5,
+       DBG_BLOCK_ID_TA16                                = 0xb6,
+       DBG_BLOCK_ID_TA17                                = 0xb7,
+       DBG_BLOCK_ID_TA18                                = 0xb8,
+       DBG_BLOCK_ID_TA19                                = 0xb9,
+       DBG_BLOCK_ID_TA1A                                = 0xba,
+       DBG_BLOCK_ID_TA1B                                = 0xbb,
+       DBG_BLOCK_ID_UNUSED39                            = 0xbc,
+       DBG_BLOCK_ID_UNUSED40                            = 0xbd,
+       DBG_BLOCK_ID_UNUSED41                            = 0xbe,
+       DBG_BLOCK_ID_UNUSED42                            = 0xbf,
+       DBG_BLOCK_ID_TD00                                = 0xc0,
+       DBG_BLOCK_ID_TD01                                = 0xc1,
+       DBG_BLOCK_ID_TD02                                = 0xc2,
+       DBG_BLOCK_ID_TD03                                = 0xc3,
+       DBG_BLOCK_ID_TD04                                = 0xc4,
+       DBG_BLOCK_ID_TD05                                = 0xc5,
+       DBG_BLOCK_ID_TD06                                = 0xc6,
+       DBG_BLOCK_ID_TD07                                = 0xc7,
+       DBG_BLOCK_ID_TD08                                = 0xc8,
+       DBG_BLOCK_ID_TD09                                = 0xc9,
+       DBG_BLOCK_ID_TD0A                                = 0xca,
+       DBG_BLOCK_ID_TD0B                                = 0xcb,
+       DBG_BLOCK_ID_UNUSED43                            = 0xcc,
+       DBG_BLOCK_ID_UNUSED44                            = 0xcd,
+       DBG_BLOCK_ID_UNUSED45                            = 0xce,
+       DBG_BLOCK_ID_UNUSED46                            = 0xcf,
+       DBG_BLOCK_ID_TD10                                = 0xd0,
+       DBG_BLOCK_ID_TD11                                = 0xd1,
+       DBG_BLOCK_ID_TD12                                = 0xd2,
+       DBG_BLOCK_ID_TD13                                = 0xd3,
+       DBG_BLOCK_ID_TD14                                = 0xd4,
+       DBG_BLOCK_ID_TD15                                = 0xd5,
+       DBG_BLOCK_ID_TD16                                = 0xd6,
+       DBG_BLOCK_ID_TD17                                = 0xd7,
+       DBG_BLOCK_ID_TD18                                = 0xd8,
+       DBG_BLOCK_ID_TD19                                = 0xd9,
+       DBG_BLOCK_ID_TD1A                                = 0xda,
+       DBG_BLOCK_ID_TD1B                                = 0xdb,
+       DBG_BLOCK_ID_UNUSED47                            = 0xdc,
+       DBG_BLOCK_ID_UNUSED48                            = 0xdd,
+       DBG_BLOCK_ID_UNUSED49                            = 0xde,
+       DBG_BLOCK_ID_UNUSED50                            = 0xdf,
+       DBG_BLOCK_ID_MCD0                                = 0xe0,
+       DBG_BLOCK_ID_MCD1                                = 0xe1,
+       DBG_BLOCK_ID_MCD2                                = 0xe2,
+       DBG_BLOCK_ID_MCD3                                = 0xe3,
+       DBG_BLOCK_ID_MCD4                                = 0xe4,
+       DBG_BLOCK_ID_MCD5                                = 0xe5,
+       DBG_BLOCK_ID_UNUSED51                            = 0xe6,
+       DBG_BLOCK_ID_UNUSED52                            = 0xe7,
+} DebugBlockId_OLD;
+typedef enum DebugBlockId_BY2 {
+       DBG_BLOCK_ID_RESERVED_BY2                        = 0x0,
+       DBG_BLOCK_ID_VMC_BY2                             = 0x1,
+       DBG_BLOCK_ID_CG_BY2                              = 0x2,
+       DBG_BLOCK_ID_GRBM_BY2                            = 0x3,
+       DBG_BLOCK_ID_CSC_BY2                             = 0x4,
+       DBG_BLOCK_ID_IH_BY2                              = 0x5,
+       DBG_BLOCK_ID_SQ_BY2                              = 0x6,
+       DBG_BLOCK_ID_GMCON_BY2                           = 0x7,
+       DBG_BLOCK_ID_DMA0_BY2                            = 0x8,
+       DBG_BLOCK_ID_SPIM_BY2                            = 0x9,
+       DBG_BLOCK_ID_SPIS_BY2                            = 0xa,
+       DBG_BLOCK_ID_PA0_BY2                             = 0xb,
+       DBG_BLOCK_ID_CP0_BY2                             = 0xc,
+       DBG_BLOCK_ID_CP2_BY2                             = 0xd,
+       DBG_BLOCK_ID_UVDU_BY2                            = 0xe,
+       DBG_BLOCK_ID_VCE_BY2                             = 0xf,
+       DBG_BLOCK_ID_VGT0_BY2                            = 0x10,
+       DBG_BLOCK_ID_IA_BY2                              = 0x11,
+       DBG_BLOCK_ID_SCT0_BY2                            = 0x12,
+       DBG_BLOCK_ID_SPM0_BY2                            = 0x13,
+       DBG_BLOCK_ID_TCAA_BY2                            = 0x14,
+       DBG_BLOCK_ID_TCCA_BY2                            = 0x15,
+       DBG_BLOCK_ID_MCC0_BY2                            = 0x16,
+       DBG_BLOCK_ID_MCC2_BY2                            = 0x17,
+       DBG_BLOCK_ID_SX0_BY2                             = 0x18,
+       DBG_BLOCK_ID_SX2_BY2                             = 0x19,
+       DBG_BLOCK_ID_UNUSED4_BY2                         = 0x1a,
+       DBG_BLOCK_ID_UNUSED6_BY2                         = 0x1b,
+       DBG_BLOCK_ID_PC0_BY2                             = 0x1c,
+       DBG_BLOCK_ID_UNUSED8_BY2                         = 0x1d,
+       DBG_BLOCK_ID_UNUSED10_BY2                        = 0x1e,
+       DBG_BLOCK_ID_MCB_BY2                             = 0x1f,
+       DBG_BLOCK_ID_SCB0_BY2                            = 0x20,
+       DBG_BLOCK_ID_UNUSED13_BY2                        = 0x21,
+       DBG_BLOCK_ID_SCF0_BY2                            = 0x22,
+       DBG_BLOCK_ID_UNUSED15_BY2                        = 0x23,
+       DBG_BLOCK_ID_BCI0_BY2                            = 0x24,
+       DBG_BLOCK_ID_BCI2_BY2                            = 0x25,
+       DBG_BLOCK_ID_UNUSED17_BY2                        = 0x26,
+       DBG_BLOCK_ID_UNUSED19_BY2                        = 0x27,
+       DBG_BLOCK_ID_CB00_BY2                            = 0x28,
+       DBG_BLOCK_ID_CB02_BY2                            = 0x29,
+       DBG_BLOCK_ID_CB04_BY2                            = 0x2a,
+       DBG_BLOCK_ID_UNUSED22_BY2                        = 0x2b,
+       DBG_BLOCK_ID_CB10_BY2                            = 0x2c,
+       DBG_BLOCK_ID_CB12_BY2                            = 0x2d,
+       DBG_BLOCK_ID_CB14_BY2                            = 0x2e,
+       DBG_BLOCK_ID_UNUSED25_BY2                        = 0x2f,
+       DBG_BLOCK_ID_TCP0_BY2                            = 0x30,
+       DBG_BLOCK_ID_TCP2_BY2                            = 0x31,
+       DBG_BLOCK_ID_TCP4_BY2                            = 0x32,
+       DBG_BLOCK_ID_TCP6_BY2                            = 0x33,
+       DBG_BLOCK_ID_TCP8_BY2                            = 0x34,
+       DBG_BLOCK_ID_TCP10_BY2                           = 0x35,
+       DBG_BLOCK_ID_TCP12_BY2                           = 0x36,
+       DBG_BLOCK_ID_TCP14_BY2                           = 0x37,
+       DBG_BLOCK_ID_TCP16_BY2                           = 0x38,
+       DBG_BLOCK_ID_TCP18_BY2                           = 0x39,
+       DBG_BLOCK_ID_TCP20_BY2                           = 0x3a,
+       DBG_BLOCK_ID_TCP22_BY2                           = 0x3b,
+       DBG_BLOCK_ID_TCP_RESERVED0_BY2                   = 0x3c,
+       DBG_BLOCK_ID_TCP_RESERVED2_BY2                   = 0x3d,
+       DBG_BLOCK_ID_TCP_RESERVED4_BY2                   = 0x3e,
+       DBG_BLOCK_ID_TCP_RESERVED6_BY2                   = 0x3f,
+       DBG_BLOCK_ID_DB00_BY2                            = 0x40,
+       DBG_BLOCK_ID_DB02_BY2                            = 0x41,
+       DBG_BLOCK_ID_DB04_BY2                            = 0x42,
+       DBG_BLOCK_ID_UNUSED28_BY2                        = 0x43,
+       DBG_BLOCK_ID_DB10_BY2                            = 0x44,
+       DBG_BLOCK_ID_DB12_BY2                            = 0x45,
+       DBG_BLOCK_ID_DB14_BY2                            = 0x46,
+       DBG_BLOCK_ID_UNUSED31_BY2                        = 0x47,
+       DBG_BLOCK_ID_TCC0_BY2                            = 0x48,
+       DBG_BLOCK_ID_TCC2_BY2                            = 0x49,
+       DBG_BLOCK_ID_TCC4_BY2                            = 0x4a,
+       DBG_BLOCK_ID_TCC6_BY2                            = 0x4b,
+       DBG_BLOCK_ID_SPS00_BY2                           = 0x4c,
+       DBG_BLOCK_ID_SPS02_BY2                           = 0x4d,
+       DBG_BLOCK_ID_SPS11_BY2                           = 0x4e,
+       DBG_BLOCK_ID_UNUSED33_BY2                        = 0x4f,
+       DBG_BLOCK_ID_TA00_BY2                            = 0x50,
+       DBG_BLOCK_ID_TA02_BY2                            = 0x51,
+       DBG_BLOCK_ID_TA04_BY2                            = 0x52,
+       DBG_BLOCK_ID_TA06_BY2                            = 0x53,
+       DBG_BLOCK_ID_TA08_BY2                            = 0x54,
+       DBG_BLOCK_ID_TA0A_BY2                            = 0x55,
+       DBG_BLOCK_ID_UNUSED35_BY2                        = 0x56,
+       DBG_BLOCK_ID_UNUSED37_BY2                        = 0x57,
+       DBG_BLOCK_ID_TA10_BY2                            = 0x58,
+       DBG_BLOCK_ID_TA12_BY2                            = 0x59,
+       DBG_BLOCK_ID_TA14_BY2                            = 0x5a,
+       DBG_BLOCK_ID_TA16_BY2                            = 0x5b,
+       DBG_BLOCK_ID_TA18_BY2                            = 0x5c,
+       DBG_BLOCK_ID_TA1A_BY2                            = 0x5d,
+       DBG_BLOCK_ID_UNUSED39_BY2                        = 0x5e,
+       DBG_BLOCK_ID_UNUSED41_BY2                        = 0x5f,
+       DBG_BLOCK_ID_TD00_BY2                            = 0x60,
+       DBG_BLOCK_ID_TD02_BY2                            = 0x61,
+       DBG_BLOCK_ID_TD04_BY2                            = 0x62,
+       DBG_BLOCK_ID_TD06_BY2                            = 0x63,
+       DBG_BLOCK_ID_TD08_BY2                            = 0x64,
+       DBG_BLOCK_ID_TD0A_BY2                            = 0x65,
+       DBG_BLOCK_ID_UNUSED43_BY2                        = 0x66,
+       DBG_BLOCK_ID_UNUSED45_BY2                        = 0x67,
+       DBG_BLOCK_ID_TD10_BY2                            = 0x68,
+       DBG_BLOCK_ID_TD12_BY2                            = 0x69,
+       DBG_BLOCK_ID_TD14_BY2                            = 0x6a,
+       DBG_BLOCK_ID_TD16_BY2                            = 0x6b,
+       DBG_BLOCK_ID_TD18_BY2                            = 0x6c,
+       DBG_BLOCK_ID_TD1A_BY2                            = 0x6d,
+       DBG_BLOCK_ID_UNUSED47_BY2                        = 0x6e,
+       DBG_BLOCK_ID_UNUSED49_BY2                        = 0x6f,
+       DBG_BLOCK_ID_MCD0_BY2                            = 0x70,
+       DBG_BLOCK_ID_MCD2_BY2                            = 0x71,
+       DBG_BLOCK_ID_MCD4_BY2                            = 0x72,
+       DBG_BLOCK_ID_UNUSED51_BY2                        = 0x73,
+} DebugBlockId_BY2;
+typedef enum DebugBlockId_BY4 {
+       DBG_BLOCK_ID_RESERVED_BY4                        = 0x0,
+       DBG_BLOCK_ID_CG_BY4                              = 0x1,
+       DBG_BLOCK_ID_CSC_BY4                             = 0x2,
+       DBG_BLOCK_ID_SQ_BY4                              = 0x3,
+       DBG_BLOCK_ID_DMA0_BY4                            = 0x4,
+       DBG_BLOCK_ID_SPIS_BY4                            = 0x5,
+       DBG_BLOCK_ID_CP0_BY4                             = 0x6,
+       DBG_BLOCK_ID_UVDU_BY4                            = 0x7,
+       DBG_BLOCK_ID_VGT0_BY4                            = 0x8,
+       DBG_BLOCK_ID_SCT0_BY4                            = 0x9,
+       DBG_BLOCK_ID_TCAA_BY4                            = 0xa,
+       DBG_BLOCK_ID_MCC0_BY4                            = 0xb,
+       DBG_BLOCK_ID_SX0_BY4                             = 0xc,
+       DBG_BLOCK_ID_UNUSED4_BY4                         = 0xd,
+       DBG_BLOCK_ID_PC0_BY4                             = 0xe,
+       DBG_BLOCK_ID_UNUSED10_BY4                        = 0xf,
+       DBG_BLOCK_ID_SCB0_BY4                            = 0x10,
+       DBG_BLOCK_ID_SCF0_BY4                            = 0x11,
+       DBG_BLOCK_ID_BCI0_BY4                            = 0x12,
+       DBG_BLOCK_ID_UNUSED17_BY4                        = 0x13,
+       DBG_BLOCK_ID_CB00_BY4                            = 0x14,
+       DBG_BLOCK_ID_CB04_BY4                            = 0x15,
+       DBG_BLOCK_ID_CB10_BY4                            = 0x16,
+       DBG_BLOCK_ID_CB14_BY4                            = 0x17,
+       DBG_BLOCK_ID_TCP0_BY4                            = 0x18,
+       DBG_BLOCK_ID_TCP4_BY4                            = 0x19,
+       DBG_BLOCK_ID_TCP8_BY4                            = 0x1a,
+       DBG_BLOCK_ID_TCP12_BY4                           = 0x1b,
+       DBG_BLOCK_ID_TCP16_BY4                           = 0x1c,
+       DBG_BLOCK_ID_TCP20_BY4                           = 0x1d,
+       DBG_BLOCK_ID_TCP_RESERVED0_BY4                   = 0x1e,
+       DBG_BLOCK_ID_TCP_RESERVED4_BY4                   = 0x1f,
+       DBG_BLOCK_ID_DB_BY4                              = 0x20,
+       DBG_BLOCK_ID_DB04_BY4                            = 0x21,
+       DBG_BLOCK_ID_DB10_BY4                            = 0x22,
+       DBG_BLOCK_ID_DB14_BY4                            = 0x23,
+       DBG_BLOCK_ID_TCC0_BY4                            = 0x24,
+       DBG_BLOCK_ID_TCC4_BY4                            = 0x25,
+       DBG_BLOCK_ID_SPS00_BY4                           = 0x26,
+       DBG_BLOCK_ID_SPS11_BY4                           = 0x27,
+       DBG_BLOCK_ID_TA00_BY4                            = 0x28,
+       DBG_BLOCK_ID_TA04_BY4                            = 0x29,
+       DBG_BLOCK_ID_TA08_BY4                            = 0x2a,
+       DBG_BLOCK_ID_UNUSED35_BY4                        = 0x2b,
+       DBG_BLOCK_ID_TA10_BY4                            = 0x2c,
+       DBG_BLOCK_ID_TA14_BY4                            = 0x2d,
+       DBG_BLOCK_ID_TA18_BY4                            = 0x2e,
+       DBG_BLOCK_ID_UNUSED39_BY4                        = 0x2f,
+       DBG_BLOCK_ID_TD00_BY4                            = 0x30,
+       DBG_BLOCK_ID_TD04_BY4                            = 0x31,
+       DBG_BLOCK_ID_TD08_BY4                            = 0x32,
+       DBG_BLOCK_ID_UNUSED43_BY4                        = 0x33,
+       DBG_BLOCK_ID_TD10_BY4                            = 0x34,
+       DBG_BLOCK_ID_TD14_BY4                            = 0x35,
+       DBG_BLOCK_ID_TD18_BY4                            = 0x36,
+       DBG_BLOCK_ID_UNUSED47_BY4                        = 0x37,
+       DBG_BLOCK_ID_MCD0_BY4                            = 0x38,
+       DBG_BLOCK_ID_MCD4_BY4                            = 0x39,
+} DebugBlockId_BY4;
+typedef enum DebugBlockId_BY8 {
+       DBG_BLOCK_ID_RESERVED_BY8                        = 0x0,
+       DBG_BLOCK_ID_CSC_BY8                             = 0x1,
+       DBG_BLOCK_ID_DMA0_BY8                            = 0x2,
+       DBG_BLOCK_ID_CP0_BY8                             = 0x3,
+       DBG_BLOCK_ID_VGT0_BY8                            = 0x4,
+       DBG_BLOCK_ID_TCAA_BY8                            = 0x5,
+       DBG_BLOCK_ID_SX0_BY8                             = 0x6,
+       DBG_BLOCK_ID_PC0_BY8                             = 0x7,
+       DBG_BLOCK_ID_SCB0_BY8                            = 0x8,
+       DBG_BLOCK_ID_BCI0_BY8                            = 0x9,
+       DBG_BLOCK_ID_CB00_BY8                            = 0xa,
+       DBG_BLOCK_ID_CB10_BY8                            = 0xb,
+       DBG_BLOCK_ID_TCP0_BY8                            = 0xc,
+       DBG_BLOCK_ID_TCP8_BY8                            = 0xd,
+       DBG_BLOCK_ID_TCP16_BY8                           = 0xe,
+       DBG_BLOCK_ID_TCP_RESERVED0_BY8                   = 0xf,
+       DBG_BLOCK_ID_DB00_BY8                            = 0x10,
+       DBG_BLOCK_ID_DB10_BY8                            = 0x11,
+       DBG_BLOCK_ID_TCC0_BY8                            = 0x12,
+       DBG_BLOCK_ID_SPS00_BY8                           = 0x13,
+       DBG_BLOCK_ID_TA00_BY8                            = 0x14,
+       DBG_BLOCK_ID_TA08_BY8                            = 0x15,
+       DBG_BLOCK_ID_TA10_BY8                            = 0x16,
+       DBG_BLOCK_ID_TA18_BY8                            = 0x17,
+       DBG_BLOCK_ID_TD00_BY8                            = 0x18,
+       DBG_BLOCK_ID_TD08_BY8                            = 0x19,
+       DBG_BLOCK_ID_TD10_BY8                            = 0x1a,
+       DBG_BLOCK_ID_TD18_BY8                            = 0x1b,
+       DBG_BLOCK_ID_MCD0_BY8                            = 0x1c,
+} DebugBlockId_BY8;
+typedef enum DebugBlockId_BY16 {
+       DBG_BLOCK_ID_RESERVED_BY16                       = 0x0,
+       DBG_BLOCK_ID_DMA0_BY16                           = 0x1,
+       DBG_BLOCK_ID_VGT0_BY16                           = 0x2,
+       DBG_BLOCK_ID_SX0_BY16                            = 0x3,
+       DBG_BLOCK_ID_SCB0_BY16                           = 0x4,
+       DBG_BLOCK_ID_CB00_BY16                           = 0x5,
+       DBG_BLOCK_ID_TCP0_BY16                           = 0x6,
+       DBG_BLOCK_ID_TCP16_BY16                          = 0x7,
+       DBG_BLOCK_ID_DB00_BY16                           = 0x8,
+       DBG_BLOCK_ID_TCC0_BY16                           = 0x9,
+       DBG_BLOCK_ID_TA00_BY16                           = 0xa,
+       DBG_BLOCK_ID_TA10_BY16                           = 0xb,
+       DBG_BLOCK_ID_TD00_BY16                           = 0xc,
+       DBG_BLOCK_ID_TD10_BY16                           = 0xd,
+       DBG_BLOCK_ID_MCD0_BY16                           = 0xe,
+} DebugBlockId_BY16;
+typedef enum ColorTransform {
+       DCC_CT_AUTO                                      = 0x0,
+       DCC_CT_NONE                                      = 0x1,
+       ABGR_TO_A_BG_G_RB                                = 0x2,
+       BGRA_TO_BG_G_RB_A                                = 0x3,
+} ColorTransform;
+typedef enum CompareRef {
+       REF_NEVER                                        = 0x0,
+       REF_LESS                                         = 0x1,
+       REF_EQUAL                                        = 0x2,
+       REF_LEQUAL                                       = 0x3,
+       REF_GREATER                                      = 0x4,
+       REF_NOTEQUAL                                     = 0x5,
+       REF_GEQUAL                                       = 0x6,
+       REF_ALWAYS                                       = 0x7,
+} CompareRef;
+typedef enum ReadSize {
+       READ_256_BITS                                    = 0x0,
+       READ_512_BITS                                    = 0x1,
+} ReadSize;
+typedef enum DepthFormat {
+       DEPTH_INVALID                                    = 0x0,
+       DEPTH_16                                         = 0x1,
+       DEPTH_X8_24                                      = 0x2,
+       DEPTH_8_24                                       = 0x3,
+       DEPTH_X8_24_FLOAT                                = 0x4,
+       DEPTH_8_24_FLOAT                                 = 0x5,
+       DEPTH_32_FLOAT                                   = 0x6,
+       DEPTH_X24_8_32_FLOAT                             = 0x7,
+} DepthFormat;
+typedef enum ZFormat {
+       Z_INVALID                                        = 0x0,
+       Z_16                                             = 0x1,
+       Z_24                                             = 0x2,
+       Z_32_FLOAT                                       = 0x3,
+} ZFormat;
+typedef enum StencilFormat {
+       STENCIL_INVALID                                  = 0x0,
+       STENCIL_8                                        = 0x1,
+} StencilFormat;
+typedef enum CmaskMode {
+       CMASK_CLEAR_NONE                                 = 0x0,
+       CMASK_CLEAR_ONE                                  = 0x1,
+       CMASK_CLEAR_ALL                                  = 0x2,
+       CMASK_ANY_EXPANDED                               = 0x3,
+       CMASK_ALPHA0_FRAG1                               = 0x4,
+       CMASK_ALPHA0_FRAG2                               = 0x5,
+       CMASK_ALPHA0_FRAG4                               = 0x6,
+       CMASK_ALPHA0_FRAGS                               = 0x7,
+       CMASK_ALPHA1_FRAG1                               = 0x8,
+       CMASK_ALPHA1_FRAG2                               = 0x9,
+       CMASK_ALPHA1_FRAG4                               = 0xa,
+       CMASK_ALPHA1_FRAGS                               = 0xb,
+       CMASK_ALPHAX_FRAG1                               = 0xc,
+       CMASK_ALPHAX_FRAG2                               = 0xd,
+       CMASK_ALPHAX_FRAG4                               = 0xe,
+       CMASK_ALPHAX_FRAGS                               = 0xf,
+} CmaskMode;
+typedef enum QuadExportFormat {
+       EXPORT_UNUSED                                    = 0x0,
+       EXPORT_32_R                                      = 0x1,
+       EXPORT_32_GR                                     = 0x2,
+       EXPORT_32_AR                                     = 0x3,
+       EXPORT_FP16_ABGR                                 = 0x4,
+       EXPORT_UNSIGNED16_ABGR                           = 0x5,
+       EXPORT_SIGNED16_ABGR                             = 0x6,
+       EXPORT_32_ABGR                                   = 0x7,
+} QuadExportFormat;
+typedef enum QuadExportFormatOld {
+       EXPORT_4P_32BPC_ABGR                             = 0x0,
+       EXPORT_4P_16BPC_ABGR                             = 0x1,
+       EXPORT_4P_32BPC_GR                               = 0x2,
+       EXPORT_4P_32BPC_AR                               = 0x3,
+       EXPORT_2P_32BPC_ABGR                             = 0x4,
+       EXPORT_8P_32BPC_R                                = 0x5,
+} QuadExportFormatOld;
+typedef enum ColorFormat {
+       COLOR_INVALID                                    = 0x0,
+       COLOR_8                                          = 0x1,
+       COLOR_16                                         = 0x2,
+       COLOR_8_8                                        = 0x3,
+       COLOR_32                                         = 0x4,
+       COLOR_16_16                                      = 0x5,
+       COLOR_10_11_11                                   = 0x6,
+       COLOR_11_11_10                                   = 0x7,
+       COLOR_10_10_10_2                                 = 0x8,
+       COLOR_2_10_10_10                                 = 0x9,
+       COLOR_8_8_8_8                                    = 0xa,
+       COLOR_32_32                                      = 0xb,
+       COLOR_16_16_16_16                                = 0xc,
+       COLOR_RESERVED_13                                = 0xd,
+       COLOR_32_32_32_32                                = 0xe,
+       COLOR_RESERVED_15                                = 0xf,
+       COLOR_5_6_5                                      = 0x10,
+       COLOR_1_5_5_5                                    = 0x11,
+       COLOR_5_5_5_1                                    = 0x12,
+       COLOR_4_4_4_4                                    = 0x13,
+       COLOR_8_24                                       = 0x14,
+       COLOR_24_8                                       = 0x15,
+       COLOR_X24_8_32_FLOAT                             = 0x16,
+       COLOR_RESERVED_23                                = 0x17,
+} ColorFormat;
+typedef enum SurfaceFormat {
+       FMT_INVALID                                      = 0x0,
+       FMT_8                                            = 0x1,
+       FMT_16                                           = 0x2,
+       FMT_8_8                                          = 0x3,
+       FMT_32                                           = 0x4,
+       FMT_16_16                                        = 0x5,
+       FMT_10_11_11                                     = 0x6,
+       FMT_11_11_10                                     = 0x7,
+       FMT_10_10_10_2                                   = 0x8,
+       FMT_2_10_10_10                                   = 0x9,
+       FMT_8_8_8_8                                      = 0xa,
+       FMT_32_32                                        = 0xb,
+       FMT_16_16_16_16                                  = 0xc,
+       FMT_32_32_32                                     = 0xd,
+       FMT_32_32_32_32                                  = 0xe,
+       FMT_RESERVED_4                                   = 0xf,
+       FMT_5_6_5                                        = 0x10,
+       FMT_1_5_5_5                                      = 0x11,
+       FMT_5_5_5_1                                      = 0x12,
+       FMT_4_4_4_4                                      = 0x13,
+       FMT_8_24                                         = 0x14,
+       FMT_24_8                                         = 0x15,
+       FMT_X24_8_32_FLOAT                               = 0x16,
+       FMT_RESERVED_33                                  = 0x17,
+       FMT_11_11_10_FLOAT                               = 0x18,
+       FMT_16_FLOAT                                     = 0x19,
+       FMT_32_FLOAT                                     = 0x1a,
+       FMT_16_16_FLOAT                                  = 0x1b,
+       FMT_8_24_FLOAT                                   = 0x1c,
+       FMT_24_8_FLOAT                                   = 0x1d,
+       FMT_32_32_FLOAT                                  = 0x1e,
+       FMT_10_11_11_FLOAT                               = 0x1f,
+       FMT_16_16_16_16_FLOAT                            = 0x20,
+       FMT_3_3_2                                        = 0x21,
+       FMT_6_5_5                                        = 0x22,
+       FMT_32_32_32_32_FLOAT                            = 0x23,
+       FMT_RESERVED_36                                  = 0x24,
+       FMT_1                                            = 0x25,
+       FMT_1_REVERSED                                   = 0x26,
+       FMT_GB_GR                                        = 0x27,
+       FMT_BG_RG                                        = 0x28,
+       FMT_32_AS_8                                      = 0x29,
+       FMT_32_AS_8_8                                    = 0x2a,
+       FMT_5_9_9_9_SHAREDEXP                            = 0x2b,
+       FMT_8_8_8                                        = 0x2c,
+       FMT_16_16_16                                     = 0x2d,
+       FMT_16_16_16_FLOAT                               = 0x2e,
+       FMT_4_4                                          = 0x2f,
+       FMT_32_32_32_FLOAT                               = 0x30,
+       FMT_BC1                                          = 0x31,
+       FMT_BC2                                          = 0x32,
+       FMT_BC3                                          = 0x33,
+       FMT_BC4                                          = 0x34,
+       FMT_BC5                                          = 0x35,
+       FMT_BC6                                          = 0x36,
+       FMT_BC7                                          = 0x37,
+       FMT_32_AS_32_32_32_32                            = 0x38,
+       FMT_APC3                                         = 0x39,
+       FMT_APC4                                         = 0x3a,
+       FMT_APC5                                         = 0x3b,
+       FMT_APC6                                         = 0x3c,
+       FMT_APC7                                         = 0x3d,
+       FMT_CTX1                                         = 0x3e,
+       FMT_RESERVED_63                                  = 0x3f,
+} SurfaceFormat;
+typedef enum BUF_DATA_FORMAT {
+       BUF_DATA_FORMAT_INVALID                          = 0x0,
+       BUF_DATA_FORMAT_8                                = 0x1,
+       BUF_DATA_FORMAT_16                               = 0x2,
+       BUF_DATA_FORMAT_8_8                              = 0x3,
+       BUF_DATA_FORMAT_32                               = 0x4,
+       BUF_DATA_FORMAT_16_16                            = 0x5,
+       BUF_DATA_FORMAT_10_11_11                         = 0x6,
+       BUF_DATA_FORMAT_11_11_10                         = 0x7,
+       BUF_DATA_FORMAT_10_10_10_2                       = 0x8,
+       BUF_DATA_FORMAT_2_10_10_10                       = 0x9,
+       BUF_DATA_FORMAT_8_8_8_8                          = 0xa,
+       BUF_DATA_FORMAT_32_32                            = 0xb,
+       BUF_DATA_FORMAT_16_16_16_16                      = 0xc,
+       BUF_DATA_FORMAT_32_32_32                         = 0xd,
+       BUF_DATA_FORMAT_32_32_32_32                      = 0xe,
+       BUF_DATA_FORMAT_RESERVED_15                      = 0xf,
+} BUF_DATA_FORMAT;
+typedef enum IMG_DATA_FORMAT {
+       IMG_DATA_FORMAT_INVALID                          = 0x0,
+       IMG_DATA_FORMAT_8                                = 0x1,
+       IMG_DATA_FORMAT_16                               = 0x2,
+       IMG_DATA_FORMAT_8_8                              = 0x3,
+       IMG_DATA_FORMAT_32                               = 0x4,
+       IMG_DATA_FORMAT_16_16                            = 0x5,
+       IMG_DATA_FORMAT_10_11_11                         = 0x6,
+       IMG_DATA_FORMAT_11_11_10                         = 0x7,
+       IMG_DATA_FORMAT_10_10_10_2                       = 0x8,
+       IMG_DATA_FORMAT_2_10_10_10                       = 0x9,
+       IMG_DATA_FORMAT_8_8_8_8                          = 0xa,
+       IMG_DATA_FORMAT_32_32                            = 0xb,
+       IMG_DATA_FORMAT_16_16_16_16                      = 0xc,
+       IMG_DATA_FORMAT_32_32_32                         = 0xd,
+       IMG_DATA_FORMAT_32_32_32_32                      = 0xe,
+       IMG_DATA_FORMAT_RESERVED_15                      = 0xf,
+       IMG_DATA_FORMAT_5_6_5                            = 0x10,
+       IMG_DATA_FORMAT_1_5_5_5                          = 0x11,
+       IMG_DATA_FORMAT_5_5_5_1                          = 0x12,
+       IMG_DATA_FORMAT_4_4_4_4                          = 0x13,
+       IMG_DATA_FORMAT_8_24                             = 0x14,
+       IMG_DATA_FORMAT_24_8                             = 0x15,
+       IMG_DATA_FORMAT_X24_8_32                         = 0x16,
+       IMG_DATA_FORMAT_RESERVED_23                      = 0x17,
+       IMG_DATA_FORMAT_RESERVED_24                      = 0x18,
+       IMG_DATA_FORMAT_RESERVED_25                      = 0x19,
+       IMG_DATA_FORMAT_RESERVED_26                      = 0x1a,
+       IMG_DATA_FORMAT_RESERVED_27                      = 0x1b,
+       IMG_DATA_FORMAT_RESERVED_28                      = 0x1c,
+       IMG_DATA_FORMAT_RESERVED_29                      = 0x1d,
+       IMG_DATA_FORMAT_RESERVED_30                      = 0x1e,
+       IMG_DATA_FORMAT_RESERVED_31                      = 0x1f,
+       IMG_DATA_FORMAT_GB_GR                            = 0x20,
+       IMG_DATA_FORMAT_BG_RG                            = 0x21,
+       IMG_DATA_FORMAT_5_9_9_9                          = 0x22,
+       IMG_DATA_FORMAT_BC1                              = 0x23,
+       IMG_DATA_FORMAT_BC2                              = 0x24,
+       IMG_DATA_FORMAT_BC3                              = 0x25,
+       IMG_DATA_FORMAT_BC4                              = 0x26,
+       IMG_DATA_FORMAT_BC5                              = 0x27,
+       IMG_DATA_FORMAT_BC6                              = 0x28,
+       IMG_DATA_FORMAT_BC7                              = 0x29,
+       IMG_DATA_FORMAT_RESERVED_42                      = 0x2a,
+       IMG_DATA_FORMAT_RESERVED_43                      = 0x2b,
+       IMG_DATA_FORMAT_FMASK8_S2_F1                     = 0x2c,
+       IMG_DATA_FORMAT_FMASK8_S4_F1                     = 0x2d,
+       IMG_DATA_FORMAT_FMASK8_S8_F1                     = 0x2e,
+       IMG_DATA_FORMAT_FMASK8_S2_F2                     = 0x2f,
+       IMG_DATA_FORMAT_FMASK8_S4_F2                     = 0x30,
+       IMG_DATA_FORMAT_FMASK8_S4_F4                     = 0x31,
+       IMG_DATA_FORMAT_FMASK16_S16_F1                   = 0x32,
+       IMG_DATA_FORMAT_FMASK16_S8_F2                    = 0x33,
+       IMG_DATA_FORMAT_FMASK32_S16_F2                   = 0x34,
+       IMG_DATA_FORMAT_FMASK32_S8_F4                    = 0x35,
+       IMG_DATA_FORMAT_FMASK32_S8_F8                    = 0x36,
+       IMG_DATA_FORMAT_FMASK64_S16_F4                   = 0x37,
+       IMG_DATA_FORMAT_FMASK64_S16_F8                   = 0x38,
+       IMG_DATA_FORMAT_4_4                              = 0x39,
+       IMG_DATA_FORMAT_6_5_5                            = 0x3a,
+       IMG_DATA_FORMAT_1                                = 0x3b,
+       IMG_DATA_FORMAT_1_REVERSED                       = 0x3c,
+       IMG_DATA_FORMAT_32_AS_8                          = 0x3d,
+       IMG_DATA_FORMAT_32_AS_8_8                        = 0x3e,
+       IMG_DATA_FORMAT_32_AS_32_32_32_32                = 0x3f,
+} IMG_DATA_FORMAT;
+typedef enum BUF_NUM_FORMAT {
+       BUF_NUM_FORMAT_UNORM                             = 0x0,
+       BUF_NUM_FORMAT_SNORM                             = 0x1,
+       BUF_NUM_FORMAT_USCALED                           = 0x2,
+       BUF_NUM_FORMAT_SSCALED                           = 0x3,
+       BUF_NUM_FORMAT_UINT                              = 0x4,
+       BUF_NUM_FORMAT_SINT                              = 0x5,
+       BUF_NUM_FORMAT_RESERVED_6                        = 0x6,
+       BUF_NUM_FORMAT_FLOAT                             = 0x7,
+} BUF_NUM_FORMAT;
+typedef enum IMG_NUM_FORMAT {
+       IMG_NUM_FORMAT_UNORM                             = 0x0,
+       IMG_NUM_FORMAT_SNORM                             = 0x1,
+       IMG_NUM_FORMAT_USCALED                           = 0x2,
+       IMG_NUM_FORMAT_SSCALED                           = 0x3,
+       IMG_NUM_FORMAT_UINT                              = 0x4,
+       IMG_NUM_FORMAT_SINT                              = 0x5,
+       IMG_NUM_FORMAT_RESERVED_6                        = 0x6,
+       IMG_NUM_FORMAT_FLOAT                             = 0x7,
+       IMG_NUM_FORMAT_RESERVED_8                        = 0x8,
+       IMG_NUM_FORMAT_SRGB                              = 0x9,
+       IMG_NUM_FORMAT_RESERVED_10                       = 0xa,
+       IMG_NUM_FORMAT_RESERVED_11                       = 0xb,
+       IMG_NUM_FORMAT_RESERVED_12                       = 0xc,
+       IMG_NUM_FORMAT_RESERVED_13                       = 0xd,
+       IMG_NUM_FORMAT_RESERVED_14                       = 0xe,
+       IMG_NUM_FORMAT_RESERVED_15                       = 0xf,
+} IMG_NUM_FORMAT;
+typedef enum TileType {
+       ARRAY_COLOR_TILE                                 = 0x0,
+       ARRAY_DEPTH_TILE                                 = 0x1,
+} TileType;
+typedef enum NonDispTilingOrder {
+       ADDR_SURF_MICRO_TILING_DISPLAY                   = 0x0,
+       ADDR_SURF_MICRO_TILING_NON_DISPLAY               = 0x1,
+} NonDispTilingOrder;
+typedef enum MicroTileMode {
+       ADDR_SURF_DISPLAY_MICRO_TILING                   = 0x0,
+       ADDR_SURF_THIN_MICRO_TILING                      = 0x1,
+       ADDR_SURF_DEPTH_MICRO_TILING                     = 0x2,
+       ADDR_SURF_ROTATED_MICRO_TILING                   = 0x3,
+       ADDR_SURF_THICK_MICRO_TILING                     = 0x4,
+} MicroTileMode;
+typedef enum TileSplit {
+       ADDR_SURF_TILE_SPLIT_64B                         = 0x0,
+       ADDR_SURF_TILE_SPLIT_128B                        = 0x1,
+       ADDR_SURF_TILE_SPLIT_256B                        = 0x2,
+       ADDR_SURF_TILE_SPLIT_512B                        = 0x3,
+       ADDR_SURF_TILE_SPLIT_1KB                         = 0x4,
+       ADDR_SURF_TILE_SPLIT_2KB                         = 0x5,
+       ADDR_SURF_TILE_SPLIT_4KB                         = 0x6,
+} TileSplit;
+typedef enum SampleSplit {
+       ADDR_SURF_SAMPLE_SPLIT_1                         = 0x0,
+       ADDR_SURF_SAMPLE_SPLIT_2                         = 0x1,
+       ADDR_SURF_SAMPLE_SPLIT_4                         = 0x2,
+       ADDR_SURF_SAMPLE_SPLIT_8                         = 0x3,
+} SampleSplit;
+typedef enum PipeConfig {
+       ADDR_SURF_P2                                     = 0x0,
+       ADDR_SURF_P2_RESERVED0                           = 0x1,
+       ADDR_SURF_P2_RESERVED1                           = 0x2,
+       ADDR_SURF_P2_RESERVED2                           = 0x3,
+       ADDR_SURF_P4_8x16                                = 0x4,
+       ADDR_SURF_P4_16x16                               = 0x5,
+       ADDR_SURF_P4_16x32                               = 0x6,
+       ADDR_SURF_P4_32x32                               = 0x7,
+       ADDR_SURF_P8_16x16_8x16                          = 0x8,
+       ADDR_SURF_P8_16x32_8x16                          = 0x9,
+       ADDR_SURF_P8_32x32_8x16                          = 0xa,
+       ADDR_SURF_P8_16x32_16x16                         = 0xb,
+       ADDR_SURF_P8_32x32_16x16                         = 0xc,
+       ADDR_SURF_P8_32x32_16x32                         = 0xd,
+       ADDR_SURF_P8_32x64_32x32                         = 0xe,
+       ADDR_SURF_P8_RESERVED0                           = 0xf,
+       ADDR_SURF_P16_32x32_8x16                         = 0x10,
+       ADDR_SURF_P16_32x32_16x16                        = 0x11,
+} PipeConfig;
+typedef enum NumBanks {
+       ADDR_SURF_2_BANK                                 = 0x0,
+       ADDR_SURF_4_BANK                                 = 0x1,
+       ADDR_SURF_8_BANK                                 = 0x2,
+       ADDR_SURF_16_BANK                                = 0x3,
+} NumBanks;
+typedef enum BankWidth {
+       ADDR_SURF_BANK_WIDTH_1                           = 0x0,
+       ADDR_SURF_BANK_WIDTH_2                           = 0x1,
+       ADDR_SURF_BANK_WIDTH_4                           = 0x2,
+       ADDR_SURF_BANK_WIDTH_8                           = 0x3,
+} BankWidth;
+typedef enum BankHeight {
+       ADDR_SURF_BANK_HEIGHT_1                          = 0x0,
+       ADDR_SURF_BANK_HEIGHT_2                          = 0x1,
+       ADDR_SURF_BANK_HEIGHT_4                          = 0x2,
+       ADDR_SURF_BANK_HEIGHT_8                          = 0x3,
+} BankHeight;
+typedef enum BankWidthHeight {
+       ADDR_SURF_BANK_WH_1                              = 0x0,
+       ADDR_SURF_BANK_WH_2                              = 0x1,
+       ADDR_SURF_BANK_WH_4                              = 0x2,
+       ADDR_SURF_BANK_WH_8                              = 0x3,
+} BankWidthHeight;
+typedef enum MacroTileAspect {
+       ADDR_SURF_MACRO_ASPECT_1                         = 0x0,
+       ADDR_SURF_MACRO_ASPECT_2                         = 0x1,
+       ADDR_SURF_MACRO_ASPECT_4                         = 0x2,
+       ADDR_SURF_MACRO_ASPECT_8                         = 0x3,
+} MacroTileAspect;
+typedef enum GATCL1RequestType {
+       GATCL1_TYPE_NORMAL                               = 0x0,
+       GATCL1_TYPE_SHOOTDOWN                            = 0x1,
+       GATCL1_TYPE_BYPASS                               = 0x2,
+} GATCL1RequestType;
+typedef enum TCC_CACHE_POLICIES {
+       TCC_CACHE_POLICY_LRU                             = 0x0,
+       TCC_CACHE_POLICY_STREAM                          = 0x1,
+} TCC_CACHE_POLICIES;
+typedef enum MTYPE {
+       MTYPE_NC_NV                                      = 0x0,
+       MTYPE_NC                                         = 0x1,
+       MTYPE_CC                                         = 0x2,
+       MTYPE_UC                                         = 0x3,
+} MTYPE;
+typedef enum PERFMON_COUNTER_MODE {
+       PERFMON_COUNTER_MODE_ACCUM                       = 0x0,
+       PERFMON_COUNTER_MODE_ACTIVE_CYCLES               = 0x1,
+       PERFMON_COUNTER_MODE_MAX                         = 0x2,
+       PERFMON_COUNTER_MODE_DIRTY                       = 0x3,
+       PERFMON_COUNTER_MODE_SAMPLE                      = 0x4,
+       PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT    = 0x5,
+       PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT     = 0x6,
+       PERFMON_COUNTER_MODE_CYCLES_GE_HI                = 0x7,
+       PERFMON_COUNTER_MODE_CYCLES_EQ_HI                = 0x8,
+       PERFMON_COUNTER_MODE_INACTIVE_CYCLES             = 0x9,
+       PERFMON_COUNTER_MODE_RESERVED                    = 0xf,
+} PERFMON_COUNTER_MODE;
+typedef enum PERFMON_SPM_MODE {
+       PERFMON_SPM_MODE_OFF                             = 0x0,
+       PERFMON_SPM_MODE_16BIT_CLAMP                     = 0x1,
+       PERFMON_SPM_MODE_16BIT_NO_CLAMP                  = 0x2,
+       PERFMON_SPM_MODE_32BIT_CLAMP                     = 0x3,
+       PERFMON_SPM_MODE_32BIT_NO_CLAMP                  = 0x4,
+       PERFMON_SPM_MODE_RESERVED_5                      = 0x5,
+       PERFMON_SPM_MODE_RESERVED_6                      = 0x6,
+       PERFMON_SPM_MODE_RESERVED_7                      = 0x7,
+       PERFMON_SPM_MODE_TEST_MODE_0                     = 0x8,
+       PERFMON_SPM_MODE_TEST_MODE_1                     = 0x9,
+       PERFMON_SPM_MODE_TEST_MODE_2                     = 0xa,
+} PERFMON_SPM_MODE;
+typedef enum SurfaceTiling {
+       ARRAY_LINEAR                                     = 0x0,
+       ARRAY_TILED                                      = 0x1,
+} SurfaceTiling;
+typedef enum SurfaceArray {
+       ARRAY_1D                                         = 0x0,
+       ARRAY_2D                                         = 0x1,
+       ARRAY_3D                                         = 0x2,
+       ARRAY_3D_SLICE                                   = 0x3,
+} SurfaceArray;
+typedef enum ColorArray {
+       ARRAY_2D_ALT_COLOR                               = 0x0,
+       ARRAY_2D_COLOR                                   = 0x1,
+       ARRAY_3D_SLICE_COLOR                             = 0x3,
+} ColorArray;
+typedef enum DepthArray {
+       ARRAY_2D_ALT_DEPTH                               = 0x0,
+       ARRAY_2D_DEPTH                                   = 0x1,
+} DepthArray;
+typedef enum ENUM_NUM_SIMD_PER_CU {
+       NUM_SIMD_PER_CU                                  = 0x4,
+} ENUM_NUM_SIMD_PER_CU;
+
+#endif /* SMU_7_1_1_ENUM_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h
new file mode 100644 (file)
index 0000000..2c997f7
--- /dev/null
@@ -0,0 +1,4864 @@
+/*
+ * SMU_7_1_1 Register documentation
+ *
+ * Copyright (C) 2014  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef SMU_7_1_1_SH_MASK_H
+#define SMU_7_1_1_SH_MASK_H
+
+#define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
+#define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
+#define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
+#define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
+#define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
+#define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
+#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
+#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
+#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
+#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
+#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
+#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER__SHIFT 0xa
+#define CG_DCLK_STATUS__DCLK_STATUS_MASK 0x1
+#define CG_DCLK_STATUS__DCLK_STATUS__SHIFT 0x0
+#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG_MASK 0x2
+#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG__SHIFT 0x1
+#define CG_VCLK_CNTL__VCLK_DIVIDER_MASK 0x7f
+#define CG_VCLK_CNTL__VCLK_DIVIDER__SHIFT 0x0
+#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN_MASK 0x100
+#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN__SHIFT 0x8
+#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG_MASK 0x200
+#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG__SHIFT 0x9
+#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
+#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER__SHIFT 0xa
+#define CG_VCLK_STATUS__VCLK_STATUS_MASK 0x1
+#define CG_VCLK_STATUS__VCLK_STATUS__SHIFT 0x0
+#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG_MASK 0x2
+#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG__SHIFT 0x1
+#define CG_ECLK_CNTL__ECLK_DIVIDER_MASK 0x7f
+#define CG_ECLK_CNTL__ECLK_DIVIDER__SHIFT 0x0
+#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK 0x100
+#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN__SHIFT 0x8
+#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG_MASK 0x200
+#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG__SHIFT 0x9
+#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
+#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER__SHIFT 0xa
+#define CG_ECLK_STATUS__ECLK_STATUS_MASK 0x1
+#define CG_ECLK_STATUS__ECLK_STATUS__SHIFT 0x0
+#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG_MASK 0x2
+#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG__SHIFT 0x1
+#define CG_ACLK_CNTL__ACLK_DIVIDER_MASK 0x7f
+#define CG_ACLK_CNTL__ACLK_DIVIDER__SHIFT 0x0
+#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN_MASK 0x100
+#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN__SHIFT 0x8
+#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG_MASK 0x200
+#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG__SHIFT 0x9
+#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
+#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER__SHIFT 0xa
+#define GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK 0x1
+#define GCK_DFS_BYPASS_CNTL__BYPASSECLK__SHIFT 0x0
+#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK_MASK 0x2
+#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK__SHIFT 0x1
+#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK_MASK 0x4
+#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK__SHIFT 0x2
+#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK 0x8
+#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK__SHIFT 0x3
+#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK 0x10
+#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK__SHIFT 0x4
+#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK_MASK 0x20
+#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK__SHIFT 0x5
+#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK_MASK 0x40
+#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK__SHIFT 0x6
+#define GCK_DFS_BYPASS_CNTL__BYPASSACLK_MASK 0x80
+#define GCK_DFS_BYPASS_CNTL__BYPASSACLK__SHIFT 0x7
+#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK_MASK 0x100
+#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK__SHIFT 0x8
+#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK_MASK 0x200
+#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK__SHIFT 0x9
+#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK_MASK 0x400
+#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK__SHIFT 0xa
+#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK_MASK 0x800
+#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK__SHIFT 0xb
+#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN_MASK 0x1000
+#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN__SHIFT 0xc
+#define CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK 0x1
+#define CG_SPLL_FUNC_CNTL__SPLL_RESET__SHIFT 0x0
+#define CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK 0x2
+#define CG_SPLL_FUNC_CNTL__SPLL_PWRON__SHIFT 0x1
+#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN_MASK 0x4
+#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN__SHIFT 0x2
+#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK 0x8
+#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT 0x3
+#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS_MASK 0x10
+#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS__SHIFT 0x4
+#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV_MASK 0x7e0
+#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT 0x5
+#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE_MASK 0x800
+#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE__SHIFT 0xb
+#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN_MASK 0x1000
+#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN__SHIFT 0xc
+#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_MASK 0x7f00000
+#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A__SHIFT 0x14
+#define CG_SPLL_FUNC_CNTL__SPLL_DIVA_ACK_MASK 0x8000000
+#define CG_SPLL_FUNC_CNTL__SPLL_DIVA_ACK__SHIFT 0x1b
+#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN_MASK 0x10000000
+#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN__SHIFT 0x1c
+#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK 0x1ff
+#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT 0x0
+#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_MASK 0x800
+#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ__SHIFT 0xb
+#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG_MASK 0x400000
+#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG__SHIFT 0x16
+#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK 0x800000
+#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT 0x17
+#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG_MASK 0x1000000
+#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG__SHIFT 0x18
+#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG_MASK 0x2000000
+#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG__SHIFT 0x19
+#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE_MASK 0x4000000
+#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE__SHIFT 0x1a
+#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR_MASK 0x8000000
+#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR__SHIFT 0x1b
+#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE_MASK 0x10000000
+#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE__SHIFT 0x1c
+#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR_MASK 0x40000000
+#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR__SHIFT 0x1e
+#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK 0x3ffffff
+#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT 0x0
+#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK 0x10000000
+#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN__SHIFT 0x1c
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL_MASK 0xf
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL__SHIFT 0x0
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL_MASK 0x60
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL__SHIFT 0x5
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN_MASK 0x180
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN__SHIFT 0x7
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK 0x7fe00
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE__SHIFT 0x9
+#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS_MASK 0x200000
+#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS__SHIFT 0x15
+#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK_MASK 0x800000
+#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK__SHIFT 0x17
+#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL_MASK 0x1000000
+#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL__SHIFT 0x18
+#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN_MASK 0x2000000
+#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN__SHIFT 0x19
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_MASK 0xc000000
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT__SHIFT 0x1a
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT_MASK 0x70000000
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT__SHIFT 0x1c
+#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL_MASK 0x80000000
+#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL__SHIFT 0x1f
+#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS_MASK 0x1
+#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS__SHIFT 0x0
+#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN_MASK 0x2
+#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN__SHIFT 0x1
+#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL_MASK 0xc
+#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL__SHIFT 0x2
+#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER_MASK 0x30
+#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER__SHIFT 0x4
+#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL_MASK 0xc0
+#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL__SHIFT 0x6
+#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN_MASK 0x100
+#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN__SHIFT 0x8
+#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX_MASK 0x200
+#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX__SHIFT 0x9
+#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT_MASK 0xff
+#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT__SHIFT 0x0
+#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT_MASK 0xff00
+#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT__SHIFT 0x8
+#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN_MASK 0x10000
+#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN__SHIFT 0x10
+#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN_MASK 0x1e0000
+#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN__SHIFT 0x11
+#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT_MASK 0x1e00000
+#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT__SHIFT 0x15
+#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR_MASK 0xfe000000
+#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR__SHIFT 0x19
+#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL_MASK 0xfff
+#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL__SHIFT 0x0
+#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x1
+#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL__SHIFT 0x0
+#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV_MASK 0x2
+#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV__SHIFT 0x1
+#define SPLL_CNTL_MODE__SPLL_TEST_MASK 0x4
+#define SPLL_CNTL_MODE__SPLL_TEST__SHIFT 0x2
+#define SPLL_CNTL_MODE__SPLL_FASTEN_MASK 0x8
+#define SPLL_CNTL_MODE__SPLL_FASTEN__SHIFT 0x3
+#define SPLL_CNTL_MODE__SPLL_ENSAT_MASK 0x10
+#define SPLL_CNTL_MODE__SPLL_ENSAT__SHIFT 0x4
+#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV_MASK 0xc00
+#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV__SHIFT 0xa
+#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT_MASK 0xff000
+#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT__SHIFT 0xc
+#define SPLL_CNTL_MODE__SPLL_RESET_EN_MASK 0x10000000
+#define SPLL_CNTL_MODE__SPLL_RESET_EN__SHIFT 0x1c
+#define SPLL_CNTL_MODE__SPLL_VCO_MODE_MASK 0x60000000
+#define SPLL_CNTL_MODE__SPLL_VCO_MODE__SHIFT 0x1d
+#define CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK 0x1
+#define CG_SPLL_SPREAD_SPECTRUM__SSEN__SHIFT 0x0
+#define CG_SPLL_SPREAD_SPECTRUM__CLKS_MASK 0xfff0
+#define CG_SPLL_SPREAD_SPECTRUM__CLKS__SHIFT 0x4
+#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV_MASK 0x3ffffff
+#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV__SHIFT 0x0
+#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK 0xff00
+#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT 0x8
+#define CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK 0x2
+#define CG_CLKPIN_CNTL__XTALIN_DIVIDE__SHIFT 0x1
+#define CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK 0x4
+#define CG_CLKPIN_CNTL__BCLK_AS_XCLK__SHIFT 0x2
+#define CG_CLKPIN_CNTL_2__ENABLE_XCLK_MASK 0x1
+#define CG_CLKPIN_CNTL_2__ENABLE_XCLK__SHIFT 0x0
+#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK 0x8
+#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN__SHIFT 0x3
+#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK_MASK 0x100
+#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK__SHIFT 0x8
+#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN_MASK 0x4000
+#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN__SHIFT 0xe
+#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE_MASK 0x8000
+#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE__SHIFT 0xf
+#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN_MASK 0x10000
+#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN__SHIFT 0x10
+#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE_MASK 0x20000
+#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE__SHIFT 0x11
+#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN_MASK 0x40000
+#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN__SHIFT 0x12
+#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE_MASK 0x80000
+#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE__SHIFT 0x13
+#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN_MASK 0x100000
+#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN__SHIFT 0x14
+#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE_MASK 0x200000
+#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE__SHIFT 0x15
+#define CG_CLKPIN_CNTL_2__CML_CTRL_MASK 0xc00000
+#define CG_CLKPIN_CNTL_2__CML_CTRL__SHIFT 0x16
+#define CG_CLKPIN_CNTL_2__CLK_SPARE_MASK 0xff000000
+#define CG_CLKPIN_CNTL_2__CLK_SPARE__SHIFT 0x18
+#define CG_CLKPIN_CNTL_DC__OSC_EN_MASK 0x1
+#define CG_CLKPIN_CNTL_DC__OSC_EN__SHIFT 0x0
+#define CG_CLKPIN_CNTL_DC__XTL_LOW_GAIN_MASK 0x6
+#define CG_CLKPIN_CNTL_DC__XTL_LOW_GAIN__SHIFT 0x1
+#define CG_CLKPIN_CNTL_DC__XTL_XOCLK_DRV_R_EN_MASK 0x200
+#define CG_CLKPIN_CNTL_DC__XTL_XOCLK_DRV_R_EN__SHIFT 0x9
+#define CG_CLKPIN_CNTL_DC__XTALIN_SEL_MASK 0x1c00
+#define CG_CLKPIN_CNTL_DC__XTALIN_SEL__SHIFT 0xa
+#define THM_CLK_CNTL__CMON_CLK_SEL_MASK 0xff
+#define THM_CLK_CNTL__CMON_CLK_SEL__SHIFT 0x0
+#define THM_CLK_CNTL__TMON_CLK_SEL_MASK 0xff00
+#define THM_CLK_CNTL__TMON_CLK_SEL__SHIFT 0x8
+#define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN_MASK 0x10000
+#define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN__SHIFT 0x10
+#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK 0xff
+#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT 0x0
+#define MISC_CLK_CTRL__ZCLK_SEL_MASK 0xff00
+#define MISC_CLK_CTRL__ZCLK_SEL__SHIFT 0x8
+#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL_MASK 0xff0000
+#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL__SHIFT 0x10
+#define GCK_PLL_TEST_CNTL__TST_SRC_SEL_MASK 0x1f
+#define GCK_PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x0
+#define GCK_PLL_TEST_CNTL__TST_REF_SEL_MASK 0x3e0
+#define GCK_PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x5
+#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x1fc00
+#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0xa
+#define GCK_PLL_TEST_CNTL__TST_RESET_MASK 0x20000
+#define GCK_PLL_TEST_CNTL__TST_RESET__SHIFT 0x11
+#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE_MASK 0x40000
+#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE__SHIFT 0x12
+#define GCK_PLL_TEST_CNTL_2__TEST_COUNT_MASK 0xfffe0000
+#define GCK_PLL_TEST_CNTL_2__TEST_COUNT__SHIFT 0x11
+#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL_MASK 0x7
+#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL__SHIFT 0x0
+#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL_MASK 0x38
+#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL__SHIFT 0x3
+#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL_MASK 0x1c0
+#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL__SHIFT 0x6
+#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL_MASK 0xe00
+#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL__SHIFT 0x9
+#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL_MASK 0x7000
+#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL__SHIFT 0xc
+#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL_MASK 0x38000
+#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL__SHIFT 0xf
+#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL_MASK 0x1c0000
+#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL__SHIFT 0x12
+#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL_MASK 0xe00000
+#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL__SHIFT 0x15
+#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL_MASK 0x7000000
+#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL__SHIFT 0x18
+#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL_MASK 0x38000000
+#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL__SHIFT 0x1b
+#define SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
+#define SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
+#define SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
+#define SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
+#define SMC_IND_INDEX_0__SMC_IND_ADDR_MASK 0xffffffff
+#define SMC_IND_INDEX_0__SMC_IND_ADDR__SHIFT 0x0
+#define SMC_IND_DATA_0__SMC_IND_DATA_MASK 0xffffffff
+#define SMC_IND_DATA_0__SMC_IND_DATA__SHIFT 0x0
+#define SMC_IND_INDEX_1__SMC_IND_ADDR_MASK 0xffffffff
+#define SMC_IND_INDEX_1__SMC_IND_ADDR__SHIFT 0x0
+#define SMC_IND_DATA_1__SMC_IND_DATA_MASK 0xffffffff
+#define SMC_IND_DATA_1__SMC_IND_DATA__SHIFT 0x0
+#define SMC_IND_INDEX_2__SMC_IND_ADDR_MASK 0xffffffff
+#define SMC_IND_INDEX_2__SMC_IND_ADDR__SHIFT 0x0
+#define SMC_IND_DATA_2__SMC_IND_DATA_MASK 0xffffffff
+#define SMC_IND_DATA_2__SMC_IND_DATA__SHIFT 0x0
+#define SMC_IND_INDEX_3__SMC_IND_ADDR_MASK 0xffffffff
+#define SMC_IND_INDEX_3__SMC_IND_ADDR__SHIFT 0x0
+#define SMC_IND_DATA_3__SMC_IND_DATA_MASK 0xffffffff
+#define SMC_IND_DATA_3__SMC_IND_DATA__SHIFT 0x0
+#define SMC_IND_INDEX_4__SMC_IND_ADDR_MASK 0xffffffff
+#define SMC_IND_INDEX_4__SMC_IND_ADDR__SHIFT 0x0
+#define SMC_IND_DATA_4__SMC_IND_DATA_MASK 0xffffffff
+#define SMC_IND_DATA_4__SMC_IND_DATA__SHIFT 0x0
+#define SMC_IND_INDEX_5__SMC_IND_ADDR_MASK 0xffffffff
+#define SMC_IND_INDEX_5__SMC_IND_ADDR__SHIFT 0x0
+#define SMC_IND_DATA_5__SMC_IND_DATA_MASK 0xffffffff
+#define SMC_IND_DATA_5__SMC_IND_DATA__SHIFT 0x0
+#define SMC_IND_INDEX_6__SMC_IND_ADDR_MASK 0xffffffff
+#define SMC_IND_INDEX_6__SMC_IND_ADDR__SHIFT 0x0
+#define SMC_IND_DATA_6__SMC_IND_DATA_MASK 0xffffffff
+#define SMC_IND_DATA_6__SMC_IND_DATA__SHIFT 0x0
+#define SMC_IND_INDEX_7__SMC_IND_ADDR_MASK 0xffffffff
+#define SMC_IND_INDEX_7__SMC_IND_ADDR__SHIFT 0x0
+#define SMC_IND_DATA_7__SMC_IND_DATA_MASK 0xffffffff
+#define SMC_IND_DATA_7__SMC_IND_DATA__SHIFT 0x0
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK 0x1
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0__SHIFT 0x0
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1_MASK 0x2
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1__SHIFT 0x1
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2_MASK 0x4
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2__SHIFT 0x2
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3_MASK 0x8
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT 0x3
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4_MASK 0x10
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4__SHIFT 0x4
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5_MASK 0x20
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5__SHIFT 0x5
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6_MASK 0x40
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6__SHIFT 0x6
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7_MASK 0x80
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7__SHIFT 0x7
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_8_MASK 0x100
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_8__SHIFT 0x8
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_9_MASK 0x200
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_9__SHIFT 0x9
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_10_MASK 0x400
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_10__SHIFT 0xa
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_11_MASK 0x800
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_11__SHIFT 0xb
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_12_MASK 0x1000
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_12__SHIFT 0xc
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_13_MASK 0x2000
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_13__SHIFT 0xd
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_14_MASK 0x4000
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_14__SHIFT 0xe
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_15_MASK 0x8000
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_15__SHIFT 0xf
+#define SMC_MESSAGE_0__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_0__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_0__SMC_RESP_MASK 0xffff
+#define SMC_RESP_0__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_1__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_1__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_1__SMC_RESP_MASK 0xffff
+#define SMC_RESP_1__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_2__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_2__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_2__SMC_RESP_MASK 0xffff
+#define SMC_RESP_2__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_3__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_3__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_3__SMC_RESP_MASK 0xffff
+#define SMC_RESP_3__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_4__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_4__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_4__SMC_RESP_MASK 0xffff
+#define SMC_RESP_4__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_5__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_5__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_5__SMC_RESP_MASK 0xffff
+#define SMC_RESP_5__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_6__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_6__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_6__SMC_RESP_MASK 0xffff
+#define SMC_RESP_6__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_7__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_7__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_7__SMC_RESP_MASK 0xffff
+#define SMC_RESP_7__SMC_RESP__SHIFT 0x0
+#define SMC_MSG_ARG_0__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_0__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_1__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_1__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_2__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_2__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_3__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_3__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_4__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_4__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_5__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_5__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_6__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_6__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_7__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_7__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MESSAGE_8__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_8__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_8__SMC_RESP_MASK 0xffff
+#define SMC_RESP_8__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_9__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_9__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_9__SMC_RESP_MASK 0xffff
+#define SMC_RESP_9__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_10__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_10__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_10__SMC_RESP_MASK 0xffff
+#define SMC_RESP_10__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_11__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_11__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_11__SMC_RESP_MASK 0xffff
+#define SMC_RESP_11__SMC_RESP__SHIFT 0x0
+#define SMC_MSG_ARG_8__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_8__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_9__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_9__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_10__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_10__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_11__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_11__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_SYSCON_RESET_CNTL__rst_reg_MASK 0x1
+#define SMC_SYSCON_RESET_CNTL__rst_reg__SHIFT 0x0
+#define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override_MASK 0x2
+#define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override__SHIFT 0x1
+#define SMC_SYSCON_RESET_CNTL__RegReset_MASK 0x40000000
+#define SMC_SYSCON_RESET_CNTL__RegReset__SHIFT 0x1e
+#define SMC_SYSCON_CLOCK_CNTL_0__ck_disable_MASK 0x1
+#define SMC_SYSCON_CLOCK_CNTL_0__ck_disable__SHIFT 0x0
+#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en_MASK 0x2
+#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en__SHIFT 0x1
+#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout_MASK 0xffff00
+#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout__SHIFT 0x8
+#define SMC_SYSCON_CLOCK_CNTL_0__cken_MASK 0x1000000
+#define SMC_SYSCON_CLOCK_CNTL_0__cken__SHIFT 0x18
+#define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable_MASK 0x1
+#define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable__SHIFT 0x0
+#define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq_MASK 0xffffffff
+#define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq__SHIFT 0x0
+#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg_MASK 0xffffffff
+#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg__SHIFT 0x0
+#define SMC_PC_C__smc_pc_c_MASK 0xffffffff
+#define SMC_PC_C__smc_pc_c__SHIFT 0x0
+#define SMC_SCRATCH9__SCRATCH_VALUE_MASK 0xffffffff
+#define SMC_SCRATCH9__SCRATCH_VALUE__SHIFT 0x0
+#define GPIOPAD_SW_INT_STAT__SW_INT_STAT_MASK 0x1
+#define GPIOPAD_SW_INT_STAT__SW_INT_STAT__SHIFT 0x0
+#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN_MASK 0xf
+#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN__SHIFT 0x0
+#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP_MASK 0xf0
+#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP__SHIFT 0x4
+#define GPIOPAD_MASK__GPIO_MASK_MASK 0x7fffffff
+#define GPIOPAD_MASK__GPIO_MASK__SHIFT 0x0
+#define GPIOPAD_A__GPIO_A_MASK 0x7fffffff
+#define GPIOPAD_A__GPIO_A__SHIFT 0x0
+#define GPIOPAD_EN__GPIO_EN_MASK 0x7fffffff
+#define GPIOPAD_EN__GPIO_EN__SHIFT 0x0
+#define GPIOPAD_Y__GPIO_Y_MASK 0x7fffffff
+#define GPIOPAD_Y__GPIO_Y__SHIFT 0x0
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0_MASK 0x1
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0__SHIFT 0x0
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1_MASK 0x2
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1__SHIFT 0x1
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2_MASK 0x4
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2__SHIFT 0x2
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3_MASK 0x8
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3__SHIFT 0x3
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4_MASK 0x10
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4__SHIFT 0x4
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5_MASK 0x20
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5__SHIFT 0x5
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6_MASK 0x40
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6__SHIFT 0x6
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7_MASK 0x80
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7__SHIFT 0x7
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK 0x100
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8__SHIFT 0x8
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9_MASK 0x200
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9__SHIFT 0x9
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10_MASK 0x400
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10__SHIFT 0xa
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11_MASK 0x800
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11__SHIFT 0xb
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12_MASK 0x1000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12__SHIFT 0xc
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13_MASK 0x2000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13__SHIFT 0xd
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14_MASK 0x4000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14__SHIFT 0xe
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15_MASK 0x8000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15__SHIFT 0xf
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16_MASK 0x10000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16__SHIFT 0x10
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17_MASK 0x20000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17__SHIFT 0x11
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18_MASK 0x40000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18__SHIFT 0x12
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19_MASK 0x80000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19__SHIFT 0x13
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20_MASK 0x100000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20__SHIFT 0x14
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21_MASK 0x200000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21__SHIFT 0x15
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22_MASK 0x400000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22__SHIFT 0x16
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23_MASK 0x800000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23__SHIFT 0x17
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24_MASK 0x1000000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24__SHIFT 0x18
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25_MASK 0x2000000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25__SHIFT 0x19
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26_MASK 0x4000000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26__SHIFT 0x1a
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27_MASK 0x8000000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27__SHIFT 0x1b
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28_MASK 0x10000000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28__SHIFT 0x1c
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29_MASK 0x20000000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29__SHIFT 0x1d
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30_MASK 0x40000000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30__SHIFT 0x1e
+#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN_MASK 0x1fffffff
+#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN__SHIFT 0x0
+#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN_MASK 0x80000000
+#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN__SHIFT 0x1f
+#define GPIOPAD_INT_STAT__GPIO_INT_STAT_MASK 0x1fffffff
+#define GPIOPAD_INT_STAT__GPIO_INT_STAT__SHIFT 0x0
+#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT_MASK 0x80000000
+#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT__SHIFT 0x1f
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0_MASK 0x1
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0__SHIFT 0x0
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1_MASK 0x2
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1__SHIFT 0x1
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2_MASK 0x4
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2__SHIFT 0x2
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3_MASK 0x8
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3__SHIFT 0x3
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4_MASK 0x10
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4__SHIFT 0x4
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5_MASK 0x20
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5__SHIFT 0x5
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6_MASK 0x40
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6__SHIFT 0x6
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7_MASK 0x80
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7__SHIFT 0x7
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK 0x100
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8__SHIFT 0x8
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9_MASK 0x200
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9__SHIFT 0x9
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10_MASK 0x400
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10__SHIFT 0xa
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11_MASK 0x800
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11__SHIFT 0xb
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12_MASK 0x1000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12__SHIFT 0xc
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13_MASK 0x2000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13__SHIFT 0xd
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14_MASK 0x4000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14__SHIFT 0xe
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15_MASK 0x8000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15__SHIFT 0xf
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16_MASK 0x10000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16__SHIFT 0x10
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17_MASK 0x20000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17__SHIFT 0x11
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18_MASK 0x40000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18__SHIFT 0x12
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19_MASK 0x80000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19__SHIFT 0x13
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20_MASK 0x100000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20__SHIFT 0x14
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21_MASK 0x200000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21__SHIFT 0x15
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22_MASK 0x400000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22__SHIFT 0x16
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23_MASK 0x800000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23__SHIFT 0x17
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24_MASK 0x1000000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24__SHIFT 0x18
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25_MASK 0x2000000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25__SHIFT 0x19
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26_MASK 0x4000000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26__SHIFT 0x1a
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27_MASK 0x8000000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27__SHIFT 0x1b
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28_MASK 0x10000000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28__SHIFT 0x1c
+#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK_MASK 0x80000000
+#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK__SHIFT 0x1f
+#define GPIOPAD_INT_EN__GPIO_INT_EN_MASK 0x1fffffff
+#define GPIOPAD_INT_EN__GPIO_INT_EN__SHIFT 0x0
+#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN_MASK 0x80000000
+#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN__SHIFT 0x1f
+#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE_MASK 0x1fffffff
+#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE__SHIFT 0x0
+#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE_MASK 0x80000000
+#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE__SHIFT 0x1f
+#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY_MASK 0x1fffffff
+#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY__SHIFT 0x0
+#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY_MASK 0x80000000
+#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY__SHIFT 0x1f
+#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL_MASK 0x1f
+#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL__SHIFT 0x0
+#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR_MASK 0x20
+#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR__SHIFT 0x5
+#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ_MASK 0x40
+#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ__SHIFT 0x6
+#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL_MASK 0x7fffffff
+#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL__SHIFT 0x0
+#define GPIOPAD_PU_EN__GPIO_PU_EN_MASK 0x7fffffff
+#define GPIOPAD_PU_EN__GPIO_PU_EN__SHIFT 0x0
+#define GPIOPAD_PD_EN__GPIO_PD_EN_MASK 0x7fffffff
+#define GPIOPAD_PD_EN__GPIO_PD_EN__SHIFT 0x0
+#define CG_FPS_CNT__FPS_CNT_MASK 0xffffffff
+#define CG_FPS_CNT__FPS_CNT__SHIFT 0x0
+#define SMU_IND_INDEX_0__SMC_IND_ADDR_MASK 0xffffffff
+#define SMU_IND_INDEX_0__SMC_IND_ADDR__SHIFT 0x0
+#define SMU_IND_DATA_0__SMC_IND_DATA_MASK 0xffffffff
+#define SMU_IND_DATA_0__SMC_IND_DATA__SHIFT 0x0
+#define SMU_IND_INDEX_1__SMC_IND_ADDR_MASK 0xffffffff
+#define SMU_IND_INDEX_1__SMC_IND_ADDR__SHIFT 0x0
+#define SMU_IND_DATA_1__SMC_IND_DATA_MASK 0xffffffff
+#define SMU_IND_DATA_1__SMC_IND_DATA__SHIFT 0x0
+#define SMU_IND_INDEX_2__SMC_IND_ADDR_MASK 0xffffffff
+#define SMU_IND_INDEX_2__SMC_IND_ADDR__SHIFT 0x0
+#define SMU_IND_DATA_2__SMC_IND_DATA_MASK 0xffffffff
+#define SMU_IND_DATA_2__SMC_IND_DATA__SHIFT 0x0
+#define SMU_IND_INDEX_3__SMC_IND_ADDR_MASK 0xffffffff
+#define SMU_IND_INDEX_3__SMC_IND_ADDR__SHIFT 0x0
+#define SMU_IND_DATA_3__SMC_IND_DATA_MASK 0xffffffff
+#define SMU_IND_DATA_3__SMC_IND_DATA__SHIFT 0x0
+#define SMU_IND_INDEX_4__SMC_IND_ADDR_MASK 0xffffffff
+#define SMU_IND_INDEX_4__SMC_IND_ADDR__SHIFT 0x0
+#define SMU_IND_DATA_4__SMC_IND_DATA_MASK 0xffffffff
+#define SMU_IND_DATA_4__SMC_IND_DATA__SHIFT 0x0
+#define SMU_IND_INDEX_5__SMC_IND_ADDR_MASK 0xffffffff
+#define SMU_IND_INDEX_5__SMC_IND_ADDR__SHIFT 0x0
+#define SMU_IND_DATA_5__SMC_IND_DATA_MASK 0xffffffff
+#define SMU_IND_DATA_5__SMC_IND_DATA__SHIFT 0x0
+#define SMU_IND_INDEX_6__SMC_IND_ADDR_MASK 0xffffffff
+#define SMU_IND_INDEX_6__SMC_IND_ADDR__SHIFT 0x0
+#define SMU_IND_DATA_6__SMC_IND_DATA_MASK 0xffffffff
+#define SMU_IND_DATA_6__SMC_IND_DATA__SHIFT 0x0
+#define SMU_IND_INDEX_7__SMC_IND_ADDR_MASK 0xffffffff
+#define SMU_IND_INDEX_7__SMC_IND_ADDR__SHIFT 0x0
+#define SMU_IND_DATA_7__SMC_IND_DATA_MASK 0xffffffff
+#define SMU_IND_DATA_7__SMC_IND_DATA__SHIFT 0x0
+#define SMU_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
+#define SMU_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
+#define SMU_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
+#define SMU_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
+#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req_MASK 0x1
+#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req__SHIFT 0x0
+#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done_MASK 0x2
+#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done__SHIFT 0x1
+#define RCU_UC_EVENTS__drv_rst_mode_MASK 0x4
+#define RCU_UC_EVENTS__drv_rst_mode__SHIFT 0x2
+#define RCU_UC_EVENTS__SMU_DC_efuse_status_invalid_MASK 0x8
+#define RCU_UC_EVENTS__SMU_DC_efuse_status_invalid__SHIFT 0x3
+#define RCU_UC_EVENTS__TP_Tester_MASK 0x40
+#define RCU_UC_EVENTS__TP_Tester__SHIFT 0x6
+#define RCU_UC_EVENTS__boot_seq_done_MASK 0x80
+#define RCU_UC_EVENTS__boot_seq_done__SHIFT 0x7
+#define RCU_UC_EVENTS__sclk_deep_sleep_exit_MASK 0x100
+#define RCU_UC_EVENTS__sclk_deep_sleep_exit__SHIFT 0x8
+#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE_MASK 0x200
+#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE__SHIFT 0x9
+#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE_MASK 0x400
+#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE__SHIFT 0xa
+#define RCU_UC_EVENTS__FCH_HALT_MASK 0x800
+#define RCU_UC_EVENTS__FCH_HALT__SHIFT 0xb
+#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown_MASK 0x2000
+#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown__SHIFT 0xd
+#define RCU_UC_EVENTS__INTERRUPTS_ENABLED_MASK 0x10000
+#define RCU_UC_EVENTS__INTERRUPTS_ENABLED__SHIFT 0x10
+#define RCU_UC_EVENTS__RCU_DtmCnt0_Done_MASK 0x20000
+#define RCU_UC_EVENTS__RCU_DtmCnt0_Done__SHIFT 0x11
+#define RCU_UC_EVENTS__RCU_DtmCnt1_Done_MASK 0x40000
+#define RCU_UC_EVENTS__RCU_DtmCnt1_Done__SHIFT 0x12
+#define RCU_UC_EVENTS__RCU_DtmCnt2_Done_MASK 0x80000
+#define RCU_UC_EVENTS__RCU_DtmCnt2_Done__SHIFT 0x13
+#define RCU_UC_EVENTS__irq31_sel_MASK 0x3000000
+#define RCU_UC_EVENTS__irq31_sel__SHIFT 0x18
+#define RCU_MISC_CTRL__REG_DRV_RST_MODE_MASK 0x2
+#define RCU_MISC_CTRL__REG_DRV_RST_MODE__SHIFT 0x1
+#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS_MASK 0x8
+#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS__SHIFT 0x3
+#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE_MASK 0x10
+#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE__SHIFT 0x4
+#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE_MASK 0x20
+#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE__SHIFT 0x5
+#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE_MASK 0x100
+#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE__SHIFT 0x8
+#define RCU_MISC_CTRL__BREAK_PT1_DONE_MASK 0x10000
+#define RCU_MISC_CTRL__BREAK_PT1_DONE__SHIFT 0x10
+#define RCU_MISC_CTRL__BREAK_PT2_DONE_MASK 0x20000
+#define RCU_MISC_CTRL__BREAK_PT2_DONE__SHIFT 0x11
+#define RCU_MISC_CTRL__SAMU_START_MASK 0x400000
+#define RCU_MISC_CTRL__SAMU_START__SHIFT 0x16
+#define RCU_MISC_CTRL__RST_PULSE_WIDTH_MASK 0xff800000
+#define RCU_MISC_CTRL__RST_PULSE_WIDTH__SHIFT 0x17
+#define CC_RCU_FUSES__GPU_DIS_MASK 0x2
+#define CC_RCU_FUSES__GPU_DIS__SHIFT 0x1
+#define CC_RCU_FUSES__DEBUG_DISABLE_MASK 0x4
+#define CC_RCU_FUSES__DEBUG_DISABLE__SHIFT 0x2
+#define CC_RCU_FUSES__EFUSE_RD_DISABLE_MASK 0x10
+#define CC_RCU_FUSES__EFUSE_RD_DISABLE__SHIFT 0x4
+#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS_MASK 0x20
+#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS__SHIFT 0x5
+#define CC_RCU_FUSES__DRV_RST_MODE_MASK 0x40
+#define CC_RCU_FUSES__DRV_RST_MODE__SHIFT 0x6
+#define CC_RCU_FUSES__ROM_DIS_MASK 0x80
+#define CC_RCU_FUSES__ROM_DIS__SHIFT 0x7
+#define CC_RCU_FUSES__JPC_REP_DISABLE_MASK 0x100
+#define CC_RCU_FUSES__JPC_REP_DISABLE__SHIFT 0x8
+#define CC_RCU_FUSES__RCU_BREAK_POINT1_MASK 0x200
+#define CC_RCU_FUSES__RCU_BREAK_POINT1__SHIFT 0x9
+#define CC_RCU_FUSES__RCU_BREAK_POINT2_MASK 0x400
+#define CC_RCU_FUSES__RCU_BREAK_POINT2__SHIFT 0xa
+#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE_MASK 0x4000
+#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE__SHIFT 0xe
+#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE_MASK 0x8000
+#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE__SHIFT 0xf
+#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE_MASK 0x10000
+#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE__SHIFT 0x10
+#define CC_RCU_FUSES__XFIRE_DISABLE_MASK 0x20000
+#define CC_RCU_FUSES__XFIRE_DISABLE__SHIFT 0x11
+#define CC_RCU_FUSES__SAMU_FUSE_DISABLE_MASK 0x40000
+#define CC_RCU_FUSES__SAMU_FUSE_DISABLE__SHIFT 0x12
+#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE_MASK 0x80000
+#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE__SHIFT 0x13
+#define CC_RCU_FUSES__MEM_HARDREP_EN_MASK 0x200000
+#define CC_RCU_FUSES__MEM_HARDREP_EN__SHIFT 0x15
+#define CC_RCU_FUSES__PCIE_INIT_DISABLE_MASK 0x400000
+#define CC_RCU_FUSES__PCIE_INIT_DISABLE__SHIFT 0x16
+#define CC_RCU_FUSES__DSMU_DISABLE_MASK 0x800000
+#define CC_RCU_FUSES__DSMU_DISABLE__SHIFT 0x17
+#define CC_RCU_FUSES__WRP_FUSE_VALID_MASK 0x1000000
+#define CC_RCU_FUSES__WRP_FUSE_VALID__SHIFT 0x18
+#define CC_RCU_FUSES__PHY_FUSE_VALID_MASK 0x2000000
+#define CC_RCU_FUSES__PHY_FUSE_VALID__SHIFT 0x19
+#define CC_RCU_FUSES__RCU_SPARE_MASK 0xfc000000
+#define CC_RCU_FUSES__RCU_SPARE__SHIFT 0x1a
+#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE_MASK 0x2
+#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE__SHIFT 0x1
+#define CC_SMU_MISC_FUSES__MinSClkDid_MASK 0x1fc
+#define CC_SMU_MISC_FUSES__MinSClkDid__SHIFT 0x2
+#define CC_SMU_MISC_FUSES__MISC_SPARE_MASK 0x600
+#define CC_SMU_MISC_FUSES__MISC_SPARE__SHIFT 0x9
+#define CC_SMU_MISC_FUSES__PostResetGnbClkDid_MASK 0x3f800
+#define CC_SMU_MISC_FUSES__PostResetGnbClkDid__SHIFT 0xb
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half_MASK 0x40000
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half__SHIFT 0x12
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half_MASK 0x80000
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half__SHIFT 0x13
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half_MASK 0x100000
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half__SHIFT 0x14
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half_MASK 0x200000
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half__SHIFT 0x15
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis_MASK 0x400000
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis__SHIFT 0x16
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis_MASK 0x800000
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis__SHIFT 0x17
+#define CC_SMU_MISC_FUSES__VCE_DISABLE_MASK 0x8000000
+#define CC_SMU_MISC_FUSES__VCE_DISABLE__SHIFT 0x1b
+#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE_MASK 0x10000000
+#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE__SHIFT 0x1c
+#define CC_SMU_MISC_FUSES__GNB_SPARE_MASK 0x60000000
+#define CC_SMU_MISC_FUSES__GNB_SPARE__SHIFT 0x1d
+#define CC_SCLK_VID_FUSES__SClkVid0_MASK 0xff
+#define CC_SCLK_VID_FUSES__SClkVid0__SHIFT 0x0
+#define CC_SCLK_VID_FUSES__SClkVid1_MASK 0xff00
+#define CC_SCLK_VID_FUSES__SClkVid1__SHIFT 0x8
+#define CC_SCLK_VID_FUSES__SClkVid2_MASK 0xff0000
+#define CC_SCLK_VID_FUSES__SClkVid2__SHIFT 0x10
+#define CC_SCLK_VID_FUSES__SClkVid3_MASK 0xff000000
+#define CC_SCLK_VID_FUSES__SClkVid3__SHIFT 0x18
+#define CC_GIO_IOCCFG_FUSES__NB_REV_ID_MASK 0x7fe
+#define CC_GIO_IOCCFG_FUSES__NB_REV_ID__SHIFT 0x1
+#define CC_GIO_IOC_FUSES__IOC_FUSES_MASK 0x3e
+#define CC_GIO_IOC_FUSES__IOC_FUSES__SHIFT 0x1
+#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2_MASK 0x3e
+#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2__SHIFT 0x1
+#define CC_SMU_TST_EFUSE1_MISC__RME_MASK 0x40
+#define CC_SMU_TST_EFUSE1_MISC__RME__SHIFT 0x6
+#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE_MASK 0x80
+#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE__SHIFT 0x7
+#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE_MASK 0x100
+#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE__SHIFT 0x8
+#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE_MASK 0x200
+#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE__SHIFT 0x9
+#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS_MASK 0x400
+#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS__SHIFT 0xa
+#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE_MASK 0x800
+#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE__SHIFT 0xb
+#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA_MASK 0x1000
+#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA__SHIFT 0xc
+#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB_MASK 0x2000
+#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB__SHIFT 0xd
+#define CC_SMU_TST_EFUSE1_MISC__RM_RF8_MASK 0x4000
+#define CC_SMU_TST_EFUSE1_MISC__RM_RF8__SHIFT 0xe
+#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1_MASK 0x400000
+#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1__SHIFT 0x16
+#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2_MASK 0x800000
+#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2__SHIFT 0x17
+#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3_MASK 0x1000000
+#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3__SHIFT 0x18
+#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE_MASK 0x2000000
+#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE__SHIFT 0x19
+#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE_MASK 0x4000000
+#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE__SHIFT 0x1a
+#define CC_TST_ID_STRAPS__DEVICE_ID_MASK 0xffff0
+#define CC_TST_ID_STRAPS__DEVICE_ID__SHIFT 0x4
+#define CC_TST_ID_STRAPS__MAJOR_REV_ID_MASK 0xf00000
+#define CC_TST_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x14
+#define CC_TST_ID_STRAPS__MINOR_REV_ID_MASK 0xf000000
+#define CC_TST_ID_STRAPS__MINOR_REV_ID__SHIFT 0x18
+#define CC_TST_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000
+#define CC_TST_ID_STRAPS__ATI_REV_ID__SHIFT 0x1c
+#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT_MASK 0x2
+#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT__SHIFT 0x1
+#define CC_HARVEST_FUSES__VCE_DISABLE_MASK 0x6
+#define CC_HARVEST_FUSES__VCE_DISABLE__SHIFT 0x1
+#define CC_HARVEST_FUSES__UVD_DISABLE_MASK 0x10
+#define CC_HARVEST_FUSES__UVD_DISABLE__SHIFT 0x4
+#define CC_HARVEST_FUSES__ACP_EXISTS_MASK 0x40
+#define CC_HARVEST_FUSES__ACP_EXISTS__SHIFT 0x6
+#define CC_HARVEST_FUSES__DC_DISABLE_MASK 0x3f00
+#define CC_HARVEST_FUSES__DC_DISABLE__SHIFT 0x8
+#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ_MASK 0xffffffff
+#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ__SHIFT 0x0
+#define SMU_STATUS__SMU_DONE_MASK 0x1
+#define SMU_STATUS__SMU_DONE__SHIFT 0x0
+#define SMU_STATUS__SMU_PASS_MASK 0x2
+#define SMU_STATUS__SMU_PASS__SHIFT 0x1
+#define SMU_FIRMWARE__SMU_IN_PROG_MASK 0x1
+#define SMU_FIRMWARE__SMU_IN_PROG__SHIFT 0x0
+#define SMU_FIRMWARE__SMU_RD_DONE_MASK 0x6
+#define SMU_FIRMWARE__SMU_RD_DONE__SHIFT 0x1
+#define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN_MASK 0x8
+#define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN__SHIFT 0x3
+#define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN_MASK 0x10
+#define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN__SHIFT 0x4
+#define SMU_FIRMWARE__SMU_counter_MASK 0xf00
+#define SMU_FIRMWARE__SMU_counter__SHIFT 0x8
+#define SMU_FIRMWARE__SMU_MODE_MASK 0x10000
+#define SMU_FIRMWARE__SMU_MODE__SHIFT 0x10
+#define SMU_FIRMWARE__SMU_SEL_MASK 0x20000
+#define SMU_FIRMWARE__SMU_SEL__SHIFT 0x11
+#define SMU_INPUT_DATA__START_ADDR_MASK 0x7fffffff
+#define SMU_INPUT_DATA__START_ADDR__SHIFT 0x0
+#define SMU_INPUT_DATA__AUTO_START_MASK 0x80000000
+#define SMU_INPUT_DATA__AUTO_START__SHIFT 0x1f
+#define SMU_EFUSE_0__EFUSE_DATA_MASK 0xffffffff
+#define SMU_EFUSE_0__EFUSE_DATA__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_1__entries_0_0_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_1__entries_0_0_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_2__entries_0_0_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_2__entries_0_0_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_4__entries_0_1_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_4__entries_0_1_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_5__entries_0_1_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_5__entries_0_1_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_7__entries_0_2_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_7__entries_0_2_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_8__entries_0_2_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_8__entries_0_2_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_10__entries_0_3_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_10__entries_0_3_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_11__entries_0_3_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_11__entries_0_3_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_13__entries_1_0_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_13__entries_1_0_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_14__entries_1_0_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_14__entries_1_0_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_16__entries_1_1_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_16__entries_1_1_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_17__entries_1_1_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_17__entries_1_1_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_19__entries_1_2_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_19__entries_1_2_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_20__entries_1_2_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_20__entries_1_2_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_22__entries_1_3_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_22__entries_1_3_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_23__entries_1_3_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_23__entries_1_3_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_25__entries_2_0_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_25__entries_2_0_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_26__entries_2_0_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_26__entries_2_0_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_28__entries_2_1_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_28__entries_2_1_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_29__entries_2_1_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_29__entries_2_1_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_31__entries_2_2_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_31__entries_2_2_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_32__entries_2_2_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_32__entries_2_2_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_34__entries_2_3_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_34__entries_2_3_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_35__entries_2_3_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_35__entries_2_3_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_37__entries_3_0_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_37__entries_3_0_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_38__entries_3_0_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_38__entries_3_0_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_40__entries_3_1_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_40__entries_3_1_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_41__entries_3_1_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_41__entries_3_1_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_43__entries_3_2_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_43__entries_3_2_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_44__entries_3_2_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_44__entries_3_2_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_46__entries_3_3_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_46__entries_3_3_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_47__entries_3_3_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_47__entries_3_3_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_49__entries_4_0_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_49__entries_4_0_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_50__entries_4_0_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_50__entries_4_0_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_52__entries_4_1_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_52__entries_4_1_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_53__entries_4_1_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_53__entries_4_1_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_55__entries_4_2_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_55__entries_4_2_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_56__entries_4_2_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_56__entries_4_2_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_58__entries_4_3_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_58__entries_4_3_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_59__entries_4_3_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_59__entries_4_3_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_61__entries_5_0_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_61__entries_5_0_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_62__entries_5_0_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_62__entries_5_0_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_64__entries_5_1_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_64__entries_5_1_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_65__entries_5_1_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_65__entries_5_1_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_67__entries_5_2_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_67__entries_5_2_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_68__entries_5_2_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_68__entries_5_2_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_70__entries_5_3_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_70__entries_5_3_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_71__entries_5_3_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_71__entries_5_3_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_73__entries_6_0_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_73__entries_6_0_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_74__entries_6_0_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_74__entries_6_0_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_76__entries_6_1_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_76__entries_6_1_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_77__entries_6_1_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_77__entries_6_1_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_79__entries_6_2_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_79__entries_6_2_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_80__entries_6_2_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_80__entries_6_2_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_82__entries_6_3_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_82__entries_6_3_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_83__entries_6_3_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_83__entries_6_3_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_85__entries_7_0_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_85__entries_7_0_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_86__entries_7_0_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_86__entries_7_0_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_88__entries_7_1_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_88__entries_7_1_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_89__entries_7_1_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_89__entries_7_1_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_91__entries_7_2_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_91__entries_7_2_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_92__entries_7_2_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_92__entries_7_2_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_94__entries_7_3_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_94__entries_7_3_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_95__entries_7_3_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_95__entries_7_3_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_McArbBurstTime__SHIFT 0x18
+#define MC_REGISTERS_TABLE_1__reserved_2_MASK 0xff
+#define MC_REGISTERS_TABLE_1__reserved_2__SHIFT 0x0
+#define MC_REGISTERS_TABLE_1__reserved_1_MASK 0xff00
+#define MC_REGISTERS_TABLE_1__reserved_1__SHIFT 0x8
+#define MC_REGISTERS_TABLE_1__reserved_0_MASK 0xff0000
+#define MC_REGISTERS_TABLE_1__reserved_0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_1__last_MASK 0xff000000
+#define MC_REGISTERS_TABLE_1__last__SHIFT 0x18
+#define MC_REGISTERS_TABLE_2__address_0_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_2__address_0_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_2__address_0_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_2__address_0_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_3__address_1_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_3__address_1_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_3__address_1_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_3__address_1_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_4__address_2_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_4__address_2_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_4__address_2_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_4__address_2_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_5__address_3_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_5__address_3_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_5__address_3_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_5__address_3_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_6__address_4_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_6__address_4_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_6__address_4_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_6__address_4_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_7__address_5_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_7__address_5_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_7__address_5_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_7__address_5_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_8__address_6_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_8__address_6_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_8__address_6_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_8__address_6_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_9__address_7_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_9__address_7_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_9__address_7_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_9__address_7_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_10__address_8_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_10__address_8_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_10__address_8_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_10__address_8_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_11__address_9_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_11__address_9_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_11__address_9_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_11__address_9_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_12__address_10_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_12__address_10_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_12__address_10_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_12__address_10_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_13__address_11_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_13__address_11_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_13__address_11_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_13__address_11_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_14__address_12_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_14__address_12_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_14__address_12_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_14__address_12_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_15__address_13_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_15__address_13_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_15__address_13_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_15__address_13_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_16__address_14_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_16__address_14_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_16__address_14_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_16__address_14_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_17__address_15_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_17__address_15_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_17__address_15_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_17__address_15_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_18__data_0_value_0_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_18__data_0_value_0__SHIFT 0x0
+#define MC_REGISTERS_TABLE_19__data_0_value_1_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_19__data_0_value_1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_20__data_0_value_2_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_20__data_0_value_2__SHIFT 0x0
+#define MC_REGISTERS_TABLE_21__data_0_value_3_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_21__data_0_value_3__SHIFT 0x0
+#define MC_REGISTERS_TABLE_22__data_0_value_4_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_22__data_0_value_4__SHIFT 0x0
+#define MC_REGISTERS_TABLE_23__data_0_value_5_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_23__data_0_value_5__SHIFT 0x0
+#define MC_REGISTERS_TABLE_24__data_0_value_6_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_24__data_0_value_6__SHIFT 0x0
+#define MC_REGISTERS_TABLE_25__data_0_value_7_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_25__data_0_value_7__SHIFT 0x0
+#define MC_REGISTERS_TABLE_26__data_0_value_8_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_26__data_0_value_8__SHIFT 0x0
+#define MC_REGISTERS_TABLE_27__data_0_value_9_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_27__data_0_value_9__SHIFT 0x0
+#define MC_REGISTERS_TABLE_28__data_0_value_10_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_28__data_0_value_10__SHIFT 0x0
+#define MC_REGISTERS_TABLE_29__data_0_value_11_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_29__data_0_value_11__SHIFT 0x0
+#define MC_REGISTERS_TABLE_30__data_0_value_12_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_30__data_0_value_12__SHIFT 0x0
+#define MC_REGISTERS_TABLE_31__data_0_value_13_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_31__data_0_value_13__SHIFT 0x0
+#define MC_REGISTERS_TABLE_32__data_0_value_14_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_32__data_0_value_14__SHIFT 0x0
+#define MC_REGISTERS_TABLE_33__data_0_value_15_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_33__data_0_value_15__SHIFT 0x0
+#define MC_REGISTERS_TABLE_34__data_1_value_0_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_34__data_1_value_0__SHIFT 0x0
+#define MC_REGISTERS_TABLE_35__data_1_value_1_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_35__data_1_value_1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_36__data_1_value_2_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_36__data_1_value_2__SHIFT 0x0
+#define MC_REGISTERS_TABLE_37__data_1_value_3_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_37__data_1_value_3__SHIFT 0x0
+#define MC_REGISTERS_TABLE_38__data_1_value_4_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_38__data_1_value_4__SHIFT 0x0
+#define MC_REGISTERS_TABLE_39__data_1_value_5_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_39__data_1_value_5__SHIFT 0x0
+#define MC_REGISTERS_TABLE_40__data_1_value_6_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_40__data_1_value_6__SHIFT 0x0
+#define MC_REGISTERS_TABLE_41__data_1_value_7_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_41__data_1_value_7__SHIFT 0x0
+#define MC_REGISTERS_TABLE_42__data_1_value_8_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_42__data_1_value_8__SHIFT 0x0
+#define MC_REGISTERS_TABLE_43__data_1_value_9_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_43__data_1_value_9__SHIFT 0x0
+#define MC_REGISTERS_TABLE_44__data_1_value_10_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_44__data_1_value_10__SHIFT 0x0
+#define MC_REGISTERS_TABLE_45__data_1_value_11_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_45__data_1_value_11__SHIFT 0x0
+#define MC_REGISTERS_TABLE_46__data_1_value_12_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_46__data_1_value_12__SHIFT 0x0
+#define MC_REGISTERS_TABLE_47__data_1_value_13_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_47__data_1_value_13__SHIFT 0x0
+#define MC_REGISTERS_TABLE_48__data_1_value_14_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_48__data_1_value_14__SHIFT 0x0
+#define MC_REGISTERS_TABLE_49__data_1_value_15_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_49__data_1_value_15__SHIFT 0x0
+#define MC_REGISTERS_TABLE_50__data_2_value_0_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_50__data_2_value_0__SHIFT 0x0
+#define MC_REGISTERS_TABLE_51__data_2_value_1_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_51__data_2_value_1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_52__data_2_value_2_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_52__data_2_value_2__SHIFT 0x0
+#define MC_REGISTERS_TABLE_53__data_2_value_3_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_53__data_2_value_3__SHIFT 0x0
+#define MC_REGISTERS_TABLE_54__data_2_value_4_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_54__data_2_value_4__SHIFT 0x0
+#define MC_REGISTERS_TABLE_55__data_2_value_5_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_55__data_2_value_5__SHIFT 0x0
+#define MC_REGISTERS_TABLE_56__data_2_value_6_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_56__data_2_value_6__SHIFT 0x0
+#define MC_REGISTERS_TABLE_57__data_2_value_7_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_57__data_2_value_7__SHIFT 0x0
+#define MC_REGISTERS_TABLE_58__data_2_value_8_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_58__data_2_value_8__SHIFT 0x0
+#define MC_REGISTERS_TABLE_59__data_2_value_9_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_59__data_2_value_9__SHIFT 0x0
+#define MC_REGISTERS_TABLE_60__data_2_value_10_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_60__data_2_value_10__SHIFT 0x0
+#define MC_REGISTERS_TABLE_61__data_2_value_11_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_61__data_2_value_11__SHIFT 0x0
+#define MC_REGISTERS_TABLE_62__data_2_value_12_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_62__data_2_value_12__SHIFT 0x0
+#define MC_REGISTERS_TABLE_63__data_2_value_13_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_63__data_2_value_13__SHIFT 0x0
+#define MC_REGISTERS_TABLE_64__data_2_value_14_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_64__data_2_value_14__SHIFT 0x0
+#define MC_REGISTERS_TABLE_65__data_2_value_15_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_65__data_2_value_15__SHIFT 0x0
+#define MC_REGISTERS_TABLE_66__data_3_value_0_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_66__data_3_value_0__SHIFT 0x0
+#define MC_REGISTERS_TABLE_67__data_3_value_1_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_67__data_3_value_1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_68__data_3_value_2_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_68__data_3_value_2__SHIFT 0x0
+#define MC_REGISTERS_TABLE_69__data_3_value_3_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_69__data_3_value_3__SHIFT 0x0
+#define MC_REGISTERS_TABLE_70__data_3_value_4_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_70__data_3_value_4__SHIFT 0x0
+#define MC_REGISTERS_TABLE_71__data_3_value_5_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_71__data_3_value_5__SHIFT 0x0
+#define MC_REGISTERS_TABLE_72__data_3_value_6_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_72__data_3_value_6__SHIFT 0x0
+#define MC_REGISTERS_TABLE_73__data_3_value_7_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_73__data_3_value_7__SHIFT 0x0
+#define MC_REGISTERS_TABLE_74__data_3_value_8_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_74__data_3_value_8__SHIFT 0x0
+#define MC_REGISTERS_TABLE_75__data_3_value_9_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_75__data_3_value_9__SHIFT 0x0
+#define MC_REGISTERS_TABLE_76__data_3_value_10_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_76__data_3_value_10__SHIFT 0x0
+#define MC_REGISTERS_TABLE_77__data_3_value_11_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_77__data_3_value_11__SHIFT 0x0
+#define MC_REGISTERS_TABLE_78__data_3_value_12_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_78__data_3_value_12__SHIFT 0x0
+#define MC_REGISTERS_TABLE_79__data_3_value_13_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_79__data_3_value_13__SHIFT 0x0
+#define MC_REGISTERS_TABLE_80__data_3_value_14_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_80__data_3_value_14__SHIFT 0x0
+#define MC_REGISTERS_TABLE_81__data_3_value_15_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_81__data_3_value_15__SHIFT 0x0
+#define DPM_TABLE_1__GraphicsPIDController_Ki_MASK 0xffffffff
+#define DPM_TABLE_1__GraphicsPIDController_Ki__SHIFT 0x0
+#define DPM_TABLE_2__GraphicsPIDController_LFWindupUpperLim_MASK 0xffffffff
+#define DPM_TABLE_2__GraphicsPIDController_LFWindupUpperLim__SHIFT 0x0
+#define DPM_TABLE_3__GraphicsPIDController_LFWindupLowerLim_MASK 0xffffffff
+#define DPM_TABLE_3__GraphicsPIDController_LFWindupLowerLim__SHIFT 0x0
+#define DPM_TABLE_4__GraphicsPIDController_StatePrecision_MASK 0xffffffff
+#define DPM_TABLE_4__GraphicsPIDController_StatePrecision__SHIFT 0x0
+#define DPM_TABLE_5__GraphicsPIDController_LfPrecision_MASK 0xffffffff
+#define DPM_TABLE_5__GraphicsPIDController_LfPrecision__SHIFT 0x0
+#define DPM_TABLE_6__GraphicsPIDController_LfOffset_MASK 0xffffffff
+#define DPM_TABLE_6__GraphicsPIDController_LfOffset__SHIFT 0x0
+#define DPM_TABLE_7__GraphicsPIDController_MaxState_MASK 0xffffffff
+#define DPM_TABLE_7__GraphicsPIDController_MaxState__SHIFT 0x0
+#define DPM_TABLE_8__GraphicsPIDController_MaxLfFraction_MASK 0xffffffff
+#define DPM_TABLE_8__GraphicsPIDController_MaxLfFraction__SHIFT 0x0
+#define DPM_TABLE_9__GraphicsPIDController_StateShift_MASK 0xffffffff
+#define DPM_TABLE_9__GraphicsPIDController_StateShift__SHIFT 0x0
+#define DPM_TABLE_10__MemoryPIDController_Ki_MASK 0xffffffff
+#define DPM_TABLE_10__MemoryPIDController_Ki__SHIFT 0x0
+#define DPM_TABLE_11__MemoryPIDController_LFWindupUpperLim_MASK 0xffffffff
+#define DPM_TABLE_11__MemoryPIDController_LFWindupUpperLim__SHIFT 0x0
+#define DPM_TABLE_12__MemoryPIDController_LFWindupLowerLim_MASK 0xffffffff
+#define DPM_TABLE_12__MemoryPIDController_LFWindupLowerLim__SHIFT 0x0
+#define DPM_TABLE_13__MemoryPIDController_StatePrecision_MASK 0xffffffff
+#define DPM_TABLE_13__MemoryPIDController_StatePrecision__SHIFT 0x0
+#define DPM_TABLE_14__MemoryPIDController_LfPrecision_MASK 0xffffffff
+#define DPM_TABLE_14__MemoryPIDController_LfPrecision__SHIFT 0x0
+#define DPM_TABLE_15__MemoryPIDController_LfOffset_MASK 0xffffffff
+#define DPM_TABLE_15__MemoryPIDController_LfOffset__SHIFT 0x0
+#define DPM_TABLE_16__MemoryPIDController_MaxState_MASK 0xffffffff
+#define DPM_TABLE_16__MemoryPIDController_MaxState__SHIFT 0x0
+#define DPM_TABLE_17__MemoryPIDController_MaxLfFraction_MASK 0xffffffff
+#define DPM_TABLE_17__MemoryPIDController_MaxLfFraction__SHIFT 0x0
+#define DPM_TABLE_18__MemoryPIDController_StateShift_MASK 0xffffffff
+#define DPM_TABLE_18__MemoryPIDController_StateShift__SHIFT 0x0
+#define DPM_TABLE_19__LinkPIDController_Ki_MASK 0xffffffff
+#define DPM_TABLE_19__LinkPIDController_Ki__SHIFT 0x0
+#define DPM_TABLE_20__LinkPIDController_LFWindupUpperLim_MASK 0xffffffff
+#define DPM_TABLE_20__LinkPIDController_LFWindupUpperLim__SHIFT 0x0
+#define DPM_TABLE_21__LinkPIDController_LFWindupLowerLim_MASK 0xffffffff
+#define DPM_TABLE_21__LinkPIDController_LFWindupLowerLim__SHIFT 0x0
+#define DPM_TABLE_22__LinkPIDController_StatePrecision_MASK 0xffffffff
+#define DPM_TABLE_22__LinkPIDController_StatePrecision__SHIFT 0x0
+#define DPM_TABLE_23__LinkPIDController_LfPrecision_MASK 0xffffffff
+#define DPM_TABLE_23__LinkPIDController_LfPrecision__SHIFT 0x0
+#define DPM_TABLE_24__LinkPIDController_LfOffset_MASK 0xffffffff
+#define DPM_TABLE_24__LinkPIDController_LfOffset__SHIFT 0x0
+#define DPM_TABLE_25__LinkPIDController_MaxState_MASK 0xffffffff
+#define DPM_TABLE_25__LinkPIDController_MaxState__SHIFT 0x0
+#define DPM_TABLE_26__LinkPIDController_MaxLfFraction_MASK 0xffffffff
+#define DPM_TABLE_26__LinkPIDController_MaxLfFraction__SHIFT 0x0
+#define DPM_TABLE_27__LinkPIDController_StateShift_MASK 0xffffffff
+#define DPM_TABLE_27__LinkPIDController_StateShift__SHIFT 0x0
+#define DPM_TABLE_28__SystemFlags_MASK 0xffffffff
+#define DPM_TABLE_28__SystemFlags__SHIFT 0x0
+#define DPM_TABLE_29__SmioMaskVddcVid_MASK 0xffffffff
+#define DPM_TABLE_29__SmioMaskVddcVid__SHIFT 0x0
+#define DPM_TABLE_30__SmioMaskVddcPhase_MASK 0xffffffff
+#define DPM_TABLE_30__SmioMaskVddcPhase__SHIFT 0x0
+#define DPM_TABLE_31__SmioMaskVddciVid_MASK 0xffffffff
+#define DPM_TABLE_31__SmioMaskVddciVid__SHIFT 0x0
+#define DPM_TABLE_32__SmioMaskMvddVid_MASK 0xffffffff
+#define DPM_TABLE_32__SmioMaskMvddVid__SHIFT 0x0
+#define DPM_TABLE_33__VddcLevelCount_MASK 0xffffffff
+#define DPM_TABLE_33__VddcLevelCount__SHIFT 0x0
+#define DPM_TABLE_34__VddciLevelCount_MASK 0xffffffff
+#define DPM_TABLE_34__VddciLevelCount__SHIFT 0x0
+#define DPM_TABLE_35__MvddLevelCount_MASK 0xffffffff
+#define DPM_TABLE_35__MvddLevelCount__SHIFT 0x0
+#define DPM_TABLE_36__VddcLevel_0_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_36__VddcLevel_0_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_36__VddcLevel_0_Voltage_MASK 0xffff0000
+#define DPM_TABLE_36__VddcLevel_0_Voltage__SHIFT 0x10
+#define DPM_TABLE_37__VddcLevel_0_padding_MASK 0xff
+#define DPM_TABLE_37__VddcLevel_0_padding__SHIFT 0x0
+#define DPM_TABLE_37__VddcLevel_0_Smio_MASK 0xff00
+#define DPM_TABLE_37__VddcLevel_0_Smio__SHIFT 0x8
+#define DPM_TABLE_37__VddcLevel_0_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_37__VddcLevel_0_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_38__VddcLevel_1_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_38__VddcLevel_1_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_38__VddcLevel_1_Voltage_MASK 0xffff0000
+#define DPM_TABLE_38__VddcLevel_1_Voltage__SHIFT 0x10
+#define DPM_TABLE_39__VddcLevel_1_padding_MASK 0xff
+#define DPM_TABLE_39__VddcLevel_1_padding__SHIFT 0x0
+#define DPM_TABLE_39__VddcLevel_1_Smio_MASK 0xff00
+#define DPM_TABLE_39__VddcLevel_1_Smio__SHIFT 0x8
+#define DPM_TABLE_39__VddcLevel_1_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_39__VddcLevel_1_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_40__VddcLevel_2_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_40__VddcLevel_2_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_40__VddcLevel_2_Voltage_MASK 0xffff0000
+#define DPM_TABLE_40__VddcLevel_2_Voltage__SHIFT 0x10
+#define DPM_TABLE_41__VddcLevel_2_padding_MASK 0xff
+#define DPM_TABLE_41__VddcLevel_2_padding__SHIFT 0x0
+#define DPM_TABLE_41__VddcLevel_2_Smio_MASK 0xff00
+#define DPM_TABLE_41__VddcLevel_2_Smio__SHIFT 0x8
+#define DPM_TABLE_41__VddcLevel_2_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_41__VddcLevel_2_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_42__VddcLevel_3_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_42__VddcLevel_3_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_42__VddcLevel_3_Voltage_MASK 0xffff0000
+#define DPM_TABLE_42__VddcLevel_3_Voltage__SHIFT 0x10
+#define DPM_TABLE_43__VddcLevel_3_padding_MASK 0xff
+#define DPM_TABLE_43__VddcLevel_3_padding__SHIFT 0x0
+#define DPM_TABLE_43__VddcLevel_3_Smio_MASK 0xff00
+#define DPM_TABLE_43__VddcLevel_3_Smio__SHIFT 0x8
+#define DPM_TABLE_43__VddcLevel_3_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_43__VddcLevel_3_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_44__VddcLevel_4_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_44__VddcLevel_4_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_44__VddcLevel_4_Voltage_MASK 0xffff0000
+#define DPM_TABLE_44__VddcLevel_4_Voltage__SHIFT 0x10
+#define DPM_TABLE_45__VddcLevel_4_padding_MASK 0xff
+#define DPM_TABLE_45__VddcLevel_4_padding__SHIFT 0x0
+#define DPM_TABLE_45__VddcLevel_4_Smio_MASK 0xff00
+#define DPM_TABLE_45__VddcLevel_4_Smio__SHIFT 0x8
+#define DPM_TABLE_45__VddcLevel_4_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_45__VddcLevel_4_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_46__VddcLevel_5_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_46__VddcLevel_5_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_46__VddcLevel_5_Voltage_MASK 0xffff0000
+#define DPM_TABLE_46__VddcLevel_5_Voltage__SHIFT 0x10
+#define DPM_TABLE_47__VddcLevel_5_padding_MASK 0xff
+#define DPM_TABLE_47__VddcLevel_5_padding__SHIFT 0x0
+#define DPM_TABLE_47__VddcLevel_5_Smio_MASK 0xff00
+#define DPM_TABLE_47__VddcLevel_5_Smio__SHIFT 0x8
+#define DPM_TABLE_47__VddcLevel_5_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_47__VddcLevel_5_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_48__VddcLevel_6_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_48__VddcLevel_6_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_48__VddcLevel_6_Voltage_MASK 0xffff0000
+#define DPM_TABLE_48__VddcLevel_6_Voltage__SHIFT 0x10
+#define DPM_TABLE_49__VddcLevel_6_padding_MASK 0xff
+#define DPM_TABLE_49__VddcLevel_6_padding__SHIFT 0x0
+#define DPM_TABLE_49__VddcLevel_6_Smio_MASK 0xff00
+#define DPM_TABLE_49__VddcLevel_6_Smio__SHIFT 0x8
+#define DPM_TABLE_49__VddcLevel_6_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_49__VddcLevel_6_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_50__VddcLevel_7_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_50__VddcLevel_7_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_50__VddcLevel_7_Voltage_MASK 0xffff0000
+#define DPM_TABLE_50__VddcLevel_7_Voltage__SHIFT 0x10
+#define DPM_TABLE_51__VddcLevel_7_padding_MASK 0xff
+#define DPM_TABLE_51__VddcLevel_7_padding__SHIFT 0x0
+#define DPM_TABLE_51__VddcLevel_7_Smio_MASK 0xff00
+#define DPM_TABLE_51__VddcLevel_7_Smio__SHIFT 0x8
+#define DPM_TABLE_51__VddcLevel_7_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_51__VddcLevel_7_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_52__VddciLevel_0_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_52__VddciLevel_0_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_52__VddciLevel_0_Voltage_MASK 0xffff0000
+#define DPM_TABLE_52__VddciLevel_0_Voltage__SHIFT 0x10
+#define DPM_TABLE_53__VddciLevel_0_padding_MASK 0xff
+#define DPM_TABLE_53__VddciLevel_0_padding__SHIFT 0x0
+#define DPM_TABLE_53__VddciLevel_0_Smio_MASK 0xff00
+#define DPM_TABLE_53__VddciLevel_0_Smio__SHIFT 0x8
+#define DPM_TABLE_53__VddciLevel_0_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_53__VddciLevel_0_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_54__VddciLevel_1_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_54__VddciLevel_1_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_54__VddciLevel_1_Voltage_MASK 0xffff0000
+#define DPM_TABLE_54__VddciLevel_1_Voltage__SHIFT 0x10
+#define DPM_TABLE_55__VddciLevel_1_padding_MASK 0xff
+#define DPM_TABLE_55__VddciLevel_1_padding__SHIFT 0x0
+#define DPM_TABLE_55__VddciLevel_1_Smio_MASK 0xff00
+#define DPM_TABLE_55__VddciLevel_1_Smio__SHIFT 0x8
+#define DPM_TABLE_55__VddciLevel_1_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_55__VddciLevel_1_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_56__VddciLevel_2_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_56__VddciLevel_2_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_56__VddciLevel_2_Voltage_MASK 0xffff0000
+#define DPM_TABLE_56__VddciLevel_2_Voltage__SHIFT 0x10
+#define DPM_TABLE_57__VddciLevel_2_padding_MASK 0xff
+#define DPM_TABLE_57__VddciLevel_2_padding__SHIFT 0x0
+#define DPM_TABLE_57__VddciLevel_2_Smio_MASK 0xff00
+#define DPM_TABLE_57__VddciLevel_2_Smio__SHIFT 0x8
+#define DPM_TABLE_57__VddciLevel_2_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_57__VddciLevel_2_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_58__VddciLevel_3_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_58__VddciLevel_3_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_58__VddciLevel_3_Voltage_MASK 0xffff0000
+#define DPM_TABLE_58__VddciLevel_3_Voltage__SHIFT 0x10
+#define DPM_TABLE_59__VddciLevel_3_padding_MASK 0xff
+#define DPM_TABLE_59__VddciLevel_3_padding__SHIFT 0x0
+#define DPM_TABLE_59__VddciLevel_3_Smio_MASK 0xff00
+#define DPM_TABLE_59__VddciLevel_3_Smio__SHIFT 0x8
+#define DPM_TABLE_59__VddciLevel_3_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_59__VddciLevel_3_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_60__MvddLevel_0_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_60__MvddLevel_0_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_60__MvddLevel_0_Voltage_MASK 0xffff0000
+#define DPM_TABLE_60__MvddLevel_0_Voltage__SHIFT 0x10
+#define DPM_TABLE_61__MvddLevel_0_padding_MASK 0xff
+#define DPM_TABLE_61__MvddLevel_0_padding__SHIFT 0x0
+#define DPM_TABLE_61__MvddLevel_0_Smio_MASK 0xff00
+#define DPM_TABLE_61__MvddLevel_0_Smio__SHIFT 0x8
+#define DPM_TABLE_61__MvddLevel_0_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_61__MvddLevel_0_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_62__MvddLevel_1_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_62__MvddLevel_1_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_62__MvddLevel_1_Voltage_MASK 0xffff0000
+#define DPM_TABLE_62__MvddLevel_1_Voltage__SHIFT 0x10
+#define DPM_TABLE_63__MvddLevel_1_padding_MASK 0xff
+#define DPM_TABLE_63__MvddLevel_1_padding__SHIFT 0x0
+#define DPM_TABLE_63__MvddLevel_1_Smio_MASK 0xff00
+#define DPM_TABLE_63__MvddLevel_1_Smio__SHIFT 0x8
+#define DPM_TABLE_63__MvddLevel_1_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_63__MvddLevel_1_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_64__MvddLevel_2_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_64__MvddLevel_2_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_64__MvddLevel_2_Voltage_MASK 0xffff0000
+#define DPM_TABLE_64__MvddLevel_2_Voltage__SHIFT 0x10
+#define DPM_TABLE_65__MvddLevel_2_padding_MASK 0xff
+#define DPM_TABLE_65__MvddLevel_2_padding__SHIFT 0x0
+#define DPM_TABLE_65__MvddLevel_2_Smio_MASK 0xff00
+#define DPM_TABLE_65__MvddLevel_2_Smio__SHIFT 0x8
+#define DPM_TABLE_65__MvddLevel_2_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_65__MvddLevel_2_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_66__MvddLevel_3_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_66__MvddLevel_3_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_66__MvddLevel_3_Voltage_MASK 0xffff0000
+#define DPM_TABLE_66__MvddLevel_3_Voltage__SHIFT 0x10
+#define DPM_TABLE_67__MvddLevel_3_padding_MASK 0xff
+#define DPM_TABLE_67__MvddLevel_3_padding__SHIFT 0x0
+#define DPM_TABLE_67__MvddLevel_3_Smio_MASK 0xff00
+#define DPM_TABLE_67__MvddLevel_3_Smio__SHIFT 0x8
+#define DPM_TABLE_67__MvddLevel_3_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_67__MvddLevel_3_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_68__MasterDeepSleepControl_MASK 0xff
+#define DPM_TABLE_68__MasterDeepSleepControl__SHIFT 0x0
+#define DPM_TABLE_68__LinkLevelCount_MASK 0xff00
+#define DPM_TABLE_68__LinkLevelCount__SHIFT 0x8
+#define DPM_TABLE_68__MemoryDpmLevelCount_MASK 0xff0000
+#define DPM_TABLE_68__MemoryDpmLevelCount__SHIFT 0x10
+#define DPM_TABLE_68__GraphicsDpmLevelCount_MASK 0xff000000
+#define DPM_TABLE_68__GraphicsDpmLevelCount__SHIFT 0x18
+#define DPM_TABLE_69__Reserved_0_MASK 0xffffffff
+#define DPM_TABLE_69__Reserved_0__SHIFT 0x0
+#define DPM_TABLE_70__Reserved_1_MASK 0xffffffff
+#define DPM_TABLE_70__Reserved_1__SHIFT 0x0
+#define DPM_TABLE_71__Reserved_2_MASK 0xffffffff
+#define DPM_TABLE_71__Reserved_2__SHIFT 0x0
+#define DPM_TABLE_72__Reserved_3_MASK 0xffffffff
+#define DPM_TABLE_72__Reserved_3__SHIFT 0x0
+#define DPM_TABLE_73__Reserved_4_MASK 0xffffffff
+#define DPM_TABLE_73__Reserved_4__SHIFT 0x0
+#define DPM_TABLE_74__GraphicsLevel_0_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_74__GraphicsLevel_0_MinVddc__SHIFT 0x0
+#define DPM_TABLE_75__GraphicsLevel_0_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_75__GraphicsLevel_0_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_76__GraphicsLevel_0_SclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_76__GraphicsLevel_0_SclkFrequency__SHIFT 0x0
+#define DPM_TABLE_77__GraphicsLevel_0_ActivityLevel_MASK 0xffff
+#define DPM_TABLE_77__GraphicsLevel_0_ActivityLevel__SHIFT 0x0
+#define DPM_TABLE_77__GraphicsLevel_0_DeepSleepDivId_MASK 0xff0000
+#define DPM_TABLE_77__GraphicsLevel_0_DeepSleepDivId__SHIFT 0x10
+#define DPM_TABLE_77__GraphicsLevel_0_pcieDpmLevel_MASK 0xff000000
+#define DPM_TABLE_77__GraphicsLevel_0_pcieDpmLevel__SHIFT 0x18
+#define DPM_TABLE_78__GraphicsLevel_0_CgSpllFuncCntl3_MASK 0xffffffff
+#define DPM_TABLE_78__GraphicsLevel_0_CgSpllFuncCntl3__SHIFT 0x0
+#define DPM_TABLE_79__GraphicsLevel_0_CgSpllFuncCntl4_MASK 0xffffffff
+#define DPM_TABLE_79__GraphicsLevel_0_CgSpllFuncCntl4__SHIFT 0x0
+#define DPM_TABLE_80__GraphicsLevel_0_SpllSpreadSpectrum_MASK 0xffffffff
+#define DPM_TABLE_80__GraphicsLevel_0_SpllSpreadSpectrum__SHIFT 0x0
+#define DPM_TABLE_81__GraphicsLevel_0_SpllSpreadSpectrum2_MASK 0xffffffff
+#define DPM_TABLE_81__GraphicsLevel_0_SpllSpreadSpectrum2__SHIFT 0x0
+#define DPM_TABLE_82__GraphicsLevel_0_CcPwrDynRm_MASK 0xffffffff
+#define DPM_TABLE_82__GraphicsLevel_0_CcPwrDynRm__SHIFT 0x0
+#define DPM_TABLE_83__GraphicsLevel_0_CcPwrDynRm1_MASK 0xffffffff
+#define DPM_TABLE_83__GraphicsLevel_0_CcPwrDynRm1__SHIFT 0x0
+#define DPM_TABLE_84__GraphicsLevel_0_EnabledForThrottle_MASK 0xff
+#define DPM_TABLE_84__GraphicsLevel_0_EnabledForThrottle__SHIFT 0x0
+#define DPM_TABLE_84__GraphicsLevel_0_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_84__GraphicsLevel_0_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_84__GraphicsLevel_0_DisplayWatermark_MASK 0xff0000
+#define DPM_TABLE_84__GraphicsLevel_0_DisplayWatermark__SHIFT 0x10
+#define DPM_TABLE_84__GraphicsLevel_0_SclkDid_MASK 0xff000000
+#define DPM_TABLE_84__GraphicsLevel_0_SclkDid__SHIFT 0x18
+#define DPM_TABLE_85__GraphicsLevel_0_PowerThrottle_MASK 0xff
+#define DPM_TABLE_85__GraphicsLevel_0_PowerThrottle__SHIFT 0x0
+#define DPM_TABLE_85__GraphicsLevel_0_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_85__GraphicsLevel_0_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_85__GraphicsLevel_0_DownHyst_MASK 0xff0000
+#define DPM_TABLE_85__GraphicsLevel_0_DownHyst__SHIFT 0x10
+#define DPM_TABLE_85__GraphicsLevel_0_UpHyst_MASK 0xff000000
+#define DPM_TABLE_85__GraphicsLevel_0_UpHyst__SHIFT 0x18
+#define DPM_TABLE_86__GraphicsLevel_1_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_86__GraphicsLevel_1_MinVddc__SHIFT 0x0
+#define DPM_TABLE_87__GraphicsLevel_1_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_87__GraphicsLevel_1_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_88__GraphicsLevel_1_SclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_88__GraphicsLevel_1_SclkFrequency__SHIFT 0x0
+#define DPM_TABLE_89__GraphicsLevel_1_ActivityLevel_MASK 0xffff
+#define DPM_TABLE_89__GraphicsLevel_1_ActivityLevel__SHIFT 0x0
+#define DPM_TABLE_89__GraphicsLevel_1_DeepSleepDivId_MASK 0xff0000
+#define DPM_TABLE_89__GraphicsLevel_1_DeepSleepDivId__SHIFT 0x10
+#define DPM_TABLE_89__GraphicsLevel_1_pcieDpmLevel_MASK 0xff000000
+#define DPM_TABLE_89__GraphicsLevel_1_pcieDpmLevel__SHIFT 0x18
+#define DPM_TABLE_90__GraphicsLevel_1_CgSpllFuncCntl3_MASK 0xffffffff
+#define DPM_TABLE_90__GraphicsLevel_1_CgSpllFuncCntl3__SHIFT 0x0
+#define DPM_TABLE_91__GraphicsLevel_1_CgSpllFuncCntl4_MASK 0xffffffff
+#define DPM_TABLE_91__GraphicsLevel_1_CgSpllFuncCntl4__SHIFT 0x0
+#define DPM_TABLE_92__GraphicsLevel_1_SpllSpreadSpectrum_MASK 0xffffffff
+#define DPM_TABLE_92__GraphicsLevel_1_SpllSpreadSpectrum__SHIFT 0x0
+#define DPM_TABLE_93__GraphicsLevel_1_SpllSpreadSpectrum2_MASK 0xffffffff
+#define DPM_TABLE_93__GraphicsLevel_1_SpllSpreadSpectrum2__SHIFT 0x0
+#define DPM_TABLE_94__GraphicsLevel_1_CcPwrDynRm_MASK 0xffffffff
+#define DPM_TABLE_94__GraphicsLevel_1_CcPwrDynRm__SHIFT 0x0
+#define DPM_TABLE_95__GraphicsLevel_1_CcPwrDynRm1_MASK 0xffffffff
+#define DPM_TABLE_95__GraphicsLevel_1_CcPwrDynRm1__SHIFT 0x0
+#define DPM_TABLE_96__GraphicsLevel_1_EnabledForThrottle_MASK 0xff
+#define DPM_TABLE_96__GraphicsLevel_1_EnabledForThrottle__SHIFT 0x0
+#define DPM_TABLE_96__GraphicsLevel_1_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_96__GraphicsLevel_1_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_96__GraphicsLevel_1_DisplayWatermark_MASK 0xff0000
+#define DPM_TABLE_96__GraphicsLevel_1_DisplayWatermark__SHIFT 0x10
+#define DPM_TABLE_96__GraphicsLevel_1_SclkDid_MASK 0xff000000
+#define DPM_TABLE_96__GraphicsLevel_1_SclkDid__SHIFT 0x18
+#define DPM_TABLE_97__GraphicsLevel_1_PowerThrottle_MASK 0xff
+#define DPM_TABLE_97__GraphicsLevel_1_PowerThrottle__SHIFT 0x0
+#define DPM_TABLE_97__GraphicsLevel_1_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_97__GraphicsLevel_1_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_97__GraphicsLevel_1_DownHyst_MASK 0xff0000
+#define DPM_TABLE_97__GraphicsLevel_1_DownHyst__SHIFT 0x10
+#define DPM_TABLE_97__GraphicsLevel_1_UpHyst_MASK 0xff000000
+#define DPM_TABLE_97__GraphicsLevel_1_UpHyst__SHIFT 0x18
+#define DPM_TABLE_98__GraphicsLevel_2_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_98__GraphicsLevel_2_MinVddc__SHIFT 0x0
+#define DPM_TABLE_99__GraphicsLevel_2_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_99__GraphicsLevel_2_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_100__GraphicsLevel_2_SclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_100__GraphicsLevel_2_SclkFrequency__SHIFT 0x0
+#define DPM_TABLE_101__GraphicsLevel_2_ActivityLevel_MASK 0xffff
+#define DPM_TABLE_101__GraphicsLevel_2_ActivityLevel__SHIFT 0x0
+#define DPM_TABLE_101__GraphicsLevel_2_DeepSleepDivId_MASK 0xff0000
+#define DPM_TABLE_101__GraphicsLevel_2_DeepSleepDivId__SHIFT 0x10
+#define DPM_TABLE_101__GraphicsLevel_2_pcieDpmLevel_MASK 0xff000000
+#define DPM_TABLE_101__GraphicsLevel_2_pcieDpmLevel__SHIFT 0x18
+#define DPM_TABLE_102__GraphicsLevel_2_CgSpllFuncCntl3_MASK 0xffffffff
+#define DPM_TABLE_102__GraphicsLevel_2_CgSpllFuncCntl3__SHIFT 0x0
+#define DPM_TABLE_103__GraphicsLevel_2_CgSpllFuncCntl4_MASK 0xffffffff
+#define DPM_TABLE_103__GraphicsLevel_2_CgSpllFuncCntl4__SHIFT 0x0
+#define DPM_TABLE_104__GraphicsLevel_2_SpllSpreadSpectrum_MASK 0xffffffff
+#define DPM_TABLE_104__GraphicsLevel_2_SpllSpreadSpectrum__SHIFT 0x0
+#define DPM_TABLE_105__GraphicsLevel_2_SpllSpreadSpectrum2_MASK 0xffffffff
+#define DPM_TABLE_105__GraphicsLevel_2_SpllSpreadSpectrum2__SHIFT 0x0
+#define DPM_TABLE_106__GraphicsLevel_2_CcPwrDynRm_MASK 0xffffffff
+#define DPM_TABLE_106__GraphicsLevel_2_CcPwrDynRm__SHIFT 0x0
+#define DPM_TABLE_107__GraphicsLevel_2_CcPwrDynRm1_MASK 0xffffffff
+#define DPM_TABLE_107__GraphicsLevel_2_CcPwrDynRm1__SHIFT 0x0
+#define DPM_TABLE_108__GraphicsLevel_2_EnabledForThrottle_MASK 0xff
+#define DPM_TABLE_108__GraphicsLevel_2_EnabledForThrottle__SHIFT 0x0
+#define DPM_TABLE_108__GraphicsLevel_2_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_108__GraphicsLevel_2_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_108__GraphicsLevel_2_DisplayWatermark_MASK 0xff0000
+#define DPM_TABLE_108__GraphicsLevel_2_DisplayWatermark__SHIFT 0x10
+#define DPM_TABLE_108__GraphicsLevel_2_SclkDid_MASK 0xff000000
+#define DPM_TABLE_108__GraphicsLevel_2_SclkDid__SHIFT 0x18
+#define DPM_TABLE_109__GraphicsLevel_2_PowerThrottle_MASK 0xff
+#define DPM_TABLE_109__GraphicsLevel_2_PowerThrottle__SHIFT 0x0
+#define DPM_TABLE_109__GraphicsLevel_2_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_109__GraphicsLevel_2_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_109__GraphicsLevel_2_DownHyst_MASK 0xff0000
+#define DPM_TABLE_109__GraphicsLevel_2_DownHyst__SHIFT 0x10
+#define DPM_TABLE_109__GraphicsLevel_2_UpHyst_MASK 0xff000000
+#define DPM_TABLE_109__GraphicsLevel_2_UpHyst__SHIFT 0x18
+#define DPM_TABLE_110__GraphicsLevel_3_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_110__GraphicsLevel_3_MinVddc__SHIFT 0x0
+#define DPM_TABLE_111__GraphicsLevel_3_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_111__GraphicsLevel_3_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_112__GraphicsLevel_3_SclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_112__GraphicsLevel_3_SclkFrequency__SHIFT 0x0
+#define DPM_TABLE_113__GraphicsLevel_3_ActivityLevel_MASK 0xffff
+#define DPM_TABLE_113__GraphicsLevel_3_ActivityLevel__SHIFT 0x0
+#define DPM_TABLE_113__GraphicsLevel_3_DeepSleepDivId_MASK 0xff0000
+#define DPM_TABLE_113__GraphicsLevel_3_DeepSleepDivId__SHIFT 0x10
+#define DPM_TABLE_113__GraphicsLevel_3_pcieDpmLevel_MASK 0xff000000
+#define DPM_TABLE_113__GraphicsLevel_3_pcieDpmLevel__SHIFT 0x18
+#define DPM_TABLE_114__GraphicsLevel_3_CgSpllFuncCntl3_MASK 0xffffffff
+#define DPM_TABLE_114__GraphicsLevel_3_CgSpllFuncCntl3__SHIFT 0x0
+#define DPM_TABLE_115__GraphicsLevel_3_CgSpllFuncCntl4_MASK 0xffffffff
+#define DPM_TABLE_115__GraphicsLevel_3_CgSpllFuncCntl4__SHIFT 0x0
+#define DPM_TABLE_116__GraphicsLevel_3_SpllSpreadSpectrum_MASK 0xffffffff
+#define DPM_TABLE_116__GraphicsLevel_3_SpllSpreadSpectrum__SHIFT 0x0
+#define DPM_TABLE_117__GraphicsLevel_3_SpllSpreadSpectrum2_MASK 0xffffffff
+#define DPM_TABLE_117__GraphicsLevel_3_SpllSpreadSpectrum2__SHIFT 0x0
+#define DPM_TABLE_118__GraphicsLevel_3_CcPwrDynRm_MASK 0xffffffff
+#define DPM_TABLE_118__GraphicsLevel_3_CcPwrDynRm__SHIFT 0x0
+#define DPM_TABLE_119__GraphicsLevel_3_CcPwrDynRm1_MASK 0xffffffff
+#define DPM_TABLE_119__GraphicsLevel_3_CcPwrDynRm1__SHIFT 0x0
+#define DPM_TABLE_120__GraphicsLevel_3_EnabledForThrottle_MASK 0xff
+#define DPM_TABLE_120__GraphicsLevel_3_EnabledForThrottle__SHIFT 0x0
+#define DPM_TABLE_120__GraphicsLevel_3_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_120__GraphicsLevel_3_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_120__GraphicsLevel_3_DisplayWatermark_MASK 0xff0000
+#define DPM_TABLE_120__GraphicsLevel_3_DisplayWatermark__SHIFT 0x10
+#define DPM_TABLE_120__GraphicsLevel_3_SclkDid_MASK 0xff000000
+#define DPM_TABLE_120__GraphicsLevel_3_SclkDid__SHIFT 0x18
+#define DPM_TABLE_121__GraphicsLevel_3_PowerThrottle_MASK 0xff
+#define DPM_TABLE_121__GraphicsLevel_3_PowerThrottle__SHIFT 0x0
+#define DPM_TABLE_121__GraphicsLevel_3_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_121__GraphicsLevel_3_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_121__GraphicsLevel_3_DownHyst_MASK 0xff0000
+#define DPM_TABLE_121__GraphicsLevel_3_DownHyst__SHIFT 0x10
+#define DPM_TABLE_121__GraphicsLevel_3_UpHyst_MASK 0xff000000
+#define DPM_TABLE_121__GraphicsLevel_3_UpHyst__SHIFT 0x18
+#define DPM_TABLE_122__GraphicsLevel_4_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_122__GraphicsLevel_4_MinVddc__SHIFT 0x0
+#define DPM_TABLE_123__GraphicsLevel_4_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_123__GraphicsLevel_4_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_124__GraphicsLevel_4_SclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_124__GraphicsLevel_4_SclkFrequency__SHIFT 0x0
+#define DPM_TABLE_125__GraphicsLevel_4_ActivityLevel_MASK 0xffff
+#define DPM_TABLE_125__GraphicsLevel_4_ActivityLevel__SHIFT 0x0
+#define DPM_TABLE_125__GraphicsLevel_4_DeepSleepDivId_MASK 0xff0000
+#define DPM_TABLE_125__GraphicsLevel_4_DeepSleepDivId__SHIFT 0x10
+#define DPM_TABLE_125__GraphicsLevel_4_pcieDpmLevel_MASK 0xff000000
+#define DPM_TABLE_125__GraphicsLevel_4_pcieDpmLevel__SHIFT 0x18
+#define DPM_TABLE_126__GraphicsLevel_4_CgSpllFuncCntl3_MASK 0xffffffff
+#define DPM_TABLE_126__GraphicsLevel_4_CgSpllFuncCntl3__SHIFT 0x0
+#define DPM_TABLE_127__GraphicsLevel_4_CgSpllFuncCntl4_MASK 0xffffffff
+#define DPM_TABLE_127__GraphicsLevel_4_CgSpllFuncCntl4__SHIFT 0x0
+#define DPM_TABLE_128__GraphicsLevel_4_SpllSpreadSpectrum_MASK 0xffffffff
+#define DPM_TABLE_128__GraphicsLevel_4_SpllSpreadSpectrum__SHIFT 0x0
+#define DPM_TABLE_129__GraphicsLevel_4_SpllSpreadSpectrum2_MASK 0xffffffff
+#define DPM_TABLE_129__GraphicsLevel_4_SpllSpreadSpectrum2__SHIFT 0x0
+#define DPM_TABLE_130__GraphicsLevel_4_CcPwrDynRm_MASK 0xffffffff
+#define DPM_TABLE_130__GraphicsLevel_4_CcPwrDynRm__SHIFT 0x0
+#define DPM_TABLE_131__GraphicsLevel_4_CcPwrDynRm1_MASK 0xffffffff
+#define DPM_TABLE_131__GraphicsLevel_4_CcPwrDynRm1__SHIFT 0x0
+#define DPM_TABLE_132__GraphicsLevel_4_EnabledForThrottle_MASK 0xff
+#define DPM_TABLE_132__GraphicsLevel_4_EnabledForThrottle__SHIFT 0x0
+#define DPM_TABLE_132__GraphicsLevel_4_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_132__GraphicsLevel_4_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_132__GraphicsLevel_4_DisplayWatermark_MASK 0xff0000
+#define DPM_TABLE_132__GraphicsLevel_4_DisplayWatermark__SHIFT 0x10
+#define DPM_TABLE_132__GraphicsLevel_4_SclkDid_MASK 0xff000000
+#define DPM_TABLE_132__GraphicsLevel_4_SclkDid__SHIFT 0x18
+#define DPM_TABLE_133__GraphicsLevel_4_PowerThrottle_MASK 0xff
+#define DPM_TABLE_133__GraphicsLevel_4_PowerThrottle__SHIFT 0x0
+#define DPM_TABLE_133__GraphicsLevel_4_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_133__GraphicsLevel_4_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_133__GraphicsLevel_4_DownHyst_MASK 0xff0000
+#define DPM_TABLE_133__GraphicsLevel_4_DownHyst__SHIFT 0x10
+#define DPM_TABLE_133__GraphicsLevel_4_UpHyst_MASK 0xff000000
+#define DPM_TABLE_133__GraphicsLevel_4_UpHyst__SHIFT 0x18
+#define DPM_TABLE_134__GraphicsLevel_5_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_134__GraphicsLevel_5_MinVddc__SHIFT 0x0
+#define DPM_TABLE_135__GraphicsLevel_5_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_135__GraphicsLevel_5_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_136__GraphicsLevel_5_SclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_136__GraphicsLevel_5_SclkFrequency__SHIFT 0x0
+#define DPM_TABLE_137__GraphicsLevel_5_ActivityLevel_MASK 0xffff
+#define DPM_TABLE_137__GraphicsLevel_5_ActivityLevel__SHIFT 0x0
+#define DPM_TABLE_137__GraphicsLevel_5_DeepSleepDivId_MASK 0xff0000
+#define DPM_TABLE_137__GraphicsLevel_5_DeepSleepDivId__SHIFT 0x10
+#define DPM_TABLE_137__GraphicsLevel_5_pcieDpmLevel_MASK 0xff000000
+#define DPM_TABLE_137__GraphicsLevel_5_pcieDpmLevel__SHIFT 0x18
+#define DPM_TABLE_138__GraphicsLevel_5_CgSpllFuncCntl3_MASK 0xffffffff
+#define DPM_TABLE_138__GraphicsLevel_5_CgSpllFuncCntl3__SHIFT 0x0
+#define DPM_TABLE_139__GraphicsLevel_5_CgSpllFuncCntl4_MASK 0xffffffff
+#define DPM_TABLE_139__GraphicsLevel_5_CgSpllFuncCntl4__SHIFT 0x0
+#define DPM_TABLE_140__GraphicsLevel_5_SpllSpreadSpectrum_MASK 0xffffffff
+#define DPM_TABLE_140__GraphicsLevel_5_SpllSpreadSpectrum__SHIFT 0x0
+#define DPM_TABLE_141__GraphicsLevel_5_SpllSpreadSpectrum2_MASK 0xffffffff
+#define DPM_TABLE_141__GraphicsLevel_5_SpllSpreadSpectrum2__SHIFT 0x0
+#define DPM_TABLE_142__GraphicsLevel_5_CcPwrDynRm_MASK 0xffffffff
+#define DPM_TABLE_142__GraphicsLevel_5_CcPwrDynRm__SHIFT 0x0
+#define DPM_TABLE_143__GraphicsLevel_5_CcPwrDynRm1_MASK 0xffffffff
+#define DPM_TABLE_143__GraphicsLevel_5_CcPwrDynRm1__SHIFT 0x0
+#define DPM_TABLE_144__GraphicsLevel_5_EnabledForThrottle_MASK 0xff
+#define DPM_TABLE_144__GraphicsLevel_5_EnabledForThrottle__SHIFT 0x0
+#define DPM_TABLE_144__GraphicsLevel_5_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_144__GraphicsLevel_5_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_144__GraphicsLevel_5_DisplayWatermark_MASK 0xff0000
+#define DPM_TABLE_144__GraphicsLevel_5_DisplayWatermark__SHIFT 0x10
+#define DPM_TABLE_144__GraphicsLevel_5_SclkDid_MASK 0xff000000
+#define DPM_TABLE_144__GraphicsLevel_5_SclkDid__SHIFT 0x18
+#define DPM_TABLE_145__GraphicsLevel_5_PowerThrottle_MASK 0xff
+#define DPM_TABLE_145__GraphicsLevel_5_PowerThrottle__SHIFT 0x0
+#define DPM_TABLE_145__GraphicsLevel_5_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_145__GraphicsLevel_5_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_145__GraphicsLevel_5_DownHyst_MASK 0xff0000
+#define DPM_TABLE_145__GraphicsLevel_5_DownHyst__SHIFT 0x10
+#define DPM_TABLE_145__GraphicsLevel_5_UpHyst_MASK 0xff000000
+#define DPM_TABLE_145__GraphicsLevel_5_UpHyst__SHIFT 0x18
+#define DPM_TABLE_146__GraphicsLevel_6_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_146__GraphicsLevel_6_MinVddc__SHIFT 0x0
+#define DPM_TABLE_147__GraphicsLevel_6_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_147__GraphicsLevel_6_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_148__GraphicsLevel_6_SclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_148__GraphicsLevel_6_SclkFrequency__SHIFT 0x0
+#define DPM_TABLE_149__GraphicsLevel_6_ActivityLevel_MASK 0xffff
+#define DPM_TABLE_149__GraphicsLevel_6_ActivityLevel__SHIFT 0x0
+#define DPM_TABLE_149__GraphicsLevel_6_DeepSleepDivId_MASK 0xff0000
+#define DPM_TABLE_149__GraphicsLevel_6_DeepSleepDivId__SHIFT 0x10
+#define DPM_TABLE_149__GraphicsLevel_6_pcieDpmLevel_MASK 0xff000000
+#define DPM_TABLE_149__GraphicsLevel_6_pcieDpmLevel__SHIFT 0x18
+#define DPM_TABLE_150__GraphicsLevel_6_CgSpllFuncCntl3_MASK 0xffffffff
+#define DPM_TABLE_150__GraphicsLevel_6_CgSpllFuncCntl3__SHIFT 0x0
+#define DPM_TABLE_151__GraphicsLevel_6_CgSpllFuncCntl4_MASK 0xffffffff
+#define DPM_TABLE_151__GraphicsLevel_6_CgSpllFuncCntl4__SHIFT 0x0
+#define DPM_TABLE_152__GraphicsLevel_6_SpllSpreadSpectrum_MASK 0xffffffff
+#define DPM_TABLE_152__GraphicsLevel_6_SpllSpreadSpectrum__SHIFT 0x0
+#define DPM_TABLE_153__GraphicsLevel_6_SpllSpreadSpectrum2_MASK 0xffffffff
+#define DPM_TABLE_153__GraphicsLevel_6_SpllSpreadSpectrum2__SHIFT 0x0
+#define DPM_TABLE_154__GraphicsLevel_6_CcPwrDynRm_MASK 0xffffffff
+#define DPM_TABLE_154__GraphicsLevel_6_CcPwrDynRm__SHIFT 0x0
+#define DPM_TABLE_155__GraphicsLevel_6_CcPwrDynRm1_MASK 0xffffffff
+#define DPM_TABLE_155__GraphicsLevel_6_CcPwrDynRm1__SHIFT 0x0
+#define DPM_TABLE_156__GraphicsLevel_6_EnabledForThrottle_MASK 0xff
+#define DPM_TABLE_156__GraphicsLevel_6_EnabledForThrottle__SHIFT 0x0
+#define DPM_TABLE_156__GraphicsLevel_6_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_156__GraphicsLevel_6_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_156__GraphicsLevel_6_DisplayWatermark_MASK 0xff0000
+#define DPM_TABLE_156__GraphicsLevel_6_DisplayWatermark__SHIFT 0x10
+#define DPM_TABLE_156__GraphicsLevel_6_SclkDid_MASK 0xff000000
+#define DPM_TABLE_156__GraphicsLevel_6_SclkDid__SHIFT 0x18
+#define DPM_TABLE_157__GraphicsLevel_6_PowerThrottle_MASK 0xff
+#define DPM_TABLE_157__GraphicsLevel_6_PowerThrottle__SHIFT 0x0
+#define DPM_TABLE_157__GraphicsLevel_6_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_157__GraphicsLevel_6_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_157__GraphicsLevel_6_DownHyst_MASK 0xff0000
+#define DPM_TABLE_157__GraphicsLevel_6_DownHyst__SHIFT 0x10
+#define DPM_TABLE_157__GraphicsLevel_6_UpHyst_MASK 0xff000000
+#define DPM_TABLE_157__GraphicsLevel_6_UpHyst__SHIFT 0x18
+#define DPM_TABLE_158__GraphicsLevel_7_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_158__GraphicsLevel_7_MinVddc__SHIFT 0x0
+#define DPM_TABLE_159__GraphicsLevel_7_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_159__GraphicsLevel_7_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_160__GraphicsLevel_7_SclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_160__GraphicsLevel_7_SclkFrequency__SHIFT 0x0
+#define DPM_TABLE_161__GraphicsLevel_7_ActivityLevel_MASK 0xffff
+#define DPM_TABLE_161__GraphicsLevel_7_ActivityLevel__SHIFT 0x0
+#define DPM_TABLE_161__GraphicsLevel_7_DeepSleepDivId_MASK 0xff0000
+#define DPM_TABLE_161__GraphicsLevel_7_DeepSleepDivId__SHIFT 0x10
+#define DPM_TABLE_161__GraphicsLevel_7_pcieDpmLevel_MASK 0xff000000
+#define DPM_TABLE_161__GraphicsLevel_7_pcieDpmLevel__SHIFT 0x18
+#define DPM_TABLE_162__GraphicsLevel_7_CgSpllFuncCntl3_MASK 0xffffffff
+#define DPM_TABLE_162__GraphicsLevel_7_CgSpllFuncCntl3__SHIFT 0x0
+#define DPM_TABLE_163__GraphicsLevel_7_CgSpllFuncCntl4_MASK 0xffffffff
+#define DPM_TABLE_163__GraphicsLevel_7_CgSpllFuncCntl4__SHIFT 0x0
+#define DPM_TABLE_164__GraphicsLevel_7_SpllSpreadSpectrum_MASK 0xffffffff
+#define DPM_TABLE_164__GraphicsLevel_7_SpllSpreadSpectrum__SHIFT 0x0
+#define DPM_TABLE_165__GraphicsLevel_7_SpllSpreadSpectrum2_MASK 0xffffffff
+#define DPM_TABLE_165__GraphicsLevel_7_SpllSpreadSpectrum2__SHIFT 0x0
+#define DPM_TABLE_166__GraphicsLevel_7_CcPwrDynRm_MASK 0xffffffff
+#define DPM_TABLE_166__GraphicsLevel_7_CcPwrDynRm__SHIFT 0x0
+#define DPM_TABLE_167__GraphicsLevel_7_CcPwrDynRm1_MASK 0xffffffff
+#define DPM_TABLE_167__GraphicsLevel_7_CcPwrDynRm1__SHIFT 0x0
+#define DPM_TABLE_168__GraphicsLevel_7_EnabledForThrottle_MASK 0xff
+#define DPM_TABLE_168__GraphicsLevel_7_EnabledForThrottle__SHIFT 0x0
+#define DPM_TABLE_168__GraphicsLevel_7_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_168__GraphicsLevel_7_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_168__GraphicsLevel_7_DisplayWatermark_MASK 0xff0000
+#define DPM_TABLE_168__GraphicsLevel_7_DisplayWatermark__SHIFT 0x10
+#define DPM_TABLE_168__GraphicsLevel_7_SclkDid_MASK 0xff000000
+#define DPM_TABLE_168__GraphicsLevel_7_SclkDid__SHIFT 0x18
+#define DPM_TABLE_169__GraphicsLevel_7_PowerThrottle_MASK 0xff
+#define DPM_TABLE_169__GraphicsLevel_7_PowerThrottle__SHIFT 0x0
+#define DPM_TABLE_169__GraphicsLevel_7_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_169__GraphicsLevel_7_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_169__GraphicsLevel_7_DownHyst_MASK 0xff0000
+#define DPM_TABLE_169__GraphicsLevel_7_DownHyst__SHIFT 0x10
+#define DPM_TABLE_169__GraphicsLevel_7_UpHyst_MASK 0xff000000
+#define DPM_TABLE_169__GraphicsLevel_7_UpHyst__SHIFT 0x18
+#define DPM_TABLE_170__MemoryACPILevel_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_170__MemoryACPILevel_MinVddc__SHIFT 0x0
+#define DPM_TABLE_171__MemoryACPILevel_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_171__MemoryACPILevel_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_172__MemoryACPILevel_MinVddci_MASK 0xffffffff
+#define DPM_TABLE_172__MemoryACPILevel_MinVddci__SHIFT 0x0
+#define DPM_TABLE_173__MemoryACPILevel_MinMvdd_MASK 0xffffffff
+#define DPM_TABLE_173__MemoryACPILevel_MinMvdd__SHIFT 0x0
+#define DPM_TABLE_174__MemoryACPILevel_MclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_174__MemoryACPILevel_MclkFrequency__SHIFT 0x0
+#define DPM_TABLE_175__MemoryACPILevel_StutterEnable_MASK 0xff
+#define DPM_TABLE_175__MemoryACPILevel_StutterEnable__SHIFT 0x0
+#define DPM_TABLE_175__MemoryACPILevel_RttEnable_MASK 0xff00
+#define DPM_TABLE_175__MemoryACPILevel_RttEnable__SHIFT 0x8
+#define DPM_TABLE_175__MemoryACPILevel_EdcWriteEnable_MASK 0xff0000
+#define DPM_TABLE_175__MemoryACPILevel_EdcWriteEnable__SHIFT 0x10
+#define DPM_TABLE_175__MemoryACPILevel_EdcReadEnable_MASK 0xff000000
+#define DPM_TABLE_175__MemoryACPILevel_EdcReadEnable__SHIFT 0x18
+#define DPM_TABLE_176__MemoryACPILevel_EnabledForActivity_MASK 0xff
+#define DPM_TABLE_176__MemoryACPILevel_EnabledForActivity__SHIFT 0x0
+#define DPM_TABLE_176__MemoryACPILevel_EnabledForThrottle_MASK 0xff00
+#define DPM_TABLE_176__MemoryACPILevel_EnabledForThrottle__SHIFT 0x8
+#define DPM_TABLE_176__MemoryACPILevel_StrobeRatio_MASK 0xff0000
+#define DPM_TABLE_176__MemoryACPILevel_StrobeRatio__SHIFT 0x10
+#define DPM_TABLE_176__MemoryACPILevel_StrobeEnable_MASK 0xff000000
+#define DPM_TABLE_176__MemoryACPILevel_StrobeEnable__SHIFT 0x18
+#define DPM_TABLE_177__MemoryACPILevel_padding_MASK 0xff
+#define DPM_TABLE_177__MemoryACPILevel_padding__SHIFT 0x0
+#define DPM_TABLE_177__MemoryACPILevel_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_177__MemoryACPILevel_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_177__MemoryACPILevel_DownHyst_MASK 0xff0000
+#define DPM_TABLE_177__MemoryACPILevel_DownHyst__SHIFT 0x10
+#define DPM_TABLE_177__MemoryACPILevel_UpHyst_MASK 0xff000000
+#define DPM_TABLE_177__MemoryACPILevel_UpHyst__SHIFT 0x18
+#define DPM_TABLE_178__MemoryACPILevel_padding1_MASK 0xff
+#define DPM_TABLE_178__MemoryACPILevel_padding1__SHIFT 0x0
+#define DPM_TABLE_178__MemoryACPILevel_DisplayWatermark_MASK 0xff00
+#define DPM_TABLE_178__MemoryACPILevel_DisplayWatermark__SHIFT 0x8
+#define DPM_TABLE_178__MemoryACPILevel_ActivityLevel_MASK 0xffff0000
+#define DPM_TABLE_178__MemoryACPILevel_ActivityLevel__SHIFT 0x10
+#define DPM_TABLE_179__MemoryACPILevel_MpllFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_179__MemoryACPILevel_MpllFuncCntl__SHIFT 0x0
+#define DPM_TABLE_180__MemoryACPILevel_MpllFuncCntl_1_MASK 0xffffffff
+#define DPM_TABLE_180__MemoryACPILevel_MpllFuncCntl_1__SHIFT 0x0
+#define DPM_TABLE_181__MemoryACPILevel_MpllFuncCntl_2_MASK 0xffffffff
+#define DPM_TABLE_181__MemoryACPILevel_MpllFuncCntl_2__SHIFT 0x0
+#define DPM_TABLE_182__MemoryACPILevel_MpllAdFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_182__MemoryACPILevel_MpllAdFuncCntl__SHIFT 0x0
+#define DPM_TABLE_183__MemoryACPILevel_MpllDqFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_183__MemoryACPILevel_MpllDqFuncCntl__SHIFT 0x0
+#define DPM_TABLE_184__MemoryACPILevel_MclkPwrmgtCntl_MASK 0xffffffff
+#define DPM_TABLE_184__MemoryACPILevel_MclkPwrmgtCntl__SHIFT 0x0
+#define DPM_TABLE_185__MemoryACPILevel_DllCntl_MASK 0xffffffff
+#define DPM_TABLE_185__MemoryACPILevel_DllCntl__SHIFT 0x0
+#define DPM_TABLE_186__MemoryACPILevel_MpllSs1_MASK 0xffffffff
+#define DPM_TABLE_186__MemoryACPILevel_MpllSs1__SHIFT 0x0
+#define DPM_TABLE_187__MemoryACPILevel_MpllSs2_MASK 0xffffffff
+#define DPM_TABLE_187__MemoryACPILevel_MpllSs2__SHIFT 0x0
+#define DPM_TABLE_188__MemoryLevel_0_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_188__MemoryLevel_0_MinVddc__SHIFT 0x0
+#define DPM_TABLE_189__MemoryLevel_0_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_189__MemoryLevel_0_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_190__MemoryLevel_0_MinVddci_MASK 0xffffffff
+#define DPM_TABLE_190__MemoryLevel_0_MinVddci__SHIFT 0x0
+#define DPM_TABLE_191__MemoryLevel_0_MinMvdd_MASK 0xffffffff
+#define DPM_TABLE_191__MemoryLevel_0_MinMvdd__SHIFT 0x0
+#define DPM_TABLE_192__MemoryLevel_0_MclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_192__MemoryLevel_0_MclkFrequency__SHIFT 0x0
+#define DPM_TABLE_193__MemoryLevel_0_StutterEnable_MASK 0xff
+#define DPM_TABLE_193__MemoryLevel_0_StutterEnable__SHIFT 0x0
+#define DPM_TABLE_193__MemoryLevel_0_RttEnable_MASK 0xff00
+#define DPM_TABLE_193__MemoryLevel_0_RttEnable__SHIFT 0x8
+#define DPM_TABLE_193__MemoryLevel_0_EdcWriteEnable_MASK 0xff0000
+#define DPM_TABLE_193__MemoryLevel_0_EdcWriteEnable__SHIFT 0x10
+#define DPM_TABLE_193__MemoryLevel_0_EdcReadEnable_MASK 0xff000000
+#define DPM_TABLE_193__MemoryLevel_0_EdcReadEnable__SHIFT 0x18
+#define DPM_TABLE_194__MemoryLevel_0_EnabledForActivity_MASK 0xff
+#define DPM_TABLE_194__MemoryLevel_0_EnabledForActivity__SHIFT 0x0
+#define DPM_TABLE_194__MemoryLevel_0_EnabledForThrottle_MASK 0xff00
+#define DPM_TABLE_194__MemoryLevel_0_EnabledForThrottle__SHIFT 0x8
+#define DPM_TABLE_194__MemoryLevel_0_StrobeRatio_MASK 0xff0000
+#define DPM_TABLE_194__MemoryLevel_0_StrobeRatio__SHIFT 0x10
+#define DPM_TABLE_194__MemoryLevel_0_StrobeEnable_MASK 0xff000000
+#define DPM_TABLE_194__MemoryLevel_0_StrobeEnable__SHIFT 0x18
+#define DPM_TABLE_195__MemoryLevel_0_padding_MASK 0xff
+#define DPM_TABLE_195__MemoryLevel_0_padding__SHIFT 0x0
+#define DPM_TABLE_195__MemoryLevel_0_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_195__MemoryLevel_0_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_195__MemoryLevel_0_DownHyst_MASK 0xff0000
+#define DPM_TABLE_195__MemoryLevel_0_DownHyst__SHIFT 0x10
+#define DPM_TABLE_195__MemoryLevel_0_UpHyst_MASK 0xff000000
+#define DPM_TABLE_195__MemoryLevel_0_UpHyst__SHIFT 0x18
+#define DPM_TABLE_196__MemoryLevel_0_padding1_MASK 0xff
+#define DPM_TABLE_196__MemoryLevel_0_padding1__SHIFT 0x0
+#define DPM_TABLE_196__MemoryLevel_0_DisplayWatermark_MASK 0xff00
+#define DPM_TABLE_196__MemoryLevel_0_DisplayWatermark__SHIFT 0x8
+#define DPM_TABLE_196__MemoryLevel_0_ActivityLevel_MASK 0xffff0000
+#define DPM_TABLE_196__MemoryLevel_0_ActivityLevel__SHIFT 0x10
+#define DPM_TABLE_197__MemoryLevel_0_MpllFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_197__MemoryLevel_0_MpllFuncCntl__SHIFT 0x0
+#define DPM_TABLE_198__MemoryLevel_0_MpllFuncCntl_1_MASK 0xffffffff
+#define DPM_TABLE_198__MemoryLevel_0_MpllFuncCntl_1__SHIFT 0x0
+#define DPM_TABLE_199__MemoryLevel_0_MpllFuncCntl_2_MASK 0xffffffff
+#define DPM_TABLE_199__MemoryLevel_0_MpllFuncCntl_2__SHIFT 0x0
+#define DPM_TABLE_200__MemoryLevel_0_MpllAdFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_200__MemoryLevel_0_MpllAdFuncCntl__SHIFT 0x0
+#define DPM_TABLE_201__MemoryLevel_0_MpllDqFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_201__MemoryLevel_0_MpllDqFuncCntl__SHIFT 0x0
+#define DPM_TABLE_202__MemoryLevel_0_MclkPwrmgtCntl_MASK 0xffffffff
+#define DPM_TABLE_202__MemoryLevel_0_MclkPwrmgtCntl__SHIFT 0x0
+#define DPM_TABLE_203__MemoryLevel_0_DllCntl_MASK 0xffffffff
+#define DPM_TABLE_203__MemoryLevel_0_DllCntl__SHIFT 0x0
+#define DPM_TABLE_204__MemoryLevel_0_MpllSs1_MASK 0xffffffff
+#define DPM_TABLE_204__MemoryLevel_0_MpllSs1__SHIFT 0x0
+#define DPM_TABLE_205__MemoryLevel_0_MpllSs2_MASK 0xffffffff
+#define DPM_TABLE_205__MemoryLevel_0_MpllSs2__SHIFT 0x0
+#define DPM_TABLE_206__MemoryLevel_1_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_206__MemoryLevel_1_MinVddc__SHIFT 0x0
+#define DPM_TABLE_207__MemoryLevel_1_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_207__MemoryLevel_1_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_208__MemoryLevel_1_MinVddci_MASK 0xffffffff
+#define DPM_TABLE_208__MemoryLevel_1_MinVddci__SHIFT 0x0
+#define DPM_TABLE_209__MemoryLevel_1_MinMvdd_MASK 0xffffffff
+#define DPM_TABLE_209__MemoryLevel_1_MinMvdd__SHIFT 0x0
+#define DPM_TABLE_210__MemoryLevel_1_MclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_210__MemoryLevel_1_MclkFrequency__SHIFT 0x0
+#define DPM_TABLE_211__MemoryLevel_1_StutterEnable_MASK 0xff
+#define DPM_TABLE_211__MemoryLevel_1_StutterEnable__SHIFT 0x0
+#define DPM_TABLE_211__MemoryLevel_1_RttEnable_MASK 0xff00
+#define DPM_TABLE_211__MemoryLevel_1_RttEnable__SHIFT 0x8
+#define DPM_TABLE_211__MemoryLevel_1_EdcWriteEnable_MASK 0xff0000
+#define DPM_TABLE_211__MemoryLevel_1_EdcWriteEnable__SHIFT 0x10
+#define DPM_TABLE_211__MemoryLevel_1_EdcReadEnable_MASK 0xff000000
+#define DPM_TABLE_211__MemoryLevel_1_EdcReadEnable__SHIFT 0x18
+#define DPM_TABLE_212__MemoryLevel_1_EnabledForActivity_MASK 0xff
+#define DPM_TABLE_212__MemoryLevel_1_EnabledForActivity__SHIFT 0x0
+#define DPM_TABLE_212__MemoryLevel_1_EnabledForThrottle_MASK 0xff00
+#define DPM_TABLE_212__MemoryLevel_1_EnabledForThrottle__SHIFT 0x8
+#define DPM_TABLE_212__MemoryLevel_1_StrobeRatio_MASK 0xff0000
+#define DPM_TABLE_212__MemoryLevel_1_StrobeRatio__SHIFT 0x10
+#define DPM_TABLE_212__MemoryLevel_1_StrobeEnable_MASK 0xff000000
+#define DPM_TABLE_212__MemoryLevel_1_StrobeEnable__SHIFT 0x18
+#define DPM_TABLE_213__MemoryLevel_1_padding_MASK 0xff
+#define DPM_TABLE_213__MemoryLevel_1_padding__SHIFT 0x0
+#define DPM_TABLE_213__MemoryLevel_1_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_213__MemoryLevel_1_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_213__MemoryLevel_1_DownHyst_MASK 0xff0000
+#define DPM_TABLE_213__MemoryLevel_1_DownHyst__SHIFT 0x10
+#define DPM_TABLE_213__MemoryLevel_1_UpHyst_MASK 0xff000000
+#define DPM_TABLE_213__MemoryLevel_1_UpHyst__SHIFT 0x18
+#define DPM_TABLE_214__MemoryLevel_1_padding1_MASK 0xff
+#define DPM_TABLE_214__MemoryLevel_1_padding1__SHIFT 0x0
+#define DPM_TABLE_214__MemoryLevel_1_DisplayWatermark_MASK 0xff00
+#define DPM_TABLE_214__MemoryLevel_1_DisplayWatermark__SHIFT 0x8
+#define DPM_TABLE_214__MemoryLevel_1_ActivityLevel_MASK 0xffff0000
+#define DPM_TABLE_214__MemoryLevel_1_ActivityLevel__SHIFT 0x10
+#define DPM_TABLE_215__MemoryLevel_1_MpllFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_215__MemoryLevel_1_MpllFuncCntl__SHIFT 0x0
+#define DPM_TABLE_216__MemoryLevel_1_MpllFuncCntl_1_MASK 0xffffffff
+#define DPM_TABLE_216__MemoryLevel_1_MpllFuncCntl_1__SHIFT 0x0
+#define DPM_TABLE_217__MemoryLevel_1_MpllFuncCntl_2_MASK 0xffffffff
+#define DPM_TABLE_217__MemoryLevel_1_MpllFuncCntl_2__SHIFT 0x0
+#define DPM_TABLE_218__MemoryLevel_1_MpllAdFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_218__MemoryLevel_1_MpllAdFuncCntl__SHIFT 0x0
+#define DPM_TABLE_219__MemoryLevel_1_MpllDqFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_219__MemoryLevel_1_MpllDqFuncCntl__SHIFT 0x0
+#define DPM_TABLE_220__MemoryLevel_1_MclkPwrmgtCntl_MASK 0xffffffff
+#define DPM_TABLE_220__MemoryLevel_1_MclkPwrmgtCntl__SHIFT 0x0
+#define DPM_TABLE_221__MemoryLevel_1_DllCntl_MASK 0xffffffff
+#define DPM_TABLE_221__MemoryLevel_1_DllCntl__SHIFT 0x0
+#define DPM_TABLE_222__MemoryLevel_1_MpllSs1_MASK 0xffffffff
+#define DPM_TABLE_222__MemoryLevel_1_MpllSs1__SHIFT 0x0
+#define DPM_TABLE_223__MemoryLevel_1_MpllSs2_MASK 0xffffffff
+#define DPM_TABLE_223__MemoryLevel_1_MpllSs2__SHIFT 0x0
+#define DPM_TABLE_224__MemoryLevel_2_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_224__MemoryLevel_2_MinVddc__SHIFT 0x0
+#define DPM_TABLE_225__MemoryLevel_2_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_225__MemoryLevel_2_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_226__MemoryLevel_2_MinVddci_MASK 0xffffffff
+#define DPM_TABLE_226__MemoryLevel_2_MinVddci__SHIFT 0x0
+#define DPM_TABLE_227__MemoryLevel_2_MinMvdd_MASK 0xffffffff
+#define DPM_TABLE_227__MemoryLevel_2_MinMvdd__SHIFT 0x0
+#define DPM_TABLE_228__MemoryLevel_2_MclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_228__MemoryLevel_2_MclkFrequency__SHIFT 0x0
+#define DPM_TABLE_229__MemoryLevel_2_StutterEnable_MASK 0xff
+#define DPM_TABLE_229__MemoryLevel_2_StutterEnable__SHIFT 0x0
+#define DPM_TABLE_229__MemoryLevel_2_RttEnable_MASK 0xff00
+#define DPM_TABLE_229__MemoryLevel_2_RttEnable__SHIFT 0x8
+#define DPM_TABLE_229__MemoryLevel_2_EdcWriteEnable_MASK 0xff0000
+#define DPM_TABLE_229__MemoryLevel_2_EdcWriteEnable__SHIFT 0x10
+#define DPM_TABLE_229__MemoryLevel_2_EdcReadEnable_MASK 0xff000000
+#define DPM_TABLE_229__MemoryLevel_2_EdcReadEnable__SHIFT 0x18
+#define DPM_TABLE_230__MemoryLevel_2_EnabledForActivity_MASK 0xff
+#define DPM_TABLE_230__MemoryLevel_2_EnabledForActivity__SHIFT 0x0
+#define DPM_TABLE_230__MemoryLevel_2_EnabledForThrottle_MASK 0xff00
+#define DPM_TABLE_230__MemoryLevel_2_EnabledForThrottle__SHIFT 0x8
+#define DPM_TABLE_230__MemoryLevel_2_StrobeRatio_MASK 0xff0000
+#define DPM_TABLE_230__MemoryLevel_2_StrobeRatio__SHIFT 0x10
+#define DPM_TABLE_230__MemoryLevel_2_StrobeEnable_MASK 0xff000000
+#define DPM_TABLE_230__MemoryLevel_2_StrobeEnable__SHIFT 0x18
+#define DPM_TABLE_231__MemoryLevel_2_padding_MASK 0xff
+#define DPM_TABLE_231__MemoryLevel_2_padding__SHIFT 0x0
+#define DPM_TABLE_231__MemoryLevel_2_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_231__MemoryLevel_2_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_231__MemoryLevel_2_DownHyst_MASK 0xff0000
+#define DPM_TABLE_231__MemoryLevel_2_DownHyst__SHIFT 0x10
+#define DPM_TABLE_231__MemoryLevel_2_UpHyst_MASK 0xff000000
+#define DPM_TABLE_231__MemoryLevel_2_UpHyst__SHIFT 0x18
+#define DPM_TABLE_232__MemoryLevel_2_padding1_MASK 0xff
+#define DPM_TABLE_232__MemoryLevel_2_padding1__SHIFT 0x0
+#define DPM_TABLE_232__MemoryLevel_2_DisplayWatermark_MASK 0xff00
+#define DPM_TABLE_232__MemoryLevel_2_DisplayWatermark__SHIFT 0x8
+#define DPM_TABLE_232__MemoryLevel_2_ActivityLevel_MASK 0xffff0000
+#define DPM_TABLE_232__MemoryLevel_2_ActivityLevel__SHIFT 0x10
+#define DPM_TABLE_233__MemoryLevel_2_MpllFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_233__MemoryLevel_2_MpllFuncCntl__SHIFT 0x0
+#define DPM_TABLE_234__MemoryLevel_2_MpllFuncCntl_1_MASK 0xffffffff
+#define DPM_TABLE_234__MemoryLevel_2_MpllFuncCntl_1__SHIFT 0x0
+#define DPM_TABLE_235__MemoryLevel_2_MpllFuncCntl_2_MASK 0xffffffff
+#define DPM_TABLE_235__MemoryLevel_2_MpllFuncCntl_2__SHIFT 0x0
+#define DPM_TABLE_236__MemoryLevel_2_MpllAdFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_236__MemoryLevel_2_MpllAdFuncCntl__SHIFT 0x0
+#define DPM_TABLE_237__MemoryLevel_2_MpllDqFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_237__MemoryLevel_2_MpllDqFuncCntl__SHIFT 0x0
+#define DPM_TABLE_238__MemoryLevel_2_MclkPwrmgtCntl_MASK 0xffffffff
+#define DPM_TABLE_238__MemoryLevel_2_MclkPwrmgtCntl__SHIFT 0x0
+#define DPM_TABLE_239__MemoryLevel_2_DllCntl_MASK 0xffffffff
+#define DPM_TABLE_239__MemoryLevel_2_DllCntl__SHIFT 0x0
+#define DPM_TABLE_240__MemoryLevel_2_MpllSs1_MASK 0xffffffff
+#define DPM_TABLE_240__MemoryLevel_2_MpllSs1__SHIFT 0x0
+#define DPM_TABLE_241__MemoryLevel_2_MpllSs2_MASK 0xffffffff
+#define DPM_TABLE_241__MemoryLevel_2_MpllSs2__SHIFT 0x0
+#define DPM_TABLE_242__MemoryLevel_3_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_242__MemoryLevel_3_MinVddc__SHIFT 0x0
+#define DPM_TABLE_243__MemoryLevel_3_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_243__MemoryLevel_3_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_244__MemoryLevel_3_MinVddci_MASK 0xffffffff
+#define DPM_TABLE_244__MemoryLevel_3_MinVddci__SHIFT 0x0
+#define DPM_TABLE_245__MemoryLevel_3_MinMvdd_MASK 0xffffffff
+#define DPM_TABLE_245__MemoryLevel_3_MinMvdd__SHIFT 0x0
+#define DPM_TABLE_246__MemoryLevel_3_MclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_246__MemoryLevel_3_MclkFrequency__SHIFT 0x0
+#define DPM_TABLE_247__MemoryLevel_3_StutterEnable_MASK 0xff
+#define DPM_TABLE_247__MemoryLevel_3_StutterEnable__SHIFT 0x0
+#define DPM_TABLE_247__MemoryLevel_3_RttEnable_MASK 0xff00
+#define DPM_TABLE_247__MemoryLevel_3_RttEnable__SHIFT 0x8
+#define DPM_TABLE_247__MemoryLevel_3_EdcWriteEnable_MASK 0xff0000
+#define DPM_TABLE_247__MemoryLevel_3_EdcWriteEnable__SHIFT 0x10
+#define DPM_TABLE_247__MemoryLevel_3_EdcReadEnable_MASK 0xff000000
+#define DPM_TABLE_247__MemoryLevel_3_EdcReadEnable__SHIFT 0x18
+#define DPM_TABLE_248__MemoryLevel_3_EnabledForActivity_MASK 0xff
+#define DPM_TABLE_248__MemoryLevel_3_EnabledForActivity__SHIFT 0x0
+#define DPM_TABLE_248__MemoryLevel_3_EnabledForThrottle_MASK 0xff00
+#define DPM_TABLE_248__MemoryLevel_3_EnabledForThrottle__SHIFT 0x8
+#define DPM_TABLE_248__MemoryLevel_3_StrobeRatio_MASK 0xff0000
+#define DPM_TABLE_248__MemoryLevel_3_StrobeRatio__SHIFT 0x10
+#define DPM_TABLE_248__MemoryLevel_3_StrobeEnable_MASK 0xff000000
+#define DPM_TABLE_248__MemoryLevel_3_StrobeEnable__SHIFT 0x18
+#define DPM_TABLE_249__MemoryLevel_3_padding_MASK 0xff
+#define DPM_TABLE_249__MemoryLevel_3_padding__SHIFT 0x0
+#define DPM_TABLE_249__MemoryLevel_3_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_249__MemoryLevel_3_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_249__MemoryLevel_3_DownHyst_MASK 0xff0000
+#define DPM_TABLE_249__MemoryLevel_3_DownHyst__SHIFT 0x10
+#define DPM_TABLE_249__MemoryLevel_3_UpHyst_MASK 0xff000000
+#define DPM_TABLE_249__MemoryLevel_3_UpHyst__SHIFT 0x18
+#define DPM_TABLE_250__MemoryLevel_3_padding1_MASK 0xff
+#define DPM_TABLE_250__MemoryLevel_3_padding1__SHIFT 0x0
+#define DPM_TABLE_250__MemoryLevel_3_DisplayWatermark_MASK 0xff00
+#define DPM_TABLE_250__MemoryLevel_3_DisplayWatermark__SHIFT 0x8
+#define DPM_TABLE_250__MemoryLevel_3_ActivityLevel_MASK 0xffff0000
+#define DPM_TABLE_250__MemoryLevel_3_ActivityLevel__SHIFT 0x10
+#define DPM_TABLE_251__MemoryLevel_3_MpllFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_251__MemoryLevel_3_MpllFuncCntl__SHIFT 0x0
+#define DPM_TABLE_252__MemoryLevel_3_MpllFuncCntl_1_MASK 0xffffffff
+#define DPM_TABLE_252__MemoryLevel_3_MpllFuncCntl_1__SHIFT 0x0
+#define DPM_TABLE_253__MemoryLevel_3_MpllFuncCntl_2_MASK 0xffffffff
+#define DPM_TABLE_253__MemoryLevel_3_MpllFuncCntl_2__SHIFT 0x0
+#define DPM_TABLE_254__MemoryLevel_3_MpllAdFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_254__MemoryLevel_3_MpllAdFuncCntl__SHIFT 0x0
+#define DPM_TABLE_255__MemoryLevel_3_MpllDqFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_255__MemoryLevel_3_MpllDqFuncCntl__SHIFT 0x0
+#define DPM_TABLE_256__MemoryLevel_3_MclkPwrmgtCntl_MASK 0xffffffff
+#define DPM_TABLE_256__MemoryLevel_3_MclkPwrmgtCntl__SHIFT 0x0
+#define DPM_TABLE_257__MemoryLevel_3_DllCntl_MASK 0xffffffff
+#define DPM_TABLE_257__MemoryLevel_3_DllCntl__SHIFT 0x0
+#define DPM_TABLE_258__MemoryLevel_3_MpllSs1_MASK 0xffffffff
+#define DPM_TABLE_258__MemoryLevel_3_MpllSs1__SHIFT 0x0
+#define DPM_TABLE_259__MemoryLevel_3_MpllSs2_MASK 0xffffffff
+#define DPM_TABLE_259__MemoryLevel_3_MpllSs2__SHIFT 0x0
+#define DPM_TABLE_260__LinkLevel_0_SPC_MASK 0xff
+#define DPM_TABLE_260__LinkLevel_0_SPC__SHIFT 0x0
+#define DPM_TABLE_260__LinkLevel_0_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_260__LinkLevel_0_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_260__LinkLevel_0_PcieLaneCount_MASK 0xff0000
+#define DPM_TABLE_260__LinkLevel_0_PcieLaneCount__SHIFT 0x10
+#define DPM_TABLE_260__LinkLevel_0_PcieGenSpeed_MASK 0xff000000
+#define DPM_TABLE_260__LinkLevel_0_PcieGenSpeed__SHIFT 0x18
+#define DPM_TABLE_261__LinkLevel_0_DownThreshold_MASK 0xffffffff
+#define DPM_TABLE_261__LinkLevel_0_DownThreshold__SHIFT 0x0
+#define DPM_TABLE_262__LinkLevel_0_UpThreshold_MASK 0xffffffff
+#define DPM_TABLE_262__LinkLevel_0_UpThreshold__SHIFT 0x0
+#define DPM_TABLE_263__LinkLevel_0_Reserved_MASK 0xffffffff
+#define DPM_TABLE_263__LinkLevel_0_Reserved__SHIFT 0x0
+#define DPM_TABLE_264__LinkLevel_1_SPC_MASK 0xff
+#define DPM_TABLE_264__LinkLevel_1_SPC__SHIFT 0x0
+#define DPM_TABLE_264__LinkLevel_1_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_264__LinkLevel_1_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_264__LinkLevel_1_PcieLaneCount_MASK 0xff0000
+#define DPM_TABLE_264__LinkLevel_1_PcieLaneCount__SHIFT 0x10
+#define DPM_TABLE_264__LinkLevel_1_PcieGenSpeed_MASK 0xff000000
+#define DPM_TABLE_264__LinkLevel_1_PcieGenSpeed__SHIFT 0x18
+#define DPM_TABLE_265__LinkLevel_1_DownThreshold_MASK 0xffffffff
+#define DPM_TABLE_265__LinkLevel_1_DownThreshold__SHIFT 0x0
+#define DPM_TABLE_266__LinkLevel_1_UpThreshold_MASK 0xffffffff
+#define DPM_TABLE_266__LinkLevel_1_UpThreshold__SHIFT 0x0
+#define DPM_TABLE_267__LinkLevel_1_Reserved_MASK 0xffffffff
+#define DPM_TABLE_267__LinkLevel_1_Reserved__SHIFT 0x0
+#define DPM_TABLE_268__LinkLevel_2_SPC_MASK 0xff
+#define DPM_TABLE_268__LinkLevel_2_SPC__SHIFT 0x0
+#define DPM_TABLE_268__LinkLevel_2_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_268__LinkLevel_2_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_268__LinkLevel_2_PcieLaneCount_MASK 0xff0000
+#define DPM_TABLE_268__LinkLevel_2_PcieLaneCount__SHIFT 0x10
+#define DPM_TABLE_268__LinkLevel_2_PcieGenSpeed_MASK 0xff000000
+#define DPM_TABLE_268__LinkLevel_2_PcieGenSpeed__SHIFT 0x18
+#define DPM_TABLE_269__LinkLevel_2_DownThreshold_MASK 0xffffffff
+#define DPM_TABLE_269__LinkLevel_2_DownThreshold__SHIFT 0x0
+#define DPM_TABLE_270__LinkLevel_2_UpThreshold_MASK 0xffffffff
+#define DPM_TABLE_270__LinkLevel_2_UpThreshold__SHIFT 0x0
+#define DPM_TABLE_271__LinkLevel_2_Reserved_MASK 0xffffffff
+#define DPM_TABLE_271__LinkLevel_2_Reserved__SHIFT 0x0
+#define DPM_TABLE_272__LinkLevel_3_SPC_MASK 0xff
+#define DPM_TABLE_272__LinkLevel_3_SPC__SHIFT 0x0
+#define DPM_TABLE_272__LinkLevel_3_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_272__LinkLevel_3_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_272__LinkLevel_3_PcieLaneCount_MASK 0xff0000
+#define DPM_TABLE_272__LinkLevel_3_PcieLaneCount__SHIFT 0x10
+#define DPM_TABLE_272__LinkLevel_3_PcieGenSpeed_MASK 0xff000000
+#define DPM_TABLE_272__LinkLevel_3_PcieGenSpeed__SHIFT 0x18
+#define DPM_TABLE_273__LinkLevel_3_DownThreshold_MASK 0xffffffff
+#define DPM_TABLE_273__LinkLevel_3_DownThreshold__SHIFT 0x0
+#define DPM_TABLE_274__LinkLevel_3_UpThreshold_MASK 0xffffffff
+#define DPM_TABLE_274__LinkLevel_3_UpThreshold__SHIFT 0x0
+#define DPM_TABLE_275__LinkLevel_3_Reserved_MASK 0xffffffff
+#define DPM_TABLE_275__LinkLevel_3_Reserved__SHIFT 0x0
+#define DPM_TABLE_276__LinkLevel_4_SPC_MASK 0xff
+#define DPM_TABLE_276__LinkLevel_4_SPC__SHIFT 0x0
+#define DPM_TABLE_276__LinkLevel_4_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_276__LinkLevel_4_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_276__LinkLevel_4_PcieLaneCount_MASK 0xff0000
+#define DPM_TABLE_276__LinkLevel_4_PcieLaneCount__SHIFT 0x10
+#define DPM_TABLE_276__LinkLevel_4_PcieGenSpeed_MASK 0xff000000
+#define DPM_TABLE_276__LinkLevel_4_PcieGenSpeed__SHIFT 0x18
+#define DPM_TABLE_277__LinkLevel_4_DownThreshold_MASK 0xffffffff
+#define DPM_TABLE_277__LinkLevel_4_DownThreshold__SHIFT 0x0
+#define DPM_TABLE_278__LinkLevel_4_UpThreshold_MASK 0xffffffff
+#define DPM_TABLE_278__LinkLevel_4_UpThreshold__SHIFT 0x0
+#define DPM_TABLE_279__LinkLevel_4_Reserved_MASK 0xffffffff
+#define DPM_TABLE_279__LinkLevel_4_Reserved__SHIFT 0x0
+#define DPM_TABLE_280__LinkLevel_5_SPC_MASK 0xff
+#define DPM_TABLE_280__LinkLevel_5_SPC__SHIFT 0x0
+#define DPM_TABLE_280__LinkLevel_5_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_280__LinkLevel_5_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_280__LinkLevel_5_PcieLaneCount_MASK 0xff0000
+#define DPM_TABLE_280__LinkLevel_5_PcieLaneCount__SHIFT 0x10
+#define DPM_TABLE_280__LinkLevel_5_PcieGenSpeed_MASK 0xff000000
+#define DPM_TABLE_280__LinkLevel_5_PcieGenSpeed__SHIFT 0x18
+#define DPM_TABLE_281__LinkLevel_5_DownThreshold_MASK 0xffffffff
+#define DPM_TABLE_281__LinkLevel_5_DownThreshold__SHIFT 0x0
+#define DPM_TABLE_282__LinkLevel_5_UpThreshold_MASK 0xffffffff
+#define DPM_TABLE_282__LinkLevel_5_UpThreshold__SHIFT 0x0
+#define DPM_TABLE_283__LinkLevel_5_Reserved_MASK 0xffffffff
+#define DPM_TABLE_283__LinkLevel_5_Reserved__SHIFT 0x0
+#define DPM_TABLE_284__LinkLevel_6_SPC_MASK 0xff
+#define DPM_TABLE_284__LinkLevel_6_SPC__SHIFT 0x0
+#define DPM_TABLE_284__LinkLevel_6_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_284__LinkLevel_6_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_284__LinkLevel_6_PcieLaneCount_MASK 0xff0000
+#define DPM_TABLE_284__LinkLevel_6_PcieLaneCount__SHIFT 0x10
+#define DPM_TABLE_284__LinkLevel_6_PcieGenSpeed_MASK 0xff000000
+#define DPM_TABLE_284__LinkLevel_6_PcieGenSpeed__SHIFT 0x18
+#define DPM_TABLE_285__LinkLevel_6_DownThreshold_MASK 0xffffffff
+#define DPM_TABLE_285__LinkLevel_6_DownThreshold__SHIFT 0x0
+#define DPM_TABLE_286__LinkLevel_6_UpThreshold_MASK 0xffffffff
+#define DPM_TABLE_286__LinkLevel_6_UpThreshold__SHIFT 0x0
+#define DPM_TABLE_287__LinkLevel_6_Reserved_MASK 0xffffffff
+#define DPM_TABLE_287__LinkLevel_6_Reserved__SHIFT 0x0
+#define DPM_TABLE_288__LinkLevel_7_SPC_MASK 0xff
+#define DPM_TABLE_288__LinkLevel_7_SPC__SHIFT 0x0
+#define DPM_TABLE_288__LinkLevel_7_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_288__LinkLevel_7_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_288__LinkLevel_7_PcieLaneCount_MASK 0xff0000
+#define DPM_TABLE_288__LinkLevel_7_PcieLaneCount__SHIFT 0x10
+#define DPM_TABLE_288__LinkLevel_7_PcieGenSpeed_MASK 0xff000000
+#define DPM_TABLE_288__LinkLevel_7_PcieGenSpeed__SHIFT 0x18
+#define DPM_TABLE_289__LinkLevel_7_DownThreshold_MASK 0xffffffff
+#define DPM_TABLE_289__LinkLevel_7_DownThreshold__SHIFT 0x0
+#define DPM_TABLE_290__LinkLevel_7_UpThreshold_MASK 0xffffffff
+#define DPM_TABLE_290__LinkLevel_7_UpThreshold__SHIFT 0x0
+#define DPM_TABLE_291__LinkLevel_7_Reserved_MASK 0xffffffff
+#define DPM_TABLE_291__LinkLevel_7_Reserved__SHIFT 0x0
+#define DPM_TABLE_292__ACPILevel_Flags_MASK 0xffffffff
+#define DPM_TABLE_292__ACPILevel_Flags__SHIFT 0x0
+#define DPM_TABLE_293__ACPILevel_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_293__ACPILevel_MinVddc__SHIFT 0x0
+#define DPM_TABLE_294__ACPILevel_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_294__ACPILevel_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_295__ACPILevel_SclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_295__ACPILevel_SclkFrequency__SHIFT 0x0
+#define DPM_TABLE_296__ACPILevel_padding_MASK 0xff
+#define DPM_TABLE_296__ACPILevel_padding__SHIFT 0x0
+#define DPM_TABLE_296__ACPILevel_DeepSleepDivId_MASK 0xff00
+#define DPM_TABLE_296__ACPILevel_DeepSleepDivId__SHIFT 0x8
+#define DPM_TABLE_296__ACPILevel_DisplayWatermark_MASK 0xff0000
+#define DPM_TABLE_296__ACPILevel_DisplayWatermark__SHIFT 0x10
+#define DPM_TABLE_296__ACPILevel_SclkDid_MASK 0xff000000
+#define DPM_TABLE_296__ACPILevel_SclkDid__SHIFT 0x18
+#define DPM_TABLE_297__ACPILevel_CgSpllFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_297__ACPILevel_CgSpllFuncCntl__SHIFT 0x0
+#define DPM_TABLE_298__ACPILevel_CgSpllFuncCntl2_MASK 0xffffffff
+#define DPM_TABLE_298__ACPILevel_CgSpllFuncCntl2__SHIFT 0x0
+#define DPM_TABLE_299__ACPILevel_CgSpllFuncCntl3_MASK 0xffffffff
+#define DPM_TABLE_299__ACPILevel_CgSpllFuncCntl3__SHIFT 0x0
+#define DPM_TABLE_300__ACPILevel_CgSpllFuncCntl4_MASK 0xffffffff
+#define DPM_TABLE_300__ACPILevel_CgSpllFuncCntl4__SHIFT 0x0
+#define DPM_TABLE_301__ACPILevel_SpllSpreadSpectrum_MASK 0xffffffff
+#define DPM_TABLE_301__ACPILevel_SpllSpreadSpectrum__SHIFT 0x0
+#define DPM_TABLE_302__ACPILevel_SpllSpreadSpectrum2_MASK 0xffffffff
+#define DPM_TABLE_302__ACPILevel_SpllSpreadSpectrum2__SHIFT 0x0
+#define DPM_TABLE_303__ACPILevel_CcPwrDynRm_MASK 0xffffffff
+#define DPM_TABLE_303__ACPILevel_CcPwrDynRm__SHIFT 0x0
+#define DPM_TABLE_304__ACPILevel_CcPwrDynRm1_MASK 0xffffffff
+#define DPM_TABLE_304__ACPILevel_CcPwrDynRm1__SHIFT 0x0
+#define DPM_TABLE_305__SclkStepSize_MASK 0xffffffff
+#define DPM_TABLE_305__SclkStepSize__SHIFT 0x0
+#define DPM_TABLE_306__Smio_0_MASK 0xffffffff
+#define DPM_TABLE_306__Smio_0__SHIFT 0x0
+#define DPM_TABLE_307__Smio_1_MASK 0xffffffff
+#define DPM_TABLE_307__Smio_1__SHIFT 0x0
+#define DPM_TABLE_308__Smio_2_MASK 0xffffffff
+#define DPM_TABLE_308__Smio_2__SHIFT 0x0
+#define DPM_TABLE_309__Smio_3_MASK 0xffffffff
+#define DPM_TABLE_309__Smio_3__SHIFT 0x0
+#define DPM_TABLE_310__Smio_4_MASK 0xffffffff
+#define DPM_TABLE_310__Smio_4__SHIFT 0x0
+#define DPM_TABLE_311__Smio_5_MASK 0xffffffff
+#define DPM_TABLE_311__Smio_5__SHIFT 0x0
+#define DPM_TABLE_312__Smio_6_MASK 0xffffffff
+#define DPM_TABLE_312__Smio_6__SHIFT 0x0
+#define DPM_TABLE_313__Smio_7_MASK 0xffffffff
+#define DPM_TABLE_313__Smio_7__SHIFT 0x0
+#define DPM_TABLE_314__Smio_8_MASK 0xffffffff
+#define DPM_TABLE_314__Smio_8__SHIFT 0x0
+#define DPM_TABLE_315__Smio_9_MASK 0xffffffff
+#define DPM_TABLE_315__Smio_9__SHIFT 0x0
+#define DPM_TABLE_316__Smio_10_MASK 0xffffffff
+#define DPM_TABLE_316__Smio_10__SHIFT 0x0
+#define DPM_TABLE_317__Smio_11_MASK 0xffffffff
+#define DPM_TABLE_317__Smio_11__SHIFT 0x0
+#define DPM_TABLE_318__Smio_12_MASK 0xffffffff
+#define DPM_TABLE_318__Smio_12__SHIFT 0x0
+#define DPM_TABLE_319__Smio_13_MASK 0xffffffff
+#define DPM_TABLE_319__Smio_13__SHIFT 0x0
+#define DPM_TABLE_320__Smio_14_MASK 0xffffffff
+#define DPM_TABLE_320__Smio_14__SHIFT 0x0
+#define DPM_TABLE_321__Smio_15_MASK 0xffffffff
+#define DPM_TABLE_321__Smio_15__SHIFT 0x0
+#define DPM_TABLE_322__Smio_16_MASK 0xffffffff
+#define DPM_TABLE_322__Smio_16__SHIFT 0x0
+#define DPM_TABLE_323__Smio_17_MASK 0xffffffff
+#define DPM_TABLE_323__Smio_17__SHIFT 0x0
+#define DPM_TABLE_324__Smio_18_MASK 0xffffffff
+#define DPM_TABLE_324__Smio_18__SHIFT 0x0
+#define DPM_TABLE_325__Smio_19_MASK 0xffffffff
+#define DPM_TABLE_325__Smio_19__SHIFT 0x0
+#define DPM_TABLE_326__Smio_20_MASK 0xffffffff
+#define DPM_TABLE_326__Smio_20__SHIFT 0x0
+#define DPM_TABLE_327__Smio_21_MASK 0xffffffff
+#define DPM_TABLE_327__Smio_21__SHIFT 0x0
+#define DPM_TABLE_328__Smio_22_MASK 0xffffffff
+#define DPM_TABLE_328__Smio_22__SHIFT 0x0
+#define DPM_TABLE_329__Smio_23_MASK 0xffffffff
+#define DPM_TABLE_329__Smio_23__SHIFT 0x0
+#define DPM_TABLE_330__Smio_24_MASK 0xffffffff
+#define DPM_TABLE_330__Smio_24__SHIFT 0x0
+#define DPM_TABLE_331__Smio_25_MASK 0xffffffff
+#define DPM_TABLE_331__Smio_25__SHIFT 0x0
+#define DPM_TABLE_332__Smio_26_MASK 0xffffffff
+#define DPM_TABLE_332__Smio_26__SHIFT 0x0
+#define DPM_TABLE_333__Smio_27_MASK 0xffffffff
+#define DPM_TABLE_333__Smio_27__SHIFT 0x0
+#define DPM_TABLE_334__Smio_28_MASK 0xffffffff
+#define DPM_TABLE_334__Smio_28__SHIFT 0x0
+#define DPM_TABLE_335__Smio_29_MASK 0xffffffff
+#define DPM_TABLE_335__Smio_29__SHIFT 0x0
+#define DPM_TABLE_336__Smio_30_MASK 0xffffffff
+#define DPM_TABLE_336__Smio_30__SHIFT 0x0
+#define DPM_TABLE_337__Smio_31_MASK 0xffffffff
+#define DPM_TABLE_337__Smio_31__SHIFT 0x0
+#define DPM_TABLE_338__GraphicsInterval_MASK 0xff
+#define DPM_TABLE_338__GraphicsInterval__SHIFT 0x0
+#define DPM_TABLE_338__GraphicsThermThrottleEnable_MASK 0xff00
+#define DPM_TABLE_338__GraphicsThermThrottleEnable__SHIFT 0x8
+#define DPM_TABLE_338__GraphicsVoltageChangeEnable_MASK 0xff0000
+#define DPM_TABLE_338__GraphicsVoltageChangeEnable__SHIFT 0x10
+#define DPM_TABLE_338__GraphicsBootLevel_MASK 0xff000000
+#define DPM_TABLE_338__GraphicsBootLevel__SHIFT 0x18
+#define DPM_TABLE_339__TemperatureLimitHigh_MASK 0xffff
+#define DPM_TABLE_339__TemperatureLimitHigh__SHIFT 0x0
+#define DPM_TABLE_339__ThermalInterval_MASK 0xff0000
+#define DPM_TABLE_339__ThermalInterval__SHIFT 0x10
+#define DPM_TABLE_339__VoltageInterval_MASK 0xff000000
+#define DPM_TABLE_339__VoltageInterval__SHIFT 0x18
+#define DPM_TABLE_340__MemoryVoltageChangeEnable_MASK 0xff
+#define DPM_TABLE_340__MemoryVoltageChangeEnable__SHIFT 0x0
+#define DPM_TABLE_340__MemoryBootLevel_MASK 0xff00
+#define DPM_TABLE_340__MemoryBootLevel__SHIFT 0x8
+#define DPM_TABLE_340__TemperatureLimitLow_MASK 0xffff0000
+#define DPM_TABLE_340__TemperatureLimitLow__SHIFT 0x10
+#define DPM_TABLE_341__padding2_MASK 0xff
+#define DPM_TABLE_341__padding2__SHIFT 0x0
+#define DPM_TABLE_341__MergedVddci_MASK 0xff00
+#define DPM_TABLE_341__MergedVddci__SHIFT 0x8
+#define DPM_TABLE_341__MemoryThermThrottleEnable_MASK 0xff0000
+#define DPM_TABLE_341__MemoryThermThrottleEnable__SHIFT 0x10
+#define DPM_TABLE_341__MemoryInterval_MASK 0xff000000
+#define DPM_TABLE_341__MemoryInterval__SHIFT 0x18
+#define DPM_TABLE_342__PhaseResponseTime_MASK 0xffff
+#define DPM_TABLE_342__PhaseResponseTime__SHIFT 0x0
+#define DPM_TABLE_342__VoltageResponseTime_MASK 0xffff0000
+#define DPM_TABLE_342__VoltageResponseTime__SHIFT 0x10
+#define DPM_TABLE_343__DTEMode_MASK 0xff
+#define DPM_TABLE_343__DTEMode__SHIFT 0x0
+#define DPM_TABLE_343__DTEInterval_MASK 0xff00
+#define DPM_TABLE_343__DTEInterval__SHIFT 0x8
+#define DPM_TABLE_343__PCIeGenInterval_MASK 0xff0000
+#define DPM_TABLE_343__PCIeGenInterval__SHIFT 0x10
+#define DPM_TABLE_343__PCIeBootLinkLevel_MASK 0xff000000
+#define DPM_TABLE_343__PCIeBootLinkLevel__SHIFT 0x18
+#define DPM_TABLE_344__ThermGpio_MASK 0xff
+#define DPM_TABLE_344__ThermGpio__SHIFT 0x0
+#define DPM_TABLE_344__AcDcGpio_MASK 0xff00
+#define DPM_TABLE_344__AcDcGpio__SHIFT 0x8
+#define DPM_TABLE_344__VRHotGpio_MASK 0xff0000
+#define DPM_TABLE_344__VRHotGpio__SHIFT 0x10
+#define DPM_TABLE_344__SVI2Enable_MASK 0xff000000
+#define DPM_TABLE_344__SVI2Enable__SHIFT 0x18
+#define DPM_TABLE_345__DisplayCac_MASK 0xffffffff
+#define DPM_TABLE_345__DisplayCac__SHIFT 0x0
+#define DPM_TABLE_346__NomPwr_MASK 0xffff
+#define DPM_TABLE_346__NomPwr__SHIFT 0x0
+#define DPM_TABLE_346__MaxPwr_MASK 0xffff0000
+#define DPM_TABLE_346__MaxPwr__SHIFT 0x10
+#define DPM_TABLE_347__FpsLowThreshold_MASK 0xffff
+#define DPM_TABLE_347__FpsLowThreshold__SHIFT 0x0
+#define DPM_TABLE_347__FpsHighThreshold_MASK 0xffff0000
+#define DPM_TABLE_347__FpsHighThreshold__SHIFT 0x10
+#define DPM_TABLE_348__BAPMTI_R_0_1_0_MASK 0xffff
+#define DPM_TABLE_348__BAPMTI_R_0_1_0__SHIFT 0x0
+#define DPM_TABLE_348__BAPMTI_R_0_0_0_MASK 0xffff0000
+#define DPM_TABLE_348__BAPMTI_R_0_0_0__SHIFT 0x10
+#define DPM_TABLE_349__BAPMTI_R_1_0_0_MASK 0xffff
+#define DPM_TABLE_349__BAPMTI_R_1_0_0__SHIFT 0x0
+#define DPM_TABLE_349__BAPMTI_R_0_2_0_MASK 0xffff0000
+#define DPM_TABLE_349__BAPMTI_R_0_2_0__SHIFT 0x10
+#define DPM_TABLE_350__BAPMTI_R_1_2_0_MASK 0xffff
+#define DPM_TABLE_350__BAPMTI_R_1_2_0__SHIFT 0x0
+#define DPM_TABLE_350__BAPMTI_R_1_1_0_MASK 0xffff0000
+#define DPM_TABLE_350__BAPMTI_R_1_1_0__SHIFT 0x10
+#define DPM_TABLE_351__BAPMTI_R_2_1_0_MASK 0xffff
+#define DPM_TABLE_351__BAPMTI_R_2_1_0__SHIFT 0x0
+#define DPM_TABLE_351__BAPMTI_R_2_0_0_MASK 0xffff0000
+#define DPM_TABLE_351__BAPMTI_R_2_0_0__SHIFT 0x10
+#define DPM_TABLE_352__BAPMTI_R_3_0_0_MASK 0xffff
+#define DPM_TABLE_352__BAPMTI_R_3_0_0__SHIFT 0x0
+#define DPM_TABLE_352__BAPMTI_R_2_2_0_MASK 0xffff0000
+#define DPM_TABLE_352__BAPMTI_R_2_2_0__SHIFT 0x10
+#define DPM_TABLE_353__BAPMTI_R_3_2_0_MASK 0xffff
+#define DPM_TABLE_353__BAPMTI_R_3_2_0__SHIFT 0x0
+#define DPM_TABLE_353__BAPMTI_R_3_1_0_MASK 0xffff0000
+#define DPM_TABLE_353__BAPMTI_R_3_1_0__SHIFT 0x10
+#define DPM_TABLE_354__BAPMTI_R_4_1_0_MASK 0xffff
+#define DPM_TABLE_354__BAPMTI_R_4_1_0__SHIFT 0x0
+#define DPM_TABLE_354__BAPMTI_R_4_0_0_MASK 0xffff0000
+#define DPM_TABLE_354__BAPMTI_R_4_0_0__SHIFT 0x10
+#define DPM_TABLE_355__BAPMTI_RC_0_0_0_MASK 0xffff
+#define DPM_TABLE_355__BAPMTI_RC_0_0_0__SHIFT 0x0
+#define DPM_TABLE_355__BAPMTI_R_4_2_0_MASK 0xffff0000
+#define DPM_TABLE_355__BAPMTI_R_4_2_0__SHIFT 0x10
+#define DPM_TABLE_356__BAPMTI_RC_0_2_0_MASK 0xffff
+#define DPM_TABLE_356__BAPMTI_RC_0_2_0__SHIFT 0x0
+#define DPM_TABLE_356__BAPMTI_RC_0_1_0_MASK 0xffff0000
+#define DPM_TABLE_356__BAPMTI_RC_0_1_0__SHIFT 0x10
+#define DPM_TABLE_357__BAPMTI_RC_1_1_0_MASK 0xffff
+#define DPM_TABLE_357__BAPMTI_RC_1_1_0__SHIFT 0x0
+#define DPM_TABLE_357__BAPMTI_RC_1_0_0_MASK 0xffff0000
+#define DPM_TABLE_357__BAPMTI_RC_1_0_0__SHIFT 0x10
+#define DPM_TABLE_358__BAPMTI_RC_2_0_0_MASK 0xffff
+#define DPM_TABLE_358__BAPMTI_RC_2_0_0__SHIFT 0x0
+#define DPM_TABLE_358__BAPMTI_RC_1_2_0_MASK 0xffff0000
+#define DPM_TABLE_358__BAPMTI_RC_1_2_0__SHIFT 0x10
+#define DPM_TABLE_359__BAPMTI_RC_2_2_0_MASK 0xffff
+#define DPM_TABLE_359__BAPMTI_RC_2_2_0__SHIFT 0x0
+#define DPM_TABLE_359__BAPMTI_RC_2_1_0_MASK 0xffff0000
+#define DPM_TABLE_359__BAPMTI_RC_2_1_0__SHIFT 0x10
+#define DPM_TABLE_360__BAPMTI_RC_3_1_0_MASK 0xffff
+#define DPM_TABLE_360__BAPMTI_RC_3_1_0__SHIFT 0x0
+#define DPM_TABLE_360__BAPMTI_RC_3_0_0_MASK 0xffff0000
+#define DPM_TABLE_360__BAPMTI_RC_3_0_0__SHIFT 0x10
+#define DPM_TABLE_361__BAPMTI_RC_4_0_0_MASK 0xffff
+#define DPM_TABLE_361__BAPMTI_RC_4_0_0__SHIFT 0x0
+#define DPM_TABLE_361__BAPMTI_RC_3_2_0_MASK 0xffff0000
+#define DPM_TABLE_361__BAPMTI_RC_3_2_0__SHIFT 0x10
+#define DPM_TABLE_362__BAPMTI_RC_4_2_0_MASK 0xffff
+#define DPM_TABLE_362__BAPMTI_RC_4_2_0__SHIFT 0x0
+#define DPM_TABLE_362__BAPMTI_RC_4_1_0_MASK 0xffff0000
+#define DPM_TABLE_362__BAPMTI_RC_4_1_0__SHIFT 0x10
+#define DPM_TABLE_363__GpuTjHyst_MASK 0xff
+#define DPM_TABLE_363__GpuTjHyst__SHIFT 0x0
+#define DPM_TABLE_363__GpuTjMax_MASK 0xff00
+#define DPM_TABLE_363__GpuTjMax__SHIFT 0x8
+#define DPM_TABLE_363__DTETjOffset_MASK 0xff0000
+#define DPM_TABLE_363__DTETjOffset__SHIFT 0x10
+#define DPM_TABLE_363__DTEAmbientTempBase_MASK 0xff000000
+#define DPM_TABLE_363__DTEAmbientTempBase__SHIFT 0x18
+#define DPM_TABLE_364__BootVddci_MASK 0xffff
+#define DPM_TABLE_364__BootVddci__SHIFT 0x0
+#define DPM_TABLE_364__BootVddc_MASK 0xffff0000
+#define DPM_TABLE_364__BootVddc__SHIFT 0x10
+#define DPM_TABLE_365__padding_MASK 0xffff
+#define DPM_TABLE_365__padding__SHIFT 0x0
+#define DPM_TABLE_365__BootMVdd_MASK 0xffff0000
+#define DPM_TABLE_365__BootMVdd__SHIFT 0x10
+#define DPM_TABLE_366__BAPM_TEMP_GRADIENT_MASK 0xffffffff
+#define DPM_TABLE_366__BAPM_TEMP_GRADIENT__SHIFT 0x0
+#define DPM_TABLE_367__LowSclkInterruptThreshold_MASK 0xffffffff
+#define DPM_TABLE_367__LowSclkInterruptThreshold__SHIFT 0x0
+#define DPM_TABLE_368__VddGfxReChkWait_MASK 0xffffffff
+#define DPM_TABLE_368__VddGfxReChkWait__SHIFT 0x0
+#define DPM_TABLE_369__PPM_TemperatureLimit_MASK 0xffff
+#define DPM_TABLE_369__PPM_TemperatureLimit__SHIFT 0x0
+#define DPM_TABLE_369__PPM_PkgPwrLimit_MASK 0xffff0000
+#define DPM_TABLE_369__PPM_PkgPwrLimit__SHIFT 0x10
+#define DPM_TABLE_370__TargetTdp_MASK 0xffff
+#define DPM_TABLE_370__TargetTdp__SHIFT 0x0
+#define DPM_TABLE_370__DefaultTdp_MASK 0xffff0000
+#define DPM_TABLE_370__DefaultTdp__SHIFT 0x10
+#define SOFT_REGISTERS_TABLE_1__RefClockFrequency_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_1__RefClockFrequency__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_2__PmTimerPeriod_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_2__PmTimerPeriod__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_3__FeatureEnables_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_3__FeatureEnables__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_4__PreVBlankGap_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_4__PreVBlankGap__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_5__VBlankTimeout_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_5__VBlankTimeout__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_6__TrainTimeGap_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_6__TrainTimeGap__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_7__MvddSwitchTime_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_7__MvddSwitchTime__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_8__LongestAcpiTrainTime_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_8__LongestAcpiTrainTime__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_9__AcpiDelay_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_9__AcpiDelay__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_10__G5TrainTime_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_10__G5TrainTime__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_11__DelayMpllPwron_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_11__DelayMpllPwron__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_12__VoltageChangeTimeout_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_12__VoltageChangeTimeout__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_13__HandshakeDisables_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_13__HandshakeDisables__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_14__DisplayPhy4Config_MASK 0xff
+#define SOFT_REGISTERS_TABLE_14__DisplayPhy4Config__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_14__DisplayPhy3Config_MASK 0xff00
+#define SOFT_REGISTERS_TABLE_14__DisplayPhy3Config__SHIFT 0x8
+#define SOFT_REGISTERS_TABLE_14__DisplayPhy2Config_MASK 0xff0000
+#define SOFT_REGISTERS_TABLE_14__DisplayPhy2Config__SHIFT 0x10
+#define SOFT_REGISTERS_TABLE_14__DisplayPhy1Config_MASK 0xff000000
+#define SOFT_REGISTERS_TABLE_14__DisplayPhy1Config__SHIFT 0x18
+#define SOFT_REGISTERS_TABLE_15__DisplayPhy8Config_MASK 0xff
+#define SOFT_REGISTERS_TABLE_15__DisplayPhy8Config__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_15__DisplayPhy7Config_MASK 0xff00
+#define SOFT_REGISTERS_TABLE_15__DisplayPhy7Config__SHIFT 0x8
+#define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config_MASK 0xff0000
+#define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config__SHIFT 0x10
+#define SOFT_REGISTERS_TABLE_15__DisplayPhy5Config_MASK 0xff000000
+#define SOFT_REGISTERS_TABLE_15__DisplayPhy5Config__SHIFT 0x18
+#define SOFT_REGISTERS_TABLE_16__AverageGraphicsActivity_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_16__AverageGraphicsActivity__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_17__AverageMemoryActivity_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_17__AverageMemoryActivity__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_18__AverageGioActivity_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_18__AverageGioActivity__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_19__PCIeDpmEnabledLevels_MASK 0xff
+#define SOFT_REGISTERS_TABLE_19__PCIeDpmEnabledLevels__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_19__LClkDpmEnabledLevels_MASK 0xff00
+#define SOFT_REGISTERS_TABLE_19__LClkDpmEnabledLevels__SHIFT 0x8
+#define SOFT_REGISTERS_TABLE_19__MClkDpmEnabledLevels_MASK 0xff0000
+#define SOFT_REGISTERS_TABLE_19__MClkDpmEnabledLevels__SHIFT 0x10
+#define SOFT_REGISTERS_TABLE_19__SClkDpmEnabledLevels_MASK 0xff000000
+#define SOFT_REGISTERS_TABLE_19__SClkDpmEnabledLevels__SHIFT 0x18
+#define SOFT_REGISTERS_TABLE_20__DRAM_LOG_ADDR_H_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_20__DRAM_LOG_ADDR_H__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_21__DRAM_LOG_ADDR_L_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_21__DRAM_LOG_ADDR_L__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_22__DRAM_LOG_PHY_ADDR_H_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_22__DRAM_LOG_PHY_ADDR_H__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_23__DRAM_LOG_PHY_ADDR_L_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_23__DRAM_LOG_PHY_ADDR_L__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_24__DRAM_LOG_BUFF_SIZE_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_24__DRAM_LOG_BUFF_SIZE__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_25__UlvEnterCount_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_25__UlvEnterCount__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_26__UlvTime_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_26__UlvTime__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_27__UcodeLoadStatus_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_27__UcodeLoadStatus__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_28__Reserved_0_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_28__Reserved_0__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_29__Reserved_1_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_29__Reserved_1__SHIFT 0x0
+#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x1
+#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0
+#define FIRMWARE_FLAGS__RESERVED_MASK 0xfffffe
+#define FIRMWARE_FLAGS__RESERVED__SHIFT 0x1
+#define FIRMWARE_FLAGS__TEST_COUNT_MASK 0xff000000
+#define FIRMWARE_FLAGS__TEST_COUNT__SHIFT 0x18
+#define TDC_STATUS__VDD_Boost_MASK 0xff
+#define TDC_STATUS__VDD_Boost__SHIFT 0x0
+#define TDC_STATUS__VDD_Throttle_MASK 0xff00
+#define TDC_STATUS__VDD_Throttle__SHIFT 0x8
+#define TDC_STATUS__VDDC_Boost_MASK 0xff0000
+#define TDC_STATUS__VDDC_Boost__SHIFT 0x10
+#define TDC_STATUS__VDDC_Throttle_MASK 0xff000000
+#define TDC_STATUS__VDDC_Throttle__SHIFT 0x18
+#define TDC_MV_AVERAGE__IDD_MASK 0xffff
+#define TDC_MV_AVERAGE__IDD__SHIFT 0x0
+#define TDC_MV_AVERAGE__IDDC_MASK 0xffff0000
+#define TDC_MV_AVERAGE__IDDC__SHIFT 0x10
+#define TDC_VRM_LIMIT__IDD_MASK 0xffff
+#define TDC_VRM_LIMIT__IDD__SHIFT 0x0
+#define TDC_VRM_LIMIT__IDDC_MASK 0xffff0000
+#define TDC_VRM_LIMIT__IDDC__SHIFT 0x10
+#define FEATURE_STATUS__SCLK_DPM_ON_MASK 0x1
+#define FEATURE_STATUS__SCLK_DPM_ON__SHIFT 0x0
+#define FEATURE_STATUS__MCLK_DPM_ON_MASK 0x2
+#define FEATURE_STATUS__MCLK_DPM_ON__SHIFT 0x1
+#define FEATURE_STATUS__LCLK_DPM_ON_MASK 0x4
+#define FEATURE_STATUS__LCLK_DPM_ON__SHIFT 0x2
+#define FEATURE_STATUS__UVD_DPM_ON_MASK 0x8
+#define FEATURE_STATUS__UVD_DPM_ON__SHIFT 0x3
+#define FEATURE_STATUS__VCE_DPM_ON_MASK 0x10
+#define FEATURE_STATUS__VCE_DPM_ON__SHIFT 0x4
+#define FEATURE_STATUS__SAMU_DPM_ON_MASK 0x20
+#define FEATURE_STATUS__SAMU_DPM_ON__SHIFT 0x5
+#define FEATURE_STATUS__ACP_DPM_ON_MASK 0x40
+#define FEATURE_STATUS__ACP_DPM_ON__SHIFT 0x6
+#define FEATURE_STATUS__PCIE_DPM_ON_MASK 0x80
+#define FEATURE_STATUS__PCIE_DPM_ON__SHIFT 0x7
+#define FEATURE_STATUS__BAPM_ON_MASK 0x100
+#define FEATURE_STATUS__BAPM_ON__SHIFT 0x8
+#define FEATURE_STATUS__LPMX_ON_MASK 0x200
+#define FEATURE_STATUS__LPMX_ON__SHIFT 0x9
+#define FEATURE_STATUS__NBDPM_ON_MASK 0x400
+#define FEATURE_STATUS__NBDPM_ON__SHIFT 0xa
+#define FEATURE_STATUS__LHTC_ON_MASK 0x800
+#define FEATURE_STATUS__LHTC_ON__SHIFT 0xb
+#define FEATURE_STATUS__VPC_ON_MASK 0x1000
+#define FEATURE_STATUS__VPC_ON__SHIFT 0xc
+#define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON_MASK 0x2000
+#define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON__SHIFT 0xd
+#define FEATURE_STATUS__TDC_LIMIT_ON_MASK 0x4000
+#define FEATURE_STATUS__TDC_LIMIT_ON__SHIFT 0xe
+#define FEATURE_STATUS__GPU_CAC_ON_MASK 0x8000
+#define FEATURE_STATUS__GPU_CAC_ON__SHIFT 0xf
+#define FEATURE_STATUS__AVS_ON_MASK 0x10000
+#define FEATURE_STATUS__AVS_ON__SHIFT 0x10
+#define FEATURE_STATUS__SPMI_ON_MASK 0x20000
+#define FEATURE_STATUS__SPMI_ON__SHIFT 0x11
+#define FEATURE_STATUS__SCLK_DPM_FORCED_MASK 0x40000
+#define FEATURE_STATUS__SCLK_DPM_FORCED__SHIFT 0x12
+#define FEATURE_STATUS__MCLK_DPM_FORCED_MASK 0x80000
+#define FEATURE_STATUS__MCLK_DPM_FORCED__SHIFT 0x13
+#define FEATURE_STATUS__LCLK_DPM_FORCED_MASK 0x100000
+#define FEATURE_STATUS__LCLK_DPM_FORCED__SHIFT 0x14
+#define FEATURE_STATUS__PCIE_DPM_FORCED_MASK 0x200000
+#define FEATURE_STATUS__PCIE_DPM_FORCED__SHIFT 0x15
+#define FEATURE_STATUS__RESERVED_MASK 0xffc00000
+#define FEATURE_STATUS__RESERVED__SHIFT 0x16
+#define ENTITY_TEMPERATURES_1__GPU_MASK 0xffffffff
+#define ENTITY_TEMPERATURES_1__GPU__SHIFT 0x0
+#define PM_FUSES_1__BapmVddCVidHiSidd_3_MASK 0xff
+#define PM_FUSES_1__BapmVddCVidHiSidd_3__SHIFT 0x0
+#define PM_FUSES_1__BapmVddCVidHiSidd_2_MASK 0xff00
+#define PM_FUSES_1__BapmVddCVidHiSidd_2__SHIFT 0x8
+#define PM_FUSES_1__BapmVddCVidHiSidd_1_MASK 0xff0000
+#define PM_FUSES_1__BapmVddCVidHiSidd_1__SHIFT 0x10
+#define PM_FUSES_1__BapmVddCVidHiSidd_0_MASK 0xff000000
+#define PM_FUSES_1__BapmVddCVidHiSidd_0__SHIFT 0x18
+#define PM_FUSES_2__BapmVddCVidHiSidd_7_MASK 0xff
+#define PM_FUSES_2__BapmVddCVidHiSidd_7__SHIFT 0x0
+#define PM_FUSES_2__BapmVddCVidHiSidd_6_MASK 0xff00
+#define PM_FUSES_2__BapmVddCVidHiSidd_6__SHIFT 0x8
+#define PM_FUSES_2__BapmVddCVidHiSidd_5_MASK 0xff0000
+#define PM_FUSES_2__BapmVddCVidHiSidd_5__SHIFT 0x10
+#define PM_FUSES_2__BapmVddCVidHiSidd_4_MASK 0xff000000
+#define PM_FUSES_2__BapmVddCVidHiSidd_4__SHIFT 0x18
+#define PM_FUSES_3__BapmVddCVidLoSidd_3_MASK 0xff
+#define PM_FUSES_3__BapmVddCVidLoSidd_3__SHIFT 0x0
+#define PM_FUSES_3__BapmVddCVidLoSidd_2_MASK 0xff00
+#define PM_FUSES_3__BapmVddCVidLoSidd_2__SHIFT 0x8
+#define PM_FUSES_3__BapmVddCVidLoSidd_1_MASK 0xff0000
+#define PM_FUSES_3__BapmVddCVidLoSidd_1__SHIFT 0x10
+#define PM_FUSES_3__BapmVddCVidLoSidd_0_MASK 0xff000000
+#define PM_FUSES_3__BapmVddCVidLoSidd_0__SHIFT 0x18
+#define PM_FUSES_4__BapmVddCVidLoSidd_7_MASK 0xff
+#define PM_FUSES_4__BapmVddCVidLoSidd_7__SHIFT 0x0
+#define PM_FUSES_4__BapmVddCVidLoSidd_6_MASK 0xff00
+#define PM_FUSES_4__BapmVddCVidLoSidd_6__SHIFT 0x8
+#define PM_FUSES_4__BapmVddCVidLoSidd_5_MASK 0xff0000
+#define PM_FUSES_4__BapmVddCVidLoSidd_5__SHIFT 0x10
+#define PM_FUSES_4__BapmVddCVidLoSidd_4_MASK 0xff000000
+#define PM_FUSES_4__BapmVddCVidLoSidd_4__SHIFT 0x18
+#define PM_FUSES_5__VddCVid_3_MASK 0xff
+#define PM_FUSES_5__VddCVid_3__SHIFT 0x0
+#define PM_FUSES_5__VddCVid_2_MASK 0xff00
+#define PM_FUSES_5__VddCVid_2__SHIFT 0x8
+#define PM_FUSES_5__VddCVid_1_MASK 0xff0000
+#define PM_FUSES_5__VddCVid_1__SHIFT 0x10
+#define PM_FUSES_5__VddCVid_0_MASK 0xff000000
+#define PM_FUSES_5__VddCVid_0__SHIFT 0x18
+#define PM_FUSES_6__VddCVid_7_MASK 0xff
+#define PM_FUSES_6__VddCVid_7__SHIFT 0x0
+#define PM_FUSES_6__VddCVid_6_MASK 0xff00
+#define PM_FUSES_6__VddCVid_6__SHIFT 0x8
+#define PM_FUSES_6__VddCVid_5_MASK 0xff0000
+#define PM_FUSES_6__VddCVid_5__SHIFT 0x10
+#define PM_FUSES_6__VddCVid_4_MASK 0xff000000
+#define PM_FUSES_6__VddCVid_4__SHIFT 0x18
+#define PM_FUSES_7__SviLoadLineOffsetVddC_MASK 0xff
+#define PM_FUSES_7__SviLoadLineOffsetVddC__SHIFT 0x0
+#define PM_FUSES_7__SviLoadLineTrimVddC_MASK 0xff00
+#define PM_FUSES_7__SviLoadLineTrimVddC__SHIFT 0x8
+#define PM_FUSES_7__SviLoadLineVddC_MASK 0xff0000
+#define PM_FUSES_7__SviLoadLineVddC__SHIFT 0x10
+#define PM_FUSES_7__SviLoadLineEn_MASK 0xff000000
+#define PM_FUSES_7__SviLoadLineEn__SHIFT 0x18
+#define PM_FUSES_8__TDC_MAWt_MASK 0xff
+#define PM_FUSES_8__TDC_MAWt__SHIFT 0x0
+#define PM_FUSES_8__TDC_VDDC_ThrottleReleaseLimitPerc_MASK 0xff00
+#define PM_FUSES_8__TDC_VDDC_ThrottleReleaseLimitPerc__SHIFT 0x8
+#define PM_FUSES_8__TDC_VDDC_PkgLimit_MASK 0xffff0000
+#define PM_FUSES_8__TDC_VDDC_PkgLimit__SHIFT 0x10
+#define PM_FUSES_9__Reserved_MASK 0xff
+#define PM_FUSES_9__Reserved__SHIFT 0x0
+#define PM_FUSES_9__LPMLTemperatureMax_MASK 0xff00
+#define PM_FUSES_9__LPMLTemperatureMax__SHIFT 0x8
+#define PM_FUSES_9__LPMLTemperatureMin_MASK 0xff0000
+#define PM_FUSES_9__LPMLTemperatureMin__SHIFT 0x10
+#define PM_FUSES_9__TdcWaterfallCtl_MASK 0xff000000
+#define PM_FUSES_9__TdcWaterfallCtl__SHIFT 0x18
+#define PM_FUSES_10__LPMLTemperatureScaler_3_MASK 0xff
+#define PM_FUSES_10__LPMLTemperatureScaler_3__SHIFT 0x0
+#define PM_FUSES_10__LPMLTemperatureScaler_2_MASK 0xff00
+#define PM_FUSES_10__LPMLTemperatureScaler_2__SHIFT 0x8
+#define PM_FUSES_10__LPMLTemperatureScaler_1_MASK 0xff0000
+#define PM_FUSES_10__LPMLTemperatureScaler_1__SHIFT 0x10
+#define PM_FUSES_10__LPMLTemperatureScaler_0_MASK 0xff000000
+#define PM_FUSES_10__LPMLTemperatureScaler_0__SHIFT 0x18
+#define PM_FUSES_11__LPMLTemperatureScaler_7_MASK 0xff
+#define PM_FUSES_11__LPMLTemperatureScaler_7__SHIFT 0x0
+#define PM_FUSES_11__LPMLTemperatureScaler_6_MASK 0xff00
+#define PM_FUSES_11__LPMLTemperatureScaler_6__SHIFT 0x8
+#define PM_FUSES_11__LPMLTemperatureScaler_5_MASK 0xff0000
+#define PM_FUSES_11__LPMLTemperatureScaler_5__SHIFT 0x10
+#define PM_FUSES_11__LPMLTemperatureScaler_4_MASK 0xff000000
+#define PM_FUSES_11__LPMLTemperatureScaler_4__SHIFT 0x18
+#define PM_FUSES_12__LPMLTemperatureScaler_11_MASK 0xff
+#define PM_FUSES_12__LPMLTemperatureScaler_11__SHIFT 0x0
+#define PM_FUSES_12__LPMLTemperatureScaler_10_MASK 0xff00
+#define PM_FUSES_12__LPMLTemperatureScaler_10__SHIFT 0x8
+#define PM_FUSES_12__LPMLTemperatureScaler_9_MASK 0xff0000
+#define PM_FUSES_12__LPMLTemperatureScaler_9__SHIFT 0x10
+#define PM_FUSES_12__LPMLTemperatureScaler_8_MASK 0xff000000
+#define PM_FUSES_12__LPMLTemperatureScaler_8__SHIFT 0x18
+#define PM_FUSES_13__LPMLTemperatureScaler_15_MASK 0xff
+#define PM_FUSES_13__LPMLTemperatureScaler_15__SHIFT 0x0
+#define PM_FUSES_13__LPMLTemperatureScaler_14_MASK 0xff00
+#define PM_FUSES_13__LPMLTemperatureScaler_14__SHIFT 0x8
+#define PM_FUSES_13__LPMLTemperatureScaler_13_MASK 0xff0000
+#define PM_FUSES_13__LPMLTemperatureScaler_13__SHIFT 0x10
+#define PM_FUSES_13__LPMLTemperatureScaler_12_MASK 0xff000000
+#define PM_FUSES_13__LPMLTemperatureScaler_12__SHIFT 0x18
+#define PM_FUSES_14__FuzzyFan_ErrorRateSetDelta_MASK 0xffff
+#define PM_FUSES_14__FuzzyFan_ErrorRateSetDelta__SHIFT 0x0
+#define PM_FUSES_14__FuzzyFan_ErrorSetDelta_MASK 0xffff0000
+#define PM_FUSES_14__FuzzyFan_ErrorSetDelta__SHIFT 0x10
+#define PM_FUSES_15__Reserved6_MASK 0xffff
+#define PM_FUSES_15__Reserved6__SHIFT 0x0
+#define PM_FUSES_15__FuzzyFan_PwmSetDelta_MASK 0xffff0000
+#define PM_FUSES_15__FuzzyFan_PwmSetDelta__SHIFT 0x10
+#define PM_FUSES_16__GnbLPML_3_MASK 0xff
+#define PM_FUSES_16__GnbLPML_3__SHIFT 0x0
+#define PM_FUSES_16__GnbLPML_2_MASK 0xff00
+#define PM_FUSES_16__GnbLPML_2__SHIFT 0x8
+#define PM_FUSES_16__GnbLPML_1_MASK 0xff0000
+#define PM_FUSES_16__GnbLPML_1__SHIFT 0x10
+#define PM_FUSES_16__GnbLPML_0_MASK 0xff000000
+#define PM_FUSES_16__GnbLPML_0__SHIFT 0x18
+#define PM_FUSES_17__GnbLPML_7_MASK 0xff
+#define PM_FUSES_17__GnbLPML_7__SHIFT 0x0
+#define PM_FUSES_17__GnbLPML_6_MASK 0xff00
+#define PM_FUSES_17__GnbLPML_6__SHIFT 0x8
+#define PM_FUSES_17__GnbLPML_5_MASK 0xff0000
+#define PM_FUSES_17__GnbLPML_5__SHIFT 0x10
+#define PM_FUSES_17__GnbLPML_4_MASK 0xff000000
+#define PM_FUSES_17__GnbLPML_4__SHIFT 0x18
+#define PM_FUSES_18__GnbLPML_11_MASK 0xff
+#define PM_FUSES_18__GnbLPML_11__SHIFT 0x0
+#define PM_FUSES_18__GnbLPML_10_MASK 0xff00
+#define PM_FUSES_18__GnbLPML_10__SHIFT 0x8
+#define PM_FUSES_18__GnbLPML_9_MASK 0xff0000
+#define PM_FUSES_18__GnbLPML_9__SHIFT 0x10
+#define PM_FUSES_18__GnbLPML_8_MASK 0xff000000
+#define PM_FUSES_18__GnbLPML_8__SHIFT 0x18
+#define PM_FUSES_19__GnbLPML_15_MASK 0xff
+#define PM_FUSES_19__GnbLPML_15__SHIFT 0x0
+#define PM_FUSES_19__GnbLPML_14_MASK 0xff00
+#define PM_FUSES_19__GnbLPML_14__SHIFT 0x8
+#define PM_FUSES_19__GnbLPML_13_MASK 0xff0000
+#define PM_FUSES_19__GnbLPML_13__SHIFT 0x10
+#define PM_FUSES_19__GnbLPML_12_MASK 0xff000000
+#define PM_FUSES_19__GnbLPML_12__SHIFT 0x18
+#define PM_FUSES_20__Reserved1_1_MASK 0xff
+#define PM_FUSES_20__Reserved1_1__SHIFT 0x0
+#define PM_FUSES_20__Reserved1_0_MASK 0xff00
+#define PM_FUSES_20__Reserved1_0__SHIFT 0x8
+#define PM_FUSES_20__GnbLPMLMinVid_MASK 0xff0000
+#define PM_FUSES_20__GnbLPMLMinVid__SHIFT 0x10
+#define PM_FUSES_20__GnbLPMLMaxVid_MASK 0xff000000
+#define PM_FUSES_20__GnbLPMLMaxVid__SHIFT 0x18
+#define PM_FUSES_21__BapmVddCBaseLeakageLoSidd_MASK 0xffff
+#define PM_FUSES_21__BapmVddCBaseLeakageLoSidd__SHIFT 0x0
+#define PM_FUSES_21__BapmVddCBaseLeakageHiSidd_MASK 0xffff0000
+#define PM_FUSES_21__BapmVddCBaseLeakageHiSidd__SHIFT 0x10
+#define SMU_PM_STATUS_0__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_0__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_1__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_1__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_2__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_2__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_3__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_3__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_4__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_4__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_5__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_5__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_6__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_6__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_7__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_7__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_8__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_8__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_9__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_9__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_10__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_10__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_11__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_11__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_12__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_12__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_13__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_13__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_14__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_14__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_15__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_15__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_16__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_16__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_17__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_17__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_18__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_18__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_19__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_19__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_20__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_20__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_21__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_21__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_22__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_22__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_23__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_23__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_24__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_24__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_25__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_25__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_26__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_26__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_27__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_27__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_28__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_28__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_29__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_29__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_30__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_30__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_31__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_31__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_32__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_32__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_33__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_33__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_34__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_34__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_35__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_35__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_36__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_36__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_37__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_37__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_38__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_38__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_39__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_39__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_40__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_40__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_41__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_41__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_42__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_42__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_43__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_43__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_44__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_44__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_45__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_45__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_46__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_46__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_47__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_47__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_48__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_48__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_49__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_49__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_50__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_50__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_51__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_51__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_52__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_52__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_53__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_53__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_54__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_54__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_55__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_55__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_56__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_56__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_57__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_57__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_58__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_58__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_59__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_59__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_60__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_60__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_61__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_61__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_62__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_62__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_63__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_63__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_64__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_64__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_65__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_65__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_66__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_66__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_67__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_67__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_68__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_68__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_69__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_69__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_70__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_70__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_71__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_71__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_72__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_72__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_73__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_73__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_74__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_74__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_75__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_75__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_76__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_76__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_77__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_77__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_78__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_78__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_79__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_79__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_80__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_80__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_81__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_81__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_82__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_82__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_83__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_83__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_84__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_84__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_85__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_85__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_86__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_86__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_87__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_87__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_88__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_88__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_89__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_89__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_90__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_90__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_91__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_91__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_92__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_92__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_93__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_93__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_94__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_94__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_95__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_95__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_96__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_96__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_97__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_97__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_98__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_98__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_99__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_99__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_100__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_100__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_101__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_101__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_102__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_102__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_103__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_103__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_104__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_104__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_105__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_105__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_106__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_106__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_107__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_107__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_108__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_108__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_109__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_109__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_110__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_110__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_111__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_111__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_112__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_112__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_113__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_113__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_114__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_114__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_115__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_115__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_116__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_116__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_117__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_117__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_118__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_118__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_119__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_119__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_120__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_120__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_121__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_121__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_122__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_122__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_123__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_123__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_124__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_124__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_125__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_125__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_126__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_126__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_127__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_127__DATA__SHIFT 0x0
+#define CG_THERMAL_INT_ENA__THERM_INTH_SET_MASK 0x1
+#define CG_THERMAL_INT_ENA__THERM_INTH_SET__SHIFT 0x0
+#define CG_THERMAL_INT_ENA__THERM_INTL_SET_MASK 0x2
+#define CG_THERMAL_INT_ENA__THERM_INTL_SET__SHIFT 0x1
+#define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET_MASK 0x4
+#define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET__SHIFT 0x2
+#define CG_THERMAL_INT_ENA__THERM_INTH_CLR_MASK 0x8
+#define CG_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT 0x3
+#define CG_THERMAL_INT_ENA__THERM_INTL_CLR_MASK 0x10
+#define CG_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT 0x4
+#define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR_MASK 0x20
+#define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT 0x5
+#define CG_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK 0xff
+#define CG_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT 0x0
+#define CG_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK 0xff00
+#define CG_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT 0x8
+#define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD_MASK 0xff0000
+#define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD__SHIFT 0x10
+#define CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK 0x1000000
+#define CG_THERMAL_INT_CTRL__THERM_INTH_MASK__SHIFT 0x18
+#define CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK 0x2000000
+#define CG_THERMAL_INT_CTRL__THERM_INTL_MASK__SHIFT 0x19
+#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK 0x4000000
+#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK__SHIFT 0x1a
+#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK_MASK 0x8000000
+#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK__SHIFT 0x1b
+#define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA_MASK 0x10000000
+#define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA__SHIFT 0x1c
+#define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT_MASK 0x1
+#define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT__SHIFT 0x0
+#define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT_MASK 0x2
+#define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT__SHIFT 0x1
+#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT_MASK 0x4
+#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT__SHIFT 0x2
+#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT_MASK 0x8
+#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT__SHIFT 0x3
+#define CG_THERMAL_CTRL__DPM_EVENT_SRC_MASK 0x7
+#define CG_THERMAL_CTRL__DPM_EVENT_SRC__SHIFT 0x0
+#define CG_THERMAL_CTRL__THERM_INC_CLK_MASK 0x8
+#define CG_THERMAL_CTRL__THERM_INC_CLK__SHIFT 0x3
+#define CG_THERMAL_CTRL__SPARE_MASK 0x3ff0
+#define CG_THERMAL_CTRL__SPARE__SHIFT 0x4
+#define CG_THERMAL_CTRL__DIG_THERM_DPM_MASK 0x3fc000
+#define CG_THERMAL_CTRL__DIG_THERM_DPM__SHIFT 0xe
+#define CG_THERMAL_CTRL__RESERVED_MASK 0x1c00000
+#define CG_THERMAL_CTRL__RESERVED__SHIFT 0x16
+#define CG_THERMAL_CTRL__CTF_PAD_POLARITY_MASK 0x2000000
+#define CG_THERMAL_CTRL__CTF_PAD_POLARITY__SHIFT 0x19
+#define CG_THERMAL_CTRL__CTF_PAD_EN_MASK 0x4000000
+#define CG_THERMAL_CTRL__CTF_PAD_EN__SHIFT 0x1a
+#define CG_THERMAL_STATUS__SPARE_MASK 0x1ff
+#define CG_THERMAL_STATUS__SPARE__SHIFT 0x0
+#define CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK 0x1fe00
+#define CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT 0x9
+#define CG_THERMAL_STATUS__THERM_ALERT_MASK 0x20000
+#define CG_THERMAL_STATUS__THERM_ALERT__SHIFT 0x11
+#define CG_THERMAL_STATUS__GEN_STATUS_MASK 0x3c0000
+#define CG_THERMAL_STATUS__GEN_STATUS__SHIFT 0x12
+#define CG_THERMAL_INT__DIG_THERM_CTF_MASK 0xff
+#define CG_THERMAL_INT__DIG_THERM_CTF__SHIFT 0x0
+#define CG_THERMAL_INT__DIG_THERM_INTH_MASK 0xff00
+#define CG_THERMAL_INT__DIG_THERM_INTH__SHIFT 0x8
+#define CG_THERMAL_INT__DIG_THERM_INTL_MASK 0xff0000
+#define CG_THERMAL_INT__DIG_THERM_INTL__SHIFT 0x10
+#define CG_THERMAL_INT__THERM_INT_MASK_MASK 0xf000000
+#define CG_THERMAL_INT__THERM_INT_MASK__SHIFT 0x18
+#define CG_MULT_THERMAL_CTRL__TS_FILTER_MASK 0xf
+#define CG_MULT_THERMAL_CTRL__TS_FILTER__SHIFT 0x0
+#define CG_MULT_THERMAL_CTRL__UNUSED_MASK 0xf0
+#define CG_MULT_THERMAL_CTRL__UNUSED__SHIFT 0x4
+#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST_MASK 0x200
+#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST__SHIFT 0x9
+#define CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK 0xff00000
+#define CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT 0x14
+#define CG_MULT_THERMAL_CTRL__THM_READY_CLEAR_MASK 0x10000000
+#define CG_MULT_THERMAL_CTRL__THM_READY_CLEAR__SHIFT 0x1c
+#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP_MASK 0x1ff
+#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP__SHIFT 0x0
+#define CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK 0x3fe00
+#define CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT 0x9
+#define CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK 0xff
+#define CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT 0x0
+#define CG_FDO_CTRL0__FAN_SPINUP_DUTY_MASK 0xff00
+#define CG_FDO_CTRL0__FAN_SPINUP_DUTY__SHIFT 0x8
+#define CG_FDO_CTRL0__FDO_PWM_MANUAL_MASK 0x10000
+#define CG_FDO_CTRL0__FDO_PWM_MANUAL__SHIFT 0x10
+#define CG_FDO_CTRL0__FDO_PWM_HYSTER_MASK 0x7e0000
+#define CG_FDO_CTRL0__FDO_PWM_HYSTER__SHIFT 0x11
+#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN_MASK 0x800000
+#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN__SHIFT 0x17
+#define CG_FDO_CTRL0__FDO_PWM_RAMP_MASK 0xff000000
+#define CG_FDO_CTRL0__FDO_PWM_RAMP__SHIFT 0x18
+#define CG_FDO_CTRL1__FMAX_DUTY100_MASK 0xff
+#define CG_FDO_CTRL1__FMAX_DUTY100__SHIFT 0x0
+#define CG_FDO_CTRL1__FMIN_DUTY_MASK 0xff00
+#define CG_FDO_CTRL1__FMIN_DUTY__SHIFT 0x8
+#define CG_FDO_CTRL1__M_MASK 0xff0000
+#define CG_FDO_CTRL1__M__SHIFT 0x10
+#define CG_FDO_CTRL1__RESERVED_MASK 0x3f000000
+#define CG_FDO_CTRL1__RESERVED__SHIFT 0x18
+#define CG_FDO_CTRL1__FDO_PWRDNB_MASK 0x40000000
+#define CG_FDO_CTRL1__FDO_PWRDNB__SHIFT 0x1e
+#define CG_FDO_CTRL2__TMIN_MASK 0xff
+#define CG_FDO_CTRL2__TMIN__SHIFT 0x0
+#define CG_FDO_CTRL2__FAN_SPINUP_TIME_MASK 0x700
+#define CG_FDO_CTRL2__FAN_SPINUP_TIME__SHIFT 0x8
+#define CG_FDO_CTRL2__FDO_PWM_MODE_MASK 0x3800
+#define CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT 0xb
+#define CG_FDO_CTRL2__TMIN_HYSTER_MASK 0x1c000
+#define CG_FDO_CTRL2__TMIN_HYSTER__SHIFT 0xe
+#define CG_FDO_CTRL2__TMAX_MASK 0x1fe0000
+#define CG_FDO_CTRL2__TMAX__SHIFT 0x11
+#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK 0xfe000000
+#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT 0x19
+#define CG_TACH_CTRL__EDGE_PER_REV_MASK 0x7
+#define CG_TACH_CTRL__EDGE_PER_REV__SHIFT 0x0
+#define CG_TACH_CTRL__TARGET_PERIOD_MASK 0xfffffff8
+#define CG_TACH_CTRL__TARGET_PERIOD__SHIFT 0x3
+#define CG_TACH_STATUS__TACH_PERIOD_MASK 0xffffffff
+#define CG_TACH_STATUS__TACH_PERIOD__SHIFT 0x0
+#define CC_THM_STRAPS0__TMON0_BGADJ_MASK 0x1fe
+#define CC_THM_STRAPS0__TMON0_BGADJ__SHIFT 0x1
+#define CC_THM_STRAPS0__TMON1_BGADJ_MASK 0x1fe00
+#define CC_THM_STRAPS0__TMON1_BGADJ__SHIFT 0x9
+#define CC_THM_STRAPS0__TMON_CMON_FUSE_SEL_MASK 0x20000
+#define CC_THM_STRAPS0__TMON_CMON_FUSE_SEL__SHIFT 0x11
+#define CC_THM_STRAPS0__NUM_ACQ_MASK 0x1c0000
+#define CC_THM_STRAPS0__NUM_ACQ__SHIFT 0x12
+#define CC_THM_STRAPS0__TMON_CLK_SEL_MASK 0xe00000
+#define CC_THM_STRAPS0__TMON_CLK_SEL__SHIFT 0x15
+#define CC_THM_STRAPS0__TMON_CONFIG_SOURCE_MASK 0x1000000
+#define CC_THM_STRAPS0__TMON_CONFIG_SOURCE__SHIFT 0x18
+#define CC_THM_STRAPS0__CTF_DISABLE_MASK 0x2000000
+#define CC_THM_STRAPS0__CTF_DISABLE__SHIFT 0x19
+#define CC_THM_STRAPS0__TMON0_DISABLE_MASK 0x4000000
+#define CC_THM_STRAPS0__TMON0_DISABLE__SHIFT 0x1a
+#define CC_THM_STRAPS0__TMON1_DISABLE_MASK 0x8000000
+#define CC_THM_STRAPS0__TMON1_DISABLE__SHIFT 0x1b
+#define CC_THM_STRAPS0__TMON2_DISABLE_MASK 0x10000000
+#define CC_THM_STRAPS0__TMON2_DISABLE__SHIFT 0x1c
+#define CC_THM_STRAPS0__TMON3_DISABLE_MASK 0x20000000
+#define CC_THM_STRAPS0__TMON3_DISABLE__SHIFT 0x1d
+#define CC_THM_STRAPS0__UNUSED_MASK 0x80000000
+#define CC_THM_STRAPS0__UNUSED__SHIFT 0x1f
+#define THM_TMON0_RDIL0_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL0_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL0_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL0_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL0_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL0_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL1_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL1_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL1_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL1_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL1_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL1_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL2_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL2_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL2_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL2_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL2_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL2_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL3_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL3_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL3_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL3_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL3_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL3_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL4_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL4_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL4_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL4_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL4_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL4_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL5_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL5_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL5_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL5_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL5_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL5_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL6_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL6_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL6_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL6_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL6_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL6_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL7_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL7_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL7_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL7_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL7_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL7_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL8_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL8_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL8_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL8_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL8_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL8_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL9_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL9_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL9_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL9_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL9_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL9_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL10_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL10_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL10_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL10_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL10_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL10_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL11_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL11_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL11_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL11_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL11_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL11_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL12_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL12_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL12_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL12_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL12_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL12_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL13_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL13_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL13_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL13_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL13_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL13_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL14_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL14_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL14_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL14_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL14_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL14_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL15_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL15_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL15_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL15_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL15_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL15_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR0_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR0_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR0_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR0_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR0_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR0_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR1_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR1_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR1_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR1_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR1_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR1_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR2_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR2_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR2_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR2_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR2_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR2_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR3_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR3_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR3_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR3_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR3_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR3_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR4_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR4_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR4_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR4_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR4_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR4_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR5_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR5_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR5_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR5_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR5_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR5_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR6_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR6_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR6_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR6_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR6_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR6_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR7_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR7_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR7_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR7_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR7_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR7_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR8_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR8_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR8_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR8_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR8_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR8_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR9_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR9_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR9_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR9_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR9_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR9_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR10_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR10_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR10_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR10_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR10_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR10_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR11_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR11_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR11_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR11_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR11_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR11_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR12_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR12_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR12_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR12_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR12_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR12_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR13_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR13_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR13_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR13_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR13_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR13_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR14_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR14_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR14_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR14_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR14_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR14_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR15_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR15_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR15_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR15_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR15_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR15_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_INT_DATA__Z_MASK 0x7ff
+#define THM_TMON0_INT_DATA__Z__SHIFT 0x0
+#define THM_TMON0_INT_DATA__VALID_MASK 0x800
+#define THM_TMON0_INT_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_INT_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_INT_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_DEBUG__DEBUG_RDI_MASK 0x1f
+#define THM_TMON0_DEBUG__DEBUG_RDI__SHIFT 0x0
+#define THM_TMON0_DEBUG__DEBUG_Z_MASK 0xffe0
+#define THM_TMON0_DEBUG__DEBUG_Z__SHIFT 0x5
+#define THM_TMON0_STATUS__CURRENT_RDI_MASK 0x1f
+#define THM_TMON0_STATUS__CURRENT_RDI__SHIFT 0x0
+#define THM_TMON0_STATUS__MEAS_DONE_MASK 0x20
+#define THM_TMON0_STATUS__MEAS_DONE__SHIFT 0x5
+#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK 0x1
+#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN__SHIFT 0x0
+#define GENERAL_PWRMGT__STATIC_PM_EN_MASK 0x2
+#define GENERAL_PWRMGT__STATIC_PM_EN__SHIFT 0x1
+#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK 0x4
+#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS__SHIFT 0x2
+#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE_MASK 0x8
+#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE__SHIFT 0x3
+#define GENERAL_PWRMGT__SW_SMIO_INDEX_MASK 0x40
+#define GENERAL_PWRMGT__SW_SMIO_INDEX__SHIFT 0x6
+#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI_MASK 0x100
+#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI__SHIFT 0x8
+#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI_MASK 0x200
+#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI__SHIFT 0x9
+#define GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK 0x400
+#define GENERAL_PWRMGT__VOLT_PWRMGT_EN__SHIFT 0xa
+#define GENERAL_PWRMGT__SPARE11_MASK 0x800
+#define GENERAL_PWRMGT__SPARE11__SHIFT 0xb
+#define GENERAL_PWRMGT__GPU_COUNTER_ACPI_MASK 0x4000
+#define GENERAL_PWRMGT__GPU_COUNTER_ACPI__SHIFT 0xe
+#define GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK 0x8000
+#define GENERAL_PWRMGT__GPU_COUNTER_CLK__SHIFT 0xf
+#define GENERAL_PWRMGT__GPU_COUNTER_OFF_MASK 0x10000
+#define GENERAL_PWRMGT__GPU_COUNTER_OFF__SHIFT 0x10
+#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF_MASK 0x20000
+#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF__SHIFT 0x11
+#define GENERAL_PWRMGT__SPARE18_MASK 0x40000
+#define GENERAL_PWRMGT__SPARE18__SHIFT 0x12
+#define GENERAL_PWRMGT__ACPI_D3_VID_MASK 0x180000
+#define GENERAL_PWRMGT__ACPI_D3_VID__SHIFT 0x13
+#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK 0x800000
+#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN__SHIFT 0x17
+#define GENERAL_PWRMGT__SPARE27_MASK 0x8000000
+#define GENERAL_PWRMGT__SPARE27__SHIFT 0x1b
+#define GENERAL_PWRMGT__SPARE_MASK 0xf0000000
+#define GENERAL_PWRMGT__SPARE__SHIFT 0x1c
+#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK 0x3
+#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT 0x0
+#define CNB_PWRMGT_CNTL__GNB_SLOW_MASK 0x4
+#define CNB_PWRMGT_CNTL__GNB_SLOW__SHIFT 0x2
+#define CNB_PWRMGT_CNTL__FORCE_NB_PS1_MASK 0x8
+#define CNB_PWRMGT_CNTL__FORCE_NB_PS1__SHIFT 0x3
+#define CNB_PWRMGT_CNTL__DPM_ENABLED_MASK 0x10
+#define CNB_PWRMGT_CNTL__DPM_ENABLED__SHIFT 0x4
+#define CNB_PWRMGT_CNTL__SPARE_MASK 0xffffffe0
+#define CNB_PWRMGT_CNTL__SPARE__SHIFT 0x5
+#define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK 0x1
+#define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF__SHIFT 0x0
+#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK 0x10
+#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT__SHIFT 0x4
+#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK 0x20
+#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT__SHIFT 0x5
+#define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN_MASK 0x4000
+#define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN__SHIFT 0xe
+#define SCLK_PWRMGT_CNTL__AUTO_SCLK_PULSE_SKIP_MASK 0x8000
+#define SCLK_PWRMGT_CNTL__AUTO_SCLK_PULSE_SKIP__SHIFT 0xf
+#define SCLK_PWRMGT_CNTL__LIGHT_SLEEP_COUNTER_MASK 0x1f0000
+#define SCLK_PWRMGT_CNTL__LIGHT_SLEEP_COUNTER__SHIFT 0x10
+#define SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK 0x200000
+#define SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN__SHIFT 0x15
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE_MASK 0xf
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE__SHIFT 0x0
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_MASK 0xf0
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE__SHIFT 0x4
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK 0xf00
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT 0x8
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX_MASK 0xf000
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX__SHIFT 0xc
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK 0x1f0000
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT 0x10
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX_MASK 0x3e00000
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX__SHIFT 0x15
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX_MASK 0x1c000000
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX__SHIFT 0x1a
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX_MASK 0xe0000000
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX__SHIFT 0x1d
+#define PWR_PCC_CONTROL__PCC_POLARITY_MASK 0x1
+#define PWR_PCC_CONTROL__PCC_POLARITY__SHIFT 0x0
+#define PWR_PCC_GPIO_SELECT__GPIO_MASK 0xffffffff
+#define PWR_PCC_GPIO_SELECT__GPIO__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_0__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_0__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_0__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
+#define CG_FREQ_TRAN_VOTING_0__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
+#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_1__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_1__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_1__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
+#define CG_FREQ_TRAN_VOTING_1__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
+#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_2__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_2__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_2__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
+#define CG_FREQ_TRAN_VOTING_2__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
+#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_3__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_3__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_3__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
+#define CG_FREQ_TRAN_VOTING_3__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
+#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_4__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_4__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_4__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
+#define CG_FREQ_TRAN_VOTING_4__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
+#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_5__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_5__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_5__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
+#define CG_FREQ_TRAN_VOTING_5__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
+#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_6__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_6__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_6__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
+#define CG_FREQ_TRAN_VOTING_6__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
+#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_7__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_7__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_7__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
+#define CG_FREQ_TRAN_VOTING_7__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
+#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define PLL_TEST_CNTL__TST_SRC_SEL_MASK 0xf
+#define PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x0
+#define PLL_TEST_CNTL__TST_REF_SEL_MASK 0xf0
+#define PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x4
+#define PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x7f00
+#define PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0x8
+#define PLL_TEST_CNTL__TST_RESET_MASK 0x8000
+#define PLL_TEST_CNTL__TST_RESET__SHIFT 0xf
+#define PLL_TEST_CNTL__TEST_COUNT_MASK 0xfffe0000
+#define PLL_TEST_CNTL__TEST_COUNT__SHIFT 0x11
+#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_MASK 0xffff
+#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD__SHIFT 0x0
+#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT_MASK 0xf0000
+#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT__SHIFT 0x10
+#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK 0x3
+#define CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT 0x0
+#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT_MASK 0x3fff0
+#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT__SHIFT 0x4
+#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT_MASK 0x700000
+#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT__SHIFT 0x14
+#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG_MASK 0x3000000
+#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG__SHIFT 0x18
+#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_DISABLE_MASK 0x10000000
+#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_DISABLE__SHIFT 0x1c
+#define CG_DISPLAY_GAP_CNTL2__VBI_PREDICTION_MASK 0xffffffff
+#define CG_DISPLAY_GAP_CNTL2__VBI_PREDICTION__SHIFT 0x0
+#define CG_ACPI_CNTL__SCLK_ACPI_DIV_MASK 0x7f
+#define CG_ACPI_CNTL__SCLK_ACPI_DIV__SHIFT 0x0
+#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP_MASK 0x80
+#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP__SHIFT 0x7
+#define SCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7
+#define SCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0
+#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8
+#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3
+#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0
+#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4
+#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK_MASK 0x10000
+#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK__SHIFT 0x10
+#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK_MASK 0x20000
+#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK__SHIFT 0x11
+#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK_MASK 0x40000
+#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK__SHIFT 0x12
+#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK_MASK 0x80000
+#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK__SHIFT 0x13
+#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK_MASK 0x100000
+#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK__SHIFT 0x14
+#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK_MASK 0x200000
+#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK__SHIFT 0x15
+#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK_MASK 0x400000
+#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK__SHIFT 0x16
+#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK_MASK 0x800000
+#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK__SHIFT 0x17
+#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK_MASK 0x1000000
+#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK__SHIFT 0x18
+#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK_MASK 0x2000000
+#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK__SHIFT 0x19
+#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE_MASK 0x4000000
+#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE__SHIFT 0x1a
+#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE_MASK 0x8000000
+#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE__SHIFT 0x1b
+#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK_MASK 0x10000000
+#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK__SHIFT 0x1c
+#define SCLK_DEEP_SLEEP_CNTL__VCE_BUSY_MASK_MASK 0x20000000
+#define SCLK_DEEP_SLEEP_CNTL__VCE_BUSY_MASK__SHIFT 0x1d
+#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK_MASK 0x40000000
+#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK__SHIFT 0x1e
+#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000
+#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f
+#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK_MASK 0x1
+#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK__SHIFT 0x0
+#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK_MASK 0x2
+#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK__SHIFT 0x1
+#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK_MASK 0x4
+#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK__SHIFT 0x2
+#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK_MASK 0x8
+#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK__SHIFT 0x3
+#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK_MASK 0x10
+#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK__SHIFT 0x4
+#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK_MASK 0x40
+#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK__SHIFT 0x6
+#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK_MASK 0x80
+#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK__SHIFT 0x7
+#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK_MASK 0x100
+#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK__SHIFT 0x8
+#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK_MASK 0x200
+#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK__SHIFT 0x9
+#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK_MASK 0x400
+#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK__SHIFT 0xa
+#define SCLK_DEEP_SLEEP_CNTL2__VCE_CG_MC_STAT_BUSY_MASK_MASK 0x800
+#define SCLK_DEEP_SLEEP_CNTL2__VCE_CG_MC_STAT_BUSY_MASK__SHIFT 0xb
+#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_MC_STAT_BUSY_MASK_MASK 0x1000
+#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_MC_STAT_BUSY_MASK__SHIFT 0xc
+#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_STATUS_BUSY_MASK_MASK 0x2000
+#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_STATUS_BUSY_MASK__SHIFT 0xd
+#define SCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK_MASK 0x4000
+#define SCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK__SHIFT 0xe
+#define SCLK_DEEP_SLEEP_CNTL2__SHALLOW_DIV_ID_MASK 0xe00000
+#define SCLK_DEEP_SLEEP_CNTL2__SHALLOW_DIV_ID__SHIFT 0x15
+#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION_MASK 0xff000000
+#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION__SHIFT 0x18
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK_MASK 0x1
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK__SHIFT 0x0
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK_MASK 0x2
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK__SHIFT 0x1
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK_MASK 0x4
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK__SHIFT 0x2
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK_MASK 0x8
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK__SHIFT 0x3
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK_MASK 0x10
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK__SHIFT 0x4
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK_MASK 0x20
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK__SHIFT 0x5
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK_MASK 0x40
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK__SHIFT 0x6
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK_MASK 0x80
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK__SHIFT 0x7
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK_MASK 0x100
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK__SHIFT 0x8
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK_MASK 0x200
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK__SHIFT 0x9
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK_MASK 0x400
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK__SHIFT 0xa
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK_MASK 0x800
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK__SHIFT 0xb
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK_MASK 0x1000
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK__SHIFT 0xc
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK_MASK 0x2000
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK__SHIFT 0xd
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK_MASK 0x4000
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK__SHIFT 0xe
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK_MASK 0x8000
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK__SHIFT 0xf
+#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID_MASK 0x7
+#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID__SHIFT 0x0
+#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID_MASK 0x38
+#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID__SHIFT 0x3
+#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE_MASK 0x10000
+#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE__SHIFT 0x10
+#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID_MASK 0xe0000
+#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID__SHIFT 0x11
+#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID_MASK 0x700000
+#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID__SHIFT 0x14
+#define LCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7
+#define LCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0
+#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8
+#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3
+#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0
+#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4
+#define LCLK_DEEP_SLEEP_CNTL__RESERVED_MASK 0x7fff0000
+#define LCLK_DEEP_SLEEP_CNTL__RESERVED__SHIFT 0x10
+#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000
+#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f
+#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK_MASK 0x1
+#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK__SHIFT 0x0
+#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK_MASK 0x2
+#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK__SHIFT 0x1
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK_MASK 0x4
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK__SHIFT 0x2
+#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3_MASK 0x8
+#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3__SHIFT 0x3
+#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK_MASK 0x10
+#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK__SHIFT 0x4
+#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK_MASK 0x20
+#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK__SHIFT 0x5
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK_MASK 0x40
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK__SHIFT 0x6
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK_MASK 0x80
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK__SHIFT 0x7
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK_MASK 0x100
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK__SHIFT 0x8
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK_MASK 0x200
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK__SHIFT 0x9
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK_MASK 0x400
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK__SHIFT 0xa
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK_MASK 0x800
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK__SHIFT 0xb
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK_MASK 0x1000
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK__SHIFT 0xc
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK_MASK 0x2000
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK__SHIFT 0xd
+#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK_MASK 0x4000
+#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK__SHIFT 0xe
+#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK_MASK 0x8000
+#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK__SHIFT 0xf
+#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK_MASK 0x10000
+#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK__SHIFT 0x10
+#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK_MASK 0x20000
+#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK__SHIFT 0x11
+#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK_MASK 0x40000
+#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK__SHIFT 0x12
+#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK_MASK 0x80000
+#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK__SHIFT 0x13
+#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK_MASK 0x100000
+#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK__SHIFT 0x14
+#define LCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK_MASK 0x200000
+#define LCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK__SHIFT 0x15
+#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_MASK 0xffc00000
+#define LCLK_DEEP_SLEEP_CNTL2__RESERVED__SHIFT 0x16
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX_MASK 0xf
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX__SHIFT 0x0
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX_MASK 0xf0
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX__SHIFT 0x4
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX_MASK 0xf00
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX__SHIFT 0x8
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX_MASK 0xf000
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX__SHIFT 0xc
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX_MASK 0xf0000
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX__SHIFT 0x10
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX_MASK 0xf00000
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX__SHIFT 0x14
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK 0xf000000
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT 0x18
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX_MASK 0xf0000000
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX__SHIFT 0x1c
+#define CG_ULV_PARAMETER__ULV_THRESHOLD_MASK 0xffff
+#define CG_ULV_PARAMETER__ULV_THRESHOLD__SHIFT 0x0
+#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT_MASK 0xf0000
+#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT__SHIFT 0x10
+#define SCLK_MIN_DIV__FRACV_MASK 0xfff
+#define SCLK_MIN_DIV__FRACV__SHIFT 0x0
+#define SCLK_MIN_DIV__INTV_MASK 0x7f000
+#define SCLK_MIN_DIV__INTV__SHIFT 0xc
+#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
+#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
+#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000
+#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
+#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000
+#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a
+#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000
+#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
+#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000
+#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c
+#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000
+#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d
+#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_MASK 0x40000000
+#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT__SHIFT 0x1e
+#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
+#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
+#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000
+#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
+#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000
+#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a
+#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000
+#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
+#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000
+#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c
+#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000
+#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d
+#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_MASK 0x40000000
+#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT__SHIFT 0x1e
+#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
+#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
+#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000
+#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
+#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000
+#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a
+#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000
+#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
+#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000
+#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c
+#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000
+#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d
+#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_MASK 0x40000000
+#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT__SHIFT 0x1e
+#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
+#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
+#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000
+#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
+#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000
+#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a
+#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000
+#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
+#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000
+#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c
+#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000
+#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d
+#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_MASK 0x40000000
+#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT__SHIFT 0x1e
+#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
+#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
+#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000
+#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
+#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000
+#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a
+#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000
+#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
+#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000
+#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c
+#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000
+#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d
+#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_MASK 0x40000000
+#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT__SHIFT 0x1e
+#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
+#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
+#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000
+#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
+#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000
+#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a
+#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000
+#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
+#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000
+#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c
+#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000
+#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d
+#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_MASK 0x40000000
+#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT__SHIFT 0x1e
+#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
+#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
+#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000
+#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
+#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000
+#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a
+#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000
+#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
+#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000
+#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c
+#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000
+#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d
+#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_MASK 0x40000000
+#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT__SHIFT 0x1e
+#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
+#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
+#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000
+#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
+#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000
+#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a
+#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000
+#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
+#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000
+#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c
+#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000
+#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d
+#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_MASK 0x40000000
+#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT__SHIFT 0x1e
+#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
+#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
+#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000
+#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
+#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000
+#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a
+#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000
+#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
+#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000
+#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c
+#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000
+#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d
+#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_MASK 0x40000000
+#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT__SHIFT 0x1e
+#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
+#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
+#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000
+#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
+#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000
+#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a
+#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000
+#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
+#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000
+#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c
+#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000
+#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d
+#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_MASK 0x40000000
+#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT__SHIFT 0x1e
+#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
+#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
+#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000
+#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
+#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000
+#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a
+#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000
+#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
+#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000
+#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c
+#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000
+#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d
+#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_MASK 0x40000000
+#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT__SHIFT 0x1e
+#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
+#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
+#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000
+#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
+#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000
+#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a
+#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000
+#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
+#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000
+#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c
+#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000
+#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d
+#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_MASK 0x40000000
+#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT__SHIFT 0x1e
+#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
+#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
+#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000
+#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
+#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000
+#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a
+#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000
+#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
+#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000
+#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c
+#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000
+#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d
+#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_MASK 0x40000000
+#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT__SHIFT 0x1e
+#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
+#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
+#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000
+#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
+#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000
+#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a
+#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000
+#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
+#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000
+#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c
+#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000
+#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d
+#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_MASK 0x40000000
+#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT__SHIFT 0x1e
+#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
+#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
+#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000
+#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
+#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000
+#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a
+#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000
+#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
+#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000
+#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c
+#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000
+#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d
+#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_MASK 0x40000000
+#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT__SHIFT 0x1e
+#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
+#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
+#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000
+#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
+#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000
+#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a
+#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000
+#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
+#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000
+#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c
+#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000
+#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d
+#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_MASK 0x40000000
+#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT__SHIFT 0x1e
+#define PWR_DISP_TIMER_CONTROL2__DISP_TIMER_PULSE_WIDTH_MASK 0x3ff
+#define PWR_DISP_TIMER_CONTROL2__DISP_TIMER_PULSE_WIDTH__SHIFT 0x0
+#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD_MASK 0xffff
+#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD__SHIFT 0x0
+#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD_UNIT_MASK 0xf0000
+#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD_UNIT__SHIFT 0x10
+#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_EN_MASK 0x1
+#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_EN__SHIFT 0x0
+#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_DETECT_MASK 0x2
+#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_DETECT__SHIFT 0x1
+#define VDDGFX_IDLE_CONTROL__FORCE_VDDGFX_IDLE_EXIT_MASK 0x4
+#define VDDGFX_IDLE_CONTROL__FORCE_VDDGFX_IDLE_EXIT__SHIFT 0x2
+#define VDDGFX_IDLE_CONTROL__SMC_VDDGFX_IDLE_STATE_MASK 0x8
+#define VDDGFX_IDLE_CONTROL__SMC_VDDGFX_IDLE_STATE__SHIFT 0x3
+#define VDDGFX_IDLE_EXIT__BIF_EXIT_REQ_MASK 0x1
+#define VDDGFX_IDLE_EXIT__BIF_EXIT_REQ__SHIFT 0x0
+#define LCAC_MC0_CNTL__MC0_ENABLE_MASK 0x1
+#define LCAC_MC0_CNTL__MC0_ENABLE__SHIFT 0x0
+#define LCAC_MC0_CNTL__MC0_THRESHOLD_MASK 0x1fffe
+#define LCAC_MC0_CNTL__MC0_THRESHOLD__SHIFT 0x1
+#define LCAC_MC0_CNTL__MC0_BLOCK_ID_MASK 0x3e0000
+#define LCAC_MC0_CNTL__MC0_BLOCK_ID__SHIFT 0x11
+#define LCAC_MC0_CNTL__MC0_SIGNAL_ID_MASK 0x3fc00000
+#define LCAC_MC0_CNTL__MC0_SIGNAL_ID__SHIFT 0x16
+#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL_MASK 0xffffffff
+#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL__SHIFT 0x0
+#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL_MASK 0xffffffff
+#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL__SHIFT 0x0
+#define LCAC_MC1_CNTL__MC1_ENABLE_MASK 0x1
+#define LCAC_MC1_CNTL__MC1_ENABLE__SHIFT 0x0
+#define LCAC_MC1_CNTL__MC1_THRESHOLD_MASK 0x1fffe
+#define LCAC_MC1_CNTL__MC1_THRESHOLD__SHIFT 0x1
+#define LCAC_MC1_CNTL__MC1_BLOCK_ID_MASK 0x3e0000
+#define LCAC_MC1_CNTL__MC1_BLOCK_ID__SHIFT 0x11
+#define LCAC_MC1_CNTL__MC1_SIGNAL_ID_MASK 0x3fc00000
+#define LCAC_MC1_CNTL__MC1_SIGNAL_ID__SHIFT 0x16
+#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL_MASK 0xffffffff
+#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL__SHIFT 0x0
+#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL_MASK 0xffffffff
+#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL__SHIFT 0x0
+#define LCAC_MC2_CNTL__MC2_ENABLE_MASK 0x1
+#define LCAC_MC2_CNTL__MC2_ENABLE__SHIFT 0x0
+#define LCAC_MC2_CNTL__MC2_THRESHOLD_MASK 0x1fffe
+#define LCAC_MC2_CNTL__MC2_THRESHOLD__SHIFT 0x1
+#define LCAC_MC2_CNTL__MC2_BLOCK_ID_MASK 0x3e0000
+#define LCAC_MC2_CNTL__MC2_BLOCK_ID__SHIFT 0x11
+#define LCAC_MC2_CNTL__MC2_SIGNAL_ID_MASK 0x3fc00000
+#define LCAC_MC2_CNTL__MC2_SIGNAL_ID__SHIFT 0x16
+#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL_MASK 0xffffffff
+#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL__SHIFT 0x0
+#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL_MASK 0xffffffff
+#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL__SHIFT 0x0
+#define LCAC_MC3_CNTL__MC3_ENABLE_MASK 0x1
+#define LCAC_MC3_CNTL__MC3_ENABLE__SHIFT 0x0
+#define LCAC_MC3_CNTL__MC3_THRESHOLD_MASK 0x1fffe
+#define LCAC_MC3_CNTL__MC3_THRESHOLD__SHIFT 0x1
+#define LCAC_MC3_CNTL__MC3_BLOCK_ID_MASK 0x3e0000
+#define LCAC_MC3_CNTL__MC3_BLOCK_ID__SHIFT 0x11
+#define LCAC_MC3_CNTL__MC3_SIGNAL_ID_MASK 0x3fc00000
+#define LCAC_MC3_CNTL__MC3_SIGNAL_ID__SHIFT 0x16
+#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL_MASK 0xffffffff
+#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL__SHIFT 0x0
+#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL_MASK 0xffffffff
+#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL__SHIFT 0x0
+#define LCAC_CPL_CNTL__CPL_ENABLE_MASK 0x1
+#define LCAC_CPL_CNTL__CPL_ENABLE__SHIFT 0x0
+#define LCAC_CPL_CNTL__CPL_THRESHOLD_MASK 0x1fffe
+#define LCAC_CPL_CNTL__CPL_THRESHOLD__SHIFT 0x1
+#define LCAC_CPL_CNTL__CPL_BLOCK_ID_MASK 0x3e0000
+#define LCAC_CPL_CNTL__CPL_BLOCK_ID__SHIFT 0x11
+#define LCAC_CPL_CNTL__CPL_SIGNAL_ID_MASK 0x3fc00000
+#define LCAC_CPL_CNTL__CPL_SIGNAL_ID__SHIFT 0x16
+#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL_MASK 0xffffffff
+#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL__SHIFT 0x0
+#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL_MASK 0xffffffff
+#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL__SHIFT 0x0
+#define ROM_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
+#define ROM_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
+#define ROM_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
+#define ROM_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
+#define ROM_CNTL__SCK_OVERWRITE_MASK 0x2
+#define ROM_CNTL__SCK_OVERWRITE__SHIFT 0x1
+#define ROM_CNTL__CLOCK_GATING_EN_MASK 0x4
+#define ROM_CNTL__CLOCK_GATING_EN__SHIFT 0x2
+#define ROM_CNTL__CSB_ACTIVE_TO_SCK_SETUP_TIME_MASK 0xff00
+#define ROM_CNTL__CSB_ACTIVE_TO_SCK_SETUP_TIME__SHIFT 0x8
+#define ROM_CNTL__CSB_ACTIVE_TO_SCK_HOLD_TIME_MASK 0xff0000
+#define ROM_CNTL__CSB_ACTIVE_TO_SCK_HOLD_TIME__SHIFT 0x10
+#define ROM_CNTL__SCK_PRESCALE_REFCLK_MASK 0xf000000
+#define ROM_CNTL__SCK_PRESCALE_REFCLK__SHIFT 0x18
+#define ROM_CNTL__SCK_PRESCALE_CRYSTAL_CLK_MASK 0xf0000000
+#define ROM_CNTL__SCK_PRESCALE_CRYSTAL_CLK__SHIFT 0x1c
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR_MASK 0xffffff
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR__SHIFT 0x0
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE_MASK 0x1000000
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE__SHIFT 0x18
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE_MASK 0x2000000
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE__SHIFT 0x19
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE_MASK 0xc000000
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE__SHIFT 0x1a
+#define ROM_STATUS__ROM_BUSY_MASK 0x1
+#define ROM_STATUS__ROM_BUSY__SHIFT 0x0
+#define CGTT_ROM_CLK_CTRL0__ON_DELAY_MASK 0xf
+#define CGTT_ROM_CLK_CTRL0__ON_DELAY__SHIFT 0x0
+#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000
+#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000
+#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f
+#define ROM_INDEX__ROM_INDEX_MASK 0xffffff
+#define ROM_INDEX__ROM_INDEX__SHIFT 0x0
+#define ROM_DATA__ROM_DATA_MASK 0xffffffff
+#define ROM_DATA__ROM_DATA__SHIFT 0x0
+#define ROM_START__ROM_START_MASK 0xffffff
+#define ROM_START__ROM_START__SHIFT 0x0
+#define ROM_SW_CNTL__DATA_SIZE_MASK 0xffff
+#define ROM_SW_CNTL__DATA_SIZE__SHIFT 0x0
+#define ROM_SW_CNTL__COMMAND_SIZE_MASK 0x30000
+#define ROM_SW_CNTL__COMMAND_SIZE__SHIFT 0x10
+#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE_MASK 0x40000
+#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE__SHIFT 0x12
+#define ROM_SW_STATUS__ROM_SW_DONE_MASK 0x1
+#define ROM_SW_STATUS__ROM_SW_DONE__SHIFT 0x0
+#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION_MASK 0xff
+#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION__SHIFT 0x0
+#define ROM_SW_COMMAND__ROM_SW_ADDRESS_MASK 0xffffff00
+#define ROM_SW_COMMAND__ROM_SW_ADDRESS__SHIFT 0x8
+#define ROM_SW_DATA_1__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_1__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_2__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_2__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_3__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_3__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_4__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_4__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_5__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_5__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_6__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_6__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_7__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_7__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_8__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_8__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_9__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_9__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_10__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_10__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_11__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_11__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_12__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_12__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_13__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_13__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_14__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_14__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_15__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_15__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_16__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_16__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_17__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_17__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_18__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_18__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_19__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_19__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_20__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_20__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_21__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_21__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_22__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_22__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_23__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_23__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_24__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_24__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_25__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_25__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_26__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_26__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_27__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_27__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_28__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_28__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_29__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_29__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_30__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_30__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_31__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_31__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_32__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_32__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_33__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_33__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_34__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_34__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_35__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_35__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_36__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_36__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_37__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_37__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_38__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_38__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_39__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_39__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_40__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_40__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_41__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_41__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_42__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_42__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_43__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_43__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_44__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_44__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_45__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_45__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_46__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_46__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_47__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_47__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_48__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_48__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_49__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_49__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_50__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_50__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_51__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_51__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_52__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_52__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_53__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_53__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_54__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_54__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_55__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_55__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_56__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_56__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_57__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_57__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_58__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_58__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_59__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_59__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_60__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_60__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_61__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_61__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_62__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_62__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_63__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_63__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_64__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x0
+
+#endif /* SMU_7_1_1_SH_MASK_H */