OMAP2+: voltage: move prm_irqst_reg from VP into voltage domain
authorKevin Hilman <khilman@ti.com>
Thu, 17 Mar 2011 00:20:35 +0000 (17:20 -0700)
committerKevin Hilman <khilman@ti.com>
Thu, 15 Sep 2011 18:39:09 +0000 (11:39 -0700)
The prm_irqst_reg is not part of the VP.  Move it up into the common
voltage domain struct.

Signed-off-by: Kevin Hilman <khilman@ti.com>
arch/arm/mach-omap2/voltage.c
arch/arm/mach-omap2/voltage.h
arch/arm/mach-omap2/voltagedomains3xxx_data.c
arch/arm/mach-omap2/voltagedomains44xx_data.c
arch/arm/mach-omap2/vp.h
arch/arm/mach-omap2/vp3xxx_data.c
arch/arm/mach-omap2/vp44xx_data.c

index 3151d7525f890ec6cb2dc0c50a3e4af5cfc6bace..a366a6b30a623ca986525746c9081631954df98f 100644 (file)
@@ -426,23 +426,21 @@ static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
                unsigned long target_volt)
 {
        u32 vpconfig;
-       u8 target_vsel, current_vsel, prm_irqst_reg;
+       u8 target_vsel, current_vsel;
        int ret, timeout = 0;
 
        ret = _pre_volt_scale(vdd, target_volt, &target_vsel, &current_vsel);
        if (ret)
                return ret;
 
-       prm_irqst_reg = vdd->vp_data->prm_irqst_data->prm_irqst_reg;
-
        /*
         * Clear all pending TransactionDone interrupt/status. Typical latency
         * is <3us
         */
        while (timeout++ < VP_TRANXDONE_TIMEOUT) {
                vdd->write_reg(vdd->vp_data->prm_irqst_data->tranxdone_status,
-                              vdd->prm_irqst_mod, prm_irqst_reg);
-               if (!(vdd->read_reg(vdd->prm_irqst_mod, prm_irqst_reg) &
+                              vdd->prm_irqst_mod, vdd->prm_irqst_reg);
+               if (!(vdd->read_reg(vdd->prm_irqst_mod, vdd->prm_irqst_reg) &
                      vdd->vp_data->prm_irqst_data->tranxdone_status))
                        break;
                udelay(1);
@@ -475,7 +473,8 @@ static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
         * Depends on SMPSWAITTIMEMIN/MAX and voltage change
         */
        timeout = 0;
-       omap_test_timeout((vdd->read_reg(vdd->prm_irqst_mod, prm_irqst_reg) &
+       omap_test_timeout((vdd->read_reg(vdd->prm_irqst_mod,
+                                        vdd->prm_irqst_reg) &
                           vdd->vp_data->prm_irqst_data->tranxdone_status),
                          VP_TRANXDONE_TIMEOUT, timeout);
        if (timeout >= VP_TRANXDONE_TIMEOUT)
@@ -492,8 +491,8 @@ static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
        timeout = 0;
        while (timeout++ < VP_TRANXDONE_TIMEOUT) {
                vdd->write_reg(vdd->vp_data->prm_irqst_data->tranxdone_status,
-                              vdd->prm_irqst_mod, prm_irqst_reg);
-               if (!(vdd->read_reg(vdd->prm_irqst_mod, prm_irqst_reg) &
+                              vdd->prm_irqst_mod, vdd->prm_irqst_reg);
+               if (!(vdd->read_reg(vdd->prm_irqst_mod, vdd->prm_irqst_reg) &
                      vdd->vp_data->prm_irqst_data->tranxdone_status))
                        break;
                udelay(1);
index ffdc55ee16445e7934a689df960d3653552be9f5..db23d493f66322c3349e8214387fb5abdcd6e899 100644 (file)
@@ -136,6 +136,7 @@ struct omap_vdd_info {
        bool vp_enabled;
 
        s16 prm_irqst_mod;
+       u8 prm_irqst_reg;
        u32 (*read_reg) (u16 mod, u8 offset);
        void (*write_reg) (u32 val, u16 mod, u8 offset);
        int (*volt_scale) (struct omap_vdd_info *vdd,
index 0d30b7fe269bbb0f98acb90fe44bde69f7a91961..f831f9adc881cd5bbc55cde9c8ff2e12f422bec8 100644 (file)
@@ -39,6 +39,7 @@ static const struct omap_vfsm_instance_data omap3_vdd1_vfsm_data = {
 
 static struct omap_vdd_info omap3_vdd1_info = {
        .prm_irqst_mod = OCP_MOD,
+       .prm_irqst_reg = OMAP3_PRM_IRQSTATUS_MPU_OFFSET,
        .vp_data = &omap3_vp1_data,
        .vc_data = &omap3_vc1_data,
        .vfsm = &omap3_vdd1_vfsm_data,
@@ -55,6 +56,7 @@ static const struct omap_vfsm_instance_data omap3_vdd2_vfsm_data = {
 
 static struct omap_vdd_info omap3_vdd2_info = {
        .prm_irqst_mod = OCP_MOD,
+       .prm_irqst_reg = OMAP3_PRM_IRQSTATUS_MPU_OFFSET,
        .vp_data = &omap3_vp2_data,
        .vc_data = &omap3_vc2_data,
        .vfsm = &omap3_vdd2_vfsm_data,
index 1c2d7d78de133763d0b7a280a1a2653b24344e95..64dc265aa2ad0726350b2b704cc4748635f42f90 100644 (file)
@@ -38,6 +38,7 @@ static const struct omap_vfsm_instance_data omap4_vdd_mpu_vfsm_data = {
 
 static struct omap_vdd_info omap4_vdd_mpu_info = {
        .prm_irqst_mod = OMAP4430_PRM_OCP_SOCKET_INST,
+       .prm_irqst_reg = OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET,
        .vp_data = &omap4_vp_mpu_data,
        .vc_data = &omap4_vc_mpu_data,
        .vfsm = &omap4_vdd_mpu_vfsm_data,
@@ -52,6 +53,7 @@ static const struct omap_vfsm_instance_data omap4_vdd_iva_vfsm_data = {
 
 static struct omap_vdd_info omap4_vdd_iva_info = {
        .prm_irqst_mod = OMAP4430_PRM_OCP_SOCKET_INST,
+       .prm_irqst_reg = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
        .vp_data = &omap4_vp_iva_data,
        .vc_data = &omap4_vc_iva_data,
        .vfsm = &omap4_vdd_iva_vfsm_data,
@@ -66,6 +68,7 @@ static const struct omap_vfsm_instance_data omap4_vdd_core_vfsm_data = {
 
 static struct omap_vdd_info omap4_vdd_core_info = {
        .prm_irqst_mod = OMAP4430_PRM_OCP_SOCKET_INST,
+       .prm_irqst_reg = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
        .vp_data = &omap4_vp_core_data,
        .vc_data = &omap4_vc_core_data,
        .vfsm = &omap4_vdd_core_vfsm_data,
index d277da6c0378387e48bb0b6fb2a533fbc42e0ec3..5406b08463b626b98ab733fe7b730597a4f1e8f0 100644 (file)
@@ -70,16 +70,13 @@ struct omap_vp_common_data {
 
 /**
  * struct omap_vp_prm_irqst_data - PRM_IRQSTATUS_MPU.VP_TRANXDONE_ST data
- * @prm_irqst_reg: reg offset for PRM_IRQSTATUS_MPU from top of PRM
  * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
  *
- * XXX prm_irqst_reg does not belong here
  * XXX Note that on OMAP3, VP_TRANXDONE interrupt may not work due to a
  *     hardware bug
  * XXX This structure is probably not needed
  */
 struct omap_vp_prm_irqst_data {
-       u8 prm_irqst_reg;
        u32 tranxdone_status;
 };
 
index c9b3e64d4e4e08b4aba861f45a67451d1242bfc8..a8ea0451d0b4d4ca0392fc417a67e8d4222ad7b4 100644 (file)
@@ -51,7 +51,6 @@ static const struct omap_vp_common_data omap3_vp_common = {
 };
 
 static const struct omap_vp_prm_irqst_data omap3_vp1_prm_irqst_data = {
-       .prm_irqst_reg = OMAP3_PRM_IRQSTATUS_MPU_OFFSET,
        .tranxdone_status = OMAP3430_VP1_TRANXDONE_ST_MASK,
 };
 
@@ -67,7 +66,6 @@ struct omap_vp_instance_data omap3_vp1_data = {
 };
 
 static const struct omap_vp_prm_irqst_data omap3_vp2_prm_irqst_data = {
-       .prm_irqst_reg = OMAP3_PRM_IRQSTATUS_MPU_OFFSET,
        .tranxdone_status = OMAP3430_VP2_TRANXDONE_ST_MASK,
 };
 
index 1a0842e59e8303c1a7e4f0ec051399029932a22c..0957c24b1fa9c62d696f549711393b8162953411 100644 (file)
@@ -52,7 +52,6 @@ static const struct omap_vp_common_data omap4_vp_common = {
 };
 
 static const struct omap_vp_prm_irqst_data omap4_vp_mpu_prm_irqst_data = {
-       .prm_irqst_reg = OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET,
        .tranxdone_status = OMAP4430_VP_MPU_TRANXDONE_ST_MASK,
 };
 
@@ -68,7 +67,6 @@ struct omap_vp_instance_data omap4_vp_mpu_data = {
 };
 
 static const struct omap_vp_prm_irqst_data omap4_vp_iva_prm_irqst_data = {
-       .prm_irqst_reg = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
        .tranxdone_status = OMAP4430_VP_IVA_TRANXDONE_ST_MASK,
 };
 
@@ -84,7 +82,6 @@ struct omap_vp_instance_data omap4_vp_iva_data = {
 };
 
 static const struct omap_vp_prm_irqst_data omap4_vp_core_prm_irqst_data = {
-       .prm_irqst_reg = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
        .tranxdone_status = OMAP4430_VP_CORE_TRANXDONE_ST_MASK,
 };