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[COMMON] i2c: exynos5: set HSI2C s/w reset without clear
authorYoungmin Nam <youngmin.nam@samsung.com>
Mon, 5 Sep 2016 12:53:37 +0000 (21:53 +0900)
committermyung-su.cha <myung-su.cha@samsung.com>
Wed, 9 May 2018 12:14:45 +0000 (21:14 +0900)
This patch sets HSI2C s/w reset before suspend without clear to
prevent central sequence stuck by HSI2C master clock reuqest.

Change-Id: I0cc38923758db76a73d96a331af79dc99d6b863f
Signed-off-by: Youngmin Nam <youngmin.nam@samsung.com>
drivers/i2c/busses/i2c-exynos5.c patch | blob | blame | history

diff --git a/drivers/i2c/busses/i2c-exynos5.c b/drivers/i2c/busses/i2c-exynos5.c
index 7b1cd37dd9bddcd772613e7c3b51dba1be73ad32..a98c2586a6a77a379b95a6f439b0c6e2f068d087 100644 (file)
--- a/drivers/i2c/busses/i2c-exynos5.c
+++ b/drivers/i2c/busses/i2c-exynos5.c
@@ -1137,7 +1137,7 @@ static int exynos5_i2c_suspend_noirq(struct device *dev)
                i2c_unlock_adapter(&i2c->adap);
                return ret;
        }
-       exynos5_i2c_reset(i2c);
+       writel(HSI2C_SW_RST, i2c->regs + HSI2C_CTL);
        clk_disable(i2c->clk);
        exynos_update_ip_idle_status(i2c->idle_ip_index, 1);
 #endif