ARM: dts: silk: Enable SCIF_CLK frequency and pins

Add and enable the external crystal for the SCIF_CLK and its pinctrl, to
be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF.

This increases the range and accuracy of supported baud rates.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts
index 98b8bcca84dac732adb2f7fc07c531252c7f1ecc..66f077a3ca41d1b06a367ca265ee5aac48f71bf2 100644 (file)
--- a/arch/arm/boot/dts/r8a7794-silk.dts
+++ b/arch/arm/boot/dts/r8a7794-silk.dts
@@ -126,11 +126,19 @@
 };
 
 &pfc {
+       pinctrl-0 = <&scif_clk_pins>;
+       pinctrl-names = "default";
+
        scif2_pins: serial2 {
                renesas,groups = "scif2_data";
                renesas,function = "scif2";
        };
 
+       scif_clk_pins: scif_clk {
+               renesas,groups = "scif_clk";
+               renesas,function = "scif_clk";
+       };
+
        ether_pins: ether {
                renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
                renesas,function = "eth";
@@ -184,6 +192,11 @@
        status = "okay";
 };
 
+&scif_clk {
+       clock-frequency = <14745600>;
+       status = "okay";
+};
+
 &ether {
        pinctrl-0 = <&ether_pins &phy1_pins>;
        pinctrl-names = "default";