Endpoint nodes have a reg property. Add their mandatory unit-address.
This solves:
Warning (unit_address_vs_reg): Node /ahb/gadget@
00400000/ep0 has a reg or ranges property, but no unit name
Warning (unit_address_vs_reg): Node /ahb/gadget@
00400000/ep1 has a reg or ranges property, but no unit name
Warning (unit_address_vs_reg): Node /ahb/gadget@
00400000/ep2 has a reg or ranges property, but no unit name
Warning (unit_address_vs_reg): Node /ahb/gadget@
00400000/ep3 has a reg or ranges property, but no unit name
Warning (unit_address_vs_reg): Node /ahb/gadget@
00400000/ep4 has a reg or ranges property, but no unit name
Warning (unit_address_vs_reg): Node /ahb/gadget@
00400000/ep5 has a reg or ranges property, but no unit name
Warning (unit_address_vs_reg): Node /ahb/gadget@
00400000/ep6 has a reg or ranges property, but no unit name
Warning (unit_address_vs_reg): Node /ahb/gadget@
00400000/ep7 has a reg or ranges property, but no unit name
Warning (unit_address_vs_reg): Node /ahb/gadget@
00400000/ep8 has a reg or ranges property, but no unit name
Warning (unit_address_vs_reg): Node /ahb/gadget@
00400000/ep9 has a reg or ranges property, but no unit name
Warning (unit_address_vs_reg): Node /ahb/gadget@
00400000/ep10 has a reg or ranges property, but no unit name
Warning (unit_address_vs_reg): Node /ahb/gadget@
00400000/ep11 has a reg or ranges property, but no unit name
Warning (unit_address_vs_reg): Node /ahb/gadget@
00400000/ep12 has a reg or ranges property, but no unit name
Warning (unit_address_vs_reg): Node /ahb/gadget@
00400000/ep13 has a reg or ranges property, but no unit name
Warning (unit_address_vs_reg): Node /ahb/gadget@
00400000/ep14 has a reg or ranges property, but no unit name
Warning (unit_address_vs_reg): Node /ahb/gadget@
00400000/ep15 has a reg or ranges property, but no unit name
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
clock-names = "pclk", "hclk";
status = "disabled";
- ep0 {
+ ep@0 {
reg = <0>;
atmel,fifo-size = <64>;
atmel,nb-banks = <1>;
};
- ep1 {
+ ep@1 {
reg = <1>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
atmel,can-isoc;
};
- ep2 {
+ ep@2 {
reg = <2>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
atmel,can-isoc;
};
- ep3 {
+ ep@3 {
reg = <3>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <3>;
atmel,can-dma;
};
- ep4 {
+ ep@4 {
reg = <4>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <3>;
atmel,can-dma;
};
- ep5 {
+ ep@5 {
reg = <5>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <3>;
atmel,can-isoc;
};
- ep6 {
+ ep@6 {
reg = <6>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <3>;
clock-names = "pclk", "hclk";
status = "disabled";
- ep0 {
+ ep@0 {
reg = <0>;
atmel,fifo-size = <64>;
atmel,nb-banks = <1>;
};
- ep1 {
+ ep@1 {
reg = <1>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
atmel,can-isoc;
};
- ep2 {
+ ep@2 {
reg = <2>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
atmel,can-isoc;
};
- ep3 {
+ ep@3 {
reg = <3>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <3>;
atmel,can-dma;
};
- ep4 {
+ ep@4 {
reg = <4>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <3>;
atmel,can-dma;
};
- ep5 {
+ ep@5 {
reg = <5>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <3>;
atmel,can-isoc;
};
- ep6 {
+ ep@6 {
reg = <6>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <3>;
clock-names = "hclk", "pclk";
status = "disabled";
- ep0 {
+ ep@0 {
reg = <0>;
atmel,fifo-size = <64>;
atmel,nb-banks = <1>;
};
- ep1 {
+ ep@1 {
reg = <1>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
atmel,can-isoc;
};
- ep2 {
+ ep@2 {
reg = <2>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
atmel,can-isoc;
};
- ep3 {
+ ep@3 {
reg = <3>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <3>;
atmel,can-dma;
};
- ep4 {
+ ep@4 {
reg = <4>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <3>;
atmel,can-dma;
};
- ep5 {
+ ep@5 {
reg = <5>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <3>;
atmel,can-isoc;
};
- ep6 {
+ ep@6 {
reg = <6>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <3>;
clock-names = "pclk", "hclk";
status = "disabled";
- ep0 {
+ ep@0 {
reg = <0>;
atmel,fifo-size = <64>;
atmel,nb-banks = <1>;
};
- ep1 {
+ ep@1 {
reg = <1>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <3>;
atmel,can-isoc;
};
- ep2 {
+ ep@2 {
reg = <2>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <3>;
atmel,can-isoc;
};
- ep3 {
+ ep@3 {
reg = <3>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
atmel,can-isoc;
};
- ep4 {
+ ep@4 {
reg = <4>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
atmel,can-isoc;
};
- ep5 {
+ ep@5 {
reg = <5>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
atmel,can-isoc;
};
- ep6 {
+ ep@6 {
reg = <6>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
atmel,can-isoc;
};
- ep7 {
+ ep@7 {
reg = <7>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
atmel,can-isoc;
};
- ep8 {
+ ep@8 {
reg = <8>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
atmel,can-isoc;
};
- ep9 {
+ ep@9 {
reg = <9>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
atmel,can-isoc;
};
- ep10 {
+ ep@10 {
reg = <10>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
atmel,can-isoc;
};
- ep11 {
+ ep@11 {
reg = <11>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
atmel,can-isoc;
};
- ep12 {
+ ep@12 {
reg = <12>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
atmel,can-isoc;
};
- ep13 {
+ ep@13 {
reg = <13>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
atmel,can-isoc;
};
- ep14 {
+ ep@14 {
reg = <14>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
atmel,can-isoc;
};
- ep15 {
+ ep@15 {
reg = <15>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
clock-names = "pclk", "hclk";
status = "disabled";
- ep0 {
+ ep@0 {
reg = <0>;
atmel,fifo-size = <64>;
atmel,nb-banks = <1>;
};
- ep1 {
+ ep@1 {
reg = <1>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <3>;
atmel,can-isoc;
};
- ep2 {
+ ep@2 {
reg = <2>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <3>;
atmel,can-isoc;
};
- ep3 {
+ ep@3 {
reg = <3>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
atmel,can-dma;
};
- ep4 {
+ ep@4 {
reg = <4>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
atmel,can-dma;
};
- ep5 {
+ ep@5 {
reg = <5>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
atmel,can-dma;
};
- ep6 {
+ ep@6 {
reg = <6>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
atmel,can-dma;
};
- ep7 {
+ ep@7 {
reg = <7>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
atmel,can-dma;
};
- ep8 {
+ ep@8 {
reg = <8>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
};
- ep9 {
+ ep@9 {
reg = <9>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
};
- ep10 {
+ ep@10 {
reg = <10>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
};
- ep11 {
+ ep@11 {
reg = <11>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
};
- ep12 {
+ ep@12 {
reg = <12>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
};
- ep13 {
+ ep@13 {
reg = <13>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
};
- ep14 {
+ ep@14 {
reg = <14>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
};
- ep15 {
+ ep@15 {
reg = <15>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
clock-names = "pclk", "hclk";
status = "disabled";
- ep0 {
+ ep@0 {
reg = <0>;
atmel,fifo-size = <64>;
atmel,nb-banks = <1>;
};
- ep1 {
+ ep@1 {
reg = <1>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <3>;
atmel,can-isoc;
};
- ep2 {
+ ep@2 {
reg = <2>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <3>;
atmel,can-isoc;
};
- ep3 {
+ ep@3 {
reg = <3>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
atmel,can-isoc;
};
- ep4 {
+ ep@4 {
reg = <4>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
atmel,can-isoc;
};
- ep5 {
+ ep@5 {
reg = <5>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
atmel,can-isoc;
};
- ep6 {
+ ep@6 {
reg = <6>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
atmel,can-isoc;
};
- ep7 {
+ ep@7 {
reg = <7>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
atmel,can-isoc;
};
- ep8 {
+ ep@8 {
reg = <8>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
atmel,can-isoc;
};
- ep9 {
+ ep@9 {
reg = <9>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
atmel,can-isoc;
};
- ep10 {
+ ep@10 {
reg = <10>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
atmel,can-isoc;
};
- ep11 {
+ ep@11 {
reg = <11>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
atmel,can-isoc;
};
- ep12 {
+ ep@12 {
reg = <12>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
atmel,can-isoc;
};
- ep13 {
+ ep@13 {
reg = <13>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
atmel,can-isoc;
};
- ep14 {
+ ep@14 {
reg = <14>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
atmel,can-isoc;
};
- ep15 {
+ ep@15 {
reg = <15>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;