drm/vc4: Fix the name of the VSYNCD_EVEN register.

It's used for delaying vsync in interlaced mode.

Signed-off-by: Eric Anholt <eric@anholt.net>

diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
index 989ee728e2b0761c30448873b22c7acea373a031..5e84be2e97d01f116065fe4efc56e18702fdc122 100644 (file)
--- a/drivers/gpu/drm/vc4/vc4_crtc.c
+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
@@ -83,7 +83,7 @@ static const struct {
 } crtc_regs[] = {
        CRTC_REG(PV_CONTROL),
        CRTC_REG(PV_V_CONTROL),
-       CRTC_REG(PV_VSYNCD),
+       CRTC_REG(PV_VSYNCD_EVEN),
        CRTC_REG(PV_HORZA),
        CRTC_REG(PV_HORZB),
        CRTC_REG(PV_VERTA),

diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h
index 85c36d238669b5c1325e3db5d39e0fd91fbbbc9c..d529665d43cd57c326481a64bb84993ea3c453f3 100644 (file)
--- a/drivers/gpu/drm/vc4/vc4_regs.h
+++ b/drivers/gpu/drm/vc4/vc4_regs.h
@@ -187,7 +187,7 @@
 # define PV_VCONTROL_CONTINUOUS                        BIT(1)
 # define PV_VCONTROL_VIDEN                     BIT(0)
 
-#define PV_VSYNCD                              0x08
+#define PV_VSYNCD_EVEN                         0x08
 
 #define PV_HORZA                               0x0c
 # define PV_HORZA_HBP_MASK                     VC4_MASK(31, 16)