/* HDMI PLL funcs */
int hdmi_pll_enable(struct hdmi_pll_data *pll);
void hdmi_pll_disable(struct hdmi_pll_data *pll);
+int hdmi_pll_set_config(struct hdmi_pll_data *pll);
void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s);
void hdmi_pll_compute(struct hdmi_pll_data *pll, unsigned long clkin,
unsigned long target_tmds);
hdmi_pll_compute(&hdmi.pll, clk_get_rate(hdmi.sys_clk), p->pixelclock);
- /* config the PLL and PHY hdmi_set_pll_pwrfirst */
r = hdmi_pll_enable(&hdmi.pll);
if (r) {
- DSSDBG("Failed to lock PLL\n");
+ DSSERR("Failed to enable PLL\n");
goto err_pll_enable;
}
+ r = hdmi_pll_set_config(&hdmi.pll);
+ if (r) {
+ DSSERR("Failed to configure PLL\n");
+ goto err_pll_cfg;
+ }
+
r = hdmi_phy_configure(&hdmi.phy, hdmi.pll.info.clkdco,
hdmi.pll.info.clkout);
if (r) {
err_phy_cfg:
hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);
err_phy_pwr:
+err_pll_cfg:
hdmi_pll_disable(&hdmi.pll);
err_pll_enable:
hdmi_power_off_core(dssdev);
hdmi_wp_set_irqstatus(&hdmi.wp,
hdmi_wp_get_irqstatus(&hdmi.wp));
- /* config the PLL and PHY hdmi_set_pll_pwrfirst */
r = hdmi_pll_enable(&hdmi.pll);
if (r) {
- DSSDBG("Failed to lock PLL\n");
+ DSSERR("Failed to enable PLL\n");
goto err_pll_enable;
}
+ r = hdmi_pll_set_config(&hdmi.pll);
+ if (r) {
+ DSSERR("Failed to configure PLL\n");
+ goto err_pll_cfg;
+ }
+
r = hdmi_phy_configure(&hdmi.phy, hdmi.pll.info.clkdco,
hdmi.pll.info.clkout);
if (r) {
hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);
err_phy_pwr:
err_phy_cfg:
+err_pll_cfg:
hdmi_pll_disable(&hdmi.pll);
err_pll_enable:
hdmi_power_off_core(dssdev);
pi->clkout = clkout;
}
-static int hdmi_pll_config(struct hdmi_pll_data *pll)
+int hdmi_pll_set_config(struct hdmi_pll_data *pll)
{
u32 r;
struct hdmi_pll_info *fmt = &pll->info;
if (r)
return r;
- r = hdmi_pll_config(pll);
- if (r)
- return r;
-
return 0;
}