Looks like some boards are calling gpio_request from init_irq.
This will make the request_irq fail, as GPIO will be initialized
as postcore_initcall.
Reported-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
},
};
+static void __init fsample_init_smc91x(void)
+{
+ fpga_write(1, H2P2_DBG_FPGA_LAN_RESET);
+ mdelay(50);
+ fpga_write(fpga_read(H2P2_DBG_FPGA_LAN_RESET) & ~1,
+ H2P2_DBG_FPGA_LAN_RESET);
+ mdelay(50);
+}
+
static struct mtd_partition nor_partitions[] = {
/* bootloader (U-Boot, etc) in first sector */
{
static void __init omap_fsample_init(void)
{
+ fsample_init_smc91x();
+
if (gpio_request(FSAMPLE_NAND_RB_GPIO_PIN, "NAND ready") < 0)
BUG();
gpio_direction_input(FSAMPLE_NAND_RB_GPIO_PIN);
omap_register_i2c_bus(1, 100, NULL, 0);
}
-static void __init fsample_init_smc91x(void)
-{
- fpga_write(1, H2P2_DBG_FPGA_LAN_RESET);
- mdelay(50);
- fpga_write(fpga_read(H2P2_DBG_FPGA_LAN_RESET) & ~1,
- H2P2_DBG_FPGA_LAN_RESET);
- mdelay(50);
-}
-
static void __init omap_fsample_init_irq(void)
{
omap1_init_common_hw();
omap_init_irq();
omap_gpio_init();
- fsample_init_smc91x();
}
/* Only FPGA needs to be mapped here. All others are done with ioremap */
omap1_init_common_hw();
omap_init_irq();
omap_gpio_init();
- h2_init_smc91x();
}
static struct omap_usb_config h2_usb_config __initdata = {
static void __init h2_init(void)
{
+ h2_init_smc91x();
+
/* Here we assume the NOR boot config: NOR on CS3 (possibly swapped
* to address 0 by a dip switch), NAND on CS2B. The NAND driver will
* notice whether a NAND chip is enabled at probe time.
.resource = smc91x_resources,
};
+static void __init h3_init_smc91x(void)
+{
+ omap_cfg_reg(W15_1710_GPIO40);
+ if (gpio_request(40, "SMC91x irq") < 0) {
+ printk("Error requesting gpio 40 for smc91x irq\n");
+ return;
+ }
+}
+
#define GPTIMER_BASE 0xFFFB1400
#define GPTIMER_REGS(x) (0xFFFB1400 + (x * 0x800))
#define GPTIMER_REGS_SIZE 0x46
static void __init h3_init(void)
{
+ h3_init_smc91x();
+
/* Here we assume the NOR boot config: NOR on CS3 (possibly swapped
* to address 0 by a dip switch), NAND on CS2B. The NAND driver will
* notice whether a NAND chip is enabled at probe time.
h3_mmc_init();
}
-static void __init h3_init_smc91x(void)
-{
- omap_cfg_reg(W15_1710_GPIO40);
- if (gpio_request(40, "SMC91x irq") < 0) {
- printk("Error requesting gpio 40 for smc91x irq\n");
- return;
- }
-}
-
static void __init h3_init_irq(void)
{
omap1_init_common_hw();
omap_init_irq();
omap_gpio_init();
- h3_init_smc91x();
}
static void __init h3_map_io(void)
omap1510_fpga_init_irq();
}
#endif
- innovator_init_smc91x();
}
#ifdef CONFIG_ARCH_OMAP15XX
static void __init innovator_init(void)
{
+ innovator_init_smc91x();
+
#ifdef CONFIG_ARCH_OMAP15XX
if (cpu_is_omap1510()) {
unsigned char reg;
omap1_init_common_hw();
omap_init_irq();
omap_gpio_init();
- osk_init_smc91x();
- osk_init_cf();
}
static struct omap_usb_config osk_usb_config __initdata = {
{
u32 l;
+ osk_init_smc91x();
+ osk_init_cf();
+
/* Workaround for wrong CS3 (NOR flash) timing
* There are some U-Boot versions out there which configure
* wrong CS3 memory timings. This mainly leads to CRC
{ OMAP_TAG_LCD, &perseus2_lcd_config },
};
+static void __init perseus2_init_smc91x(void)
+{
+ fpga_write(1, H2P2_DBG_FPGA_LAN_RESET);
+ mdelay(50);
+ fpga_write(fpga_read(H2P2_DBG_FPGA_LAN_RESET) & ~1,
+ H2P2_DBG_FPGA_LAN_RESET);
+ mdelay(50);
+}
+
static void __init omap_perseus2_init(void)
{
+ perseus2_init_smc91x();
+
if (gpio_request(P2_NAND_RB_GPIO_PIN, "NAND ready") < 0)
BUG();
gpio_direction_input(P2_NAND_RB_GPIO_PIN);
omap_register_i2c_bus(1, 100, NULL, 0);
}
-static void __init perseus2_init_smc91x(void)
-{
- fpga_write(1, H2P2_DBG_FPGA_LAN_RESET);
- mdelay(50);
- fpga_write(fpga_read(H2P2_DBG_FPGA_LAN_RESET) & ~1,
- H2P2_DBG_FPGA_LAN_RESET);
- mdelay(50);
-}
-
static void __init omap_perseus2_init_irq(void)
{
omap1_init_common_hw();
omap_init_irq();
omap_gpio_init();
- perseus2_init_smc91x();
}
/* Only FPGA needs to be mapped here. All others are done with ioremap */
static struct map_desc omap_perseus2_io_desc[] __initdata = {
omap2_init_common_hw(NULL, NULL);
omap_init_irq();
omap_gpio_init();
- apollon_init_smc91x();
}
static void __init apollon_led_init(void)
omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAC);
+ apollon_init_smc91x();
apollon_led_init();
apollon_flash_init();
apollon_usb_init();
omap2_init_common_hw(NULL, NULL);
omap_init_irq();
omap_gpio_init();
- ldp_init_smsc911x();
}
static struct twl4030_usb_data ldp_usb_data = {
static void __init omap_ldp_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
+ ldp_init_smsc911x();
omap_i2c_init();
platform_add_devices(ldp_devices, ARRAY_SIZE(ldp_devices));
ts_gpio = 54;