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clk: renesas: r8a7796: Add USB3.0 clock
authorHiromitsu Yamasaki <hiromitsu.yamasaki.ym@renesas.com>
Wed, 26 Jul 2017 11:23:39 +0000 (20:23 +0900)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Thu, 17 Aug 2017 07:22:26 +0000 (09:22 +0200)
This patch adds USB3.0-IF0 clock for R8A7796 SoC.

Signed-off-by: Hiromitsu Yamasaki <hiromitsu.yamasaki.ym@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r8a7796-cpg-mssr.c patch | blob | blame | history

diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index 22ba3c497aba970136f94bc9923f4b80fe1b0398..e5e7fb212288c3779dfa09ed0f001ee3f77b4408 100644 (file)
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -138,6 +138,7 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
        DEF_MOD("sdif0",                 314,   R8A7796_CLK_SD0),
        DEF_MOD("pcie1",                 318,   R8A7796_CLK_S3D1),
        DEF_MOD("pcie0",                 319,   R8A7796_CLK_S3D1),
+       DEF_MOD("usb3-if0",              328,   R8A7796_CLK_S3D1),
        DEF_MOD("usb-dmac0",             330,   R8A7796_CLK_S3D1),
        DEF_MOD("usb-dmac1",             331,   R8A7796_CLK_S3D1),
        DEF_MOD("rwdt",                  402,   R8A7796_CLK_R),