phy: apply 2+2 lane mode, CLK2 selection for 0502/0001

Change-Id: I7f831bd58e369288a24716efb5f4351d7b286698
Signed-off-by: Jeongtae Park <jtp.park@samsung.com>

diff --git a/drivers/phy/samsung/phy-exynos-mipi.c b/drivers/phy/samsung/phy-exynos-mipi.c
index d2dfbd925ab525da08f94c6b14ee0973ff92f674..d87fd2d6380b1c28a5a68bbf4dd65be3cd3b805d 100644 (file)
--- a/drivers/phy/samsung/phy-exynos-mipi.c
+++ b/drivers/phy/samsung/phy-exynos-mipi.c
@@ -382,6 +382,8 @@ static int __set_phy_cfg_0502_0001_dphy(void __iomem *regs, int option, u32 *cfg
                writel(0x00009000, regs + 0x000c + (i * 0x100)); /* SD_ANA_CON1 */
                writel(0x00000005, regs + 0x0010 + (i * 0x100)); /* SD_ANA_CON2 */
                update_bits(regs + 0x0010 + (i * 0x100), 8, 2, skew_delay_sel); /* SD_ANA_CON2 */
+               update_bits(regs + 0x0010 + (i * 0x100), 15, 1, 1); /* RESETN_CFG_SEL */
+               update_bits(regs + 0x0010 + (i * 0x100), 7, 1, 1); /* RXDDRCLKHS_SEL */
                writel(0x00000600, regs + 0x0014 + (i * 0x100)); /* SD_ANA_CON3 */
                update_bits(regs + 0x0030 + (i * 0x100), 0, 8, cfg[SETTLE]); /* SD_TIME_CON0 */
                update_bits(regs + 0x0030 + (i * 0x100), 8, 1, settle_clk_sel); /* SD_TIME_CON0 */