sky2: support Yukon EC_U rev B1 and later

Need to change logic to support later versions of Yukon 2 EC_U chip.

Signed-off-by: Stephen Hemminger <shemminger@vyatta.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/sky2.c b/drivers/net/sky2.c
index d8ec4c11fd49fec6a52bab0b8914cd1749419644..4b403bd7870d946ed7b0bef37f687f315a2ff102 100644 (file)
--- a/drivers/net/sky2.c
+++ b/drivers/net/sky2.c
@@ -877,6 +877,10 @@ static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
        if (hw->dev[port]->mtu > ETH_DATA_LEN)
                reg |= GM_SMOD_JUMBO_ENA;
 
+       if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
+           hw->chip_rev == CHIP_REV_YU_EC_U_B1)
+               reg |= GM_NEW_FLOW_CTRL;
+
        gma_write16(hw, port, GM_SERIAL_MODE, reg);
 
        /* virtual address for data */
@@ -1413,8 +1417,7 @@ static void sky2_rx_start(struct sky2_port *sky2)
        /* These chips have no ram buffer?
         * MAC Rx RAM Read is controlled by hardware */
        if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
-           (hw->chip_rev == CHIP_REV_YU_EC_U_A1 ||
-            hw->chip_rev == CHIP_REV_YU_EC_U_B0))
+           hw->chip_rev > CHIP_REV_YU_EC_U_A0)
                sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
 
        sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);

diff --git a/drivers/net/sky2.h b/drivers/net/sky2.h
index a5e182dd981980f3798f2702f87a7a6e5a0f61af..1c4d6a3d97cc833529edf0ab74441f7822906d76 100644 (file)
--- a/drivers/net/sky2.h
+++ b/drivers/net/sky2.h
@@ -557,6 +557,7 @@ enum yukon_ec_u_rev {
        CHIP_REV_YU_EC_U_A0  = 1,
        CHIP_REV_YU_EC_U_A1  = 2,
        CHIP_REV_YU_EC_U_B0  = 3,
+       CHIP_REV_YU_EC_U_B1  = 5,
 };
 enum yukon_fe_rev {
        CHIP_REV_YU_FE_A1    = 1,
@@ -1775,10 +1776,13 @@ enum {
 /*     GM_SERIAL_MODE                  16 bit r/w      Serial Mode Register */
 enum {
        GM_SMOD_DATABL_MSK      = 0x1f<<11, /* Bit 15..11:      Data Blinder (r/o) */
-       GM_SMOD_LIMIT_4         = 1<<10, /* Bit 10:     4 consecutive Tx trials */
-       GM_SMOD_VLAN_ENA        = 1<<9, /* Bit  9:      Enable VLAN  (Max. Frame Len) */
-       GM_SMOD_JUMBO_ENA       = 1<<8, /* Bit  8:      Enable Jumbo (Max. Frame Len) */
-        GM_SMOD_IPG_MSK        = 0x1f  /* Bit 4..0:    Inter-Packet Gap (IPG) */
+       GM_SMOD_LIMIT_4         = 1<<10, /* 4 consecutive Tx trials */
+       GM_SMOD_VLAN_ENA        = 1<<9,  /* Enable VLAN  (Max. Frame Len) */
+       GM_SMOD_JUMBO_ENA       = 1<<8,  /* Enable Jumbo (Max. Frame Len) */
+
+       GM_NEW_FLOW_CTRL        = 1<<6,  /* Enable New Flow-Control */
+
+       GM_SMOD_IPG_MSK         = 0x1f   /* Bit 4..0:   Inter-Packet Gap (IPG) */
 };
 
 #define DATA_BLIND_VAL(x)      (((x)<<11) & GM_SMOD_DATABL_MSK)