drm/i915: Enable CB tuning of the Display PLL
authorChris Wilson <chris@chris-wilson.co.uk>
Fri, 3 Dec 2010 21:35:48 +0000 (21:35 +0000)
committerChris Wilson <chris@chris-wilson.co.uk>
Sun, 5 Dec 2010 00:37:36 +0000 (00:37 +0000)
Magic numbers from the specs. This is supposed to allow the PLL some
variance to improve jitter performance and VCO headroom across
manufacturing and environmental variations.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_display.c

index 998457063d5e0bf8bbcf7c591753ce033b5f0442..06175e98c5bbee52dea454423cbcd65c941c62da 100644 (file)
 #define PCH_DPLL(pipe) _PIPE(pipe, PCH_DPLL_A, PCH_DPLL_B)
 
 #define PCH_FPA0                0xc6040
+#define  FP_CB_TUNE            (0x3<<22)
 #define PCH_FPA1                0xc6044
 #define PCH_FPB0                0xc6048
 #define PCH_FPB1                0xc604c
index e3b8d0dc7a7d930782d210f239095df46b2a2c37..f2aa76bd72c0406c72e01284d83ce0356644eeef 100644 (file)
@@ -3857,6 +3857,22 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
                                reduced_clock.m2;
        }
 
+       /* Enable autotuning of the PLL clock (if permissible) */
+       if (HAS_PCH_SPLIT(dev)) {
+               int factor = 21;
+
+               if (is_lvds) {
+                       if ((dev_priv->lvds_use_ssc &&
+                            dev_priv->lvds_ssc_freq == 100) ||
+                           (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
+                               factor = 25;
+               } else if (is_sdvo && is_tv)
+                       factor = 20;
+
+               if (clock.m1 < factor * clock.n)
+                       fp |= FP_CB_TUNE;
+       }
+
        dpll = 0;
        if (!HAS_PCH_SPLIT(dev))
                dpll = DPLL_VGA_MODE_DIS;
@@ -4071,7 +4087,6 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
        }
 
        if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
-               I915_WRITE(fp_reg, fp);
                I915_WRITE(dpll_reg, dpll);
 
                /* Wait for the clocks to stabilize. */