ARM64: dts: meson-gxl: add i2s output pins

Add EE and AO domains pins for the i2s output clocks and data the gxl
device tree

Acked-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>

diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
index 32bbc4f24fa97aa5c35d0dc876238fbeefceb6fc..79c230b12fffb8d55634fe298a0cc65da537468e 100644 (file)
--- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
@@ -161,6 +161,20 @@
                                function = "pwm_ao_b";
                        };
                };
+
+               i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
+                       mux {
+                               groups = "i2s_out_ch23_ao";
+                               function = "i2s_out_ao";
+                       };
+               };
+
+               i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
+                       mux {
+                               groups = "i2s_out_ch45_ao";
+                               function = "i2s_out_ao";
+                       };
+               };
        };
 };
 
@@ -387,6 +401,54 @@
                                function = "hdmi_i2c";
                        };
                };
+
+               i2s_am_clk_pins: i2s_am_clk {
+                       mux {
+                               groups = "i2s_am_clk";
+                               function = "i2s_out";
+                       };
+               };
+
+               i2s_out_ao_clk_pins: i2s_out_ao_clk {
+                       mux {
+                               groups = "i2s_out_ao_clk";
+                               function = "i2s_out";
+                       };
+               };
+
+               i2s_out_lr_clk_pins: i2s_out_lr_clk {
+                       mux {
+                               groups = "i2s_out_lr_clk";
+                               function = "i2s_out";
+                       };
+               };
+
+               i2s_out_ch01_pins: i2s_out_ch01 {
+                       mux {
+                               groups = "i2s_out_ch01";
+                               function = "i2s_out";
+                       };
+               };
+               i2sout_ch23_z_pins: i2sout_ch23_z {
+                       mux {
+                               groups = "i2sout_ch23_z";
+                               function = "i2s_out";
+                       };
+               };
+
+               i2sout_ch45_z_pins: i2sout_ch45_z {
+                       mux {
+                               groups = "i2sout_ch45_z";
+                               function = "i2s_out";
+                       };
+               };
+
+               i2sout_ch67_z_pins: i2sout_ch67_z {
+                       mux {
+                               groups = "i2sout_ch67_z";
+                               function = "i2s_out";
+                       };
+               };
        };
 
        eth-phy-mux {