rtl8xxxu: Reorder parts of init code to match the 8192eu vendor code flow

In order to debug 8192eu support, reorder some init code to match the
flow of the vendor driver.

Signed-off-by: Jes Sorensen <Jes.Sorensen@redhat.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>

diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.c
index e36fda8c1ad3393b003f8b2b11cc57f9c9d4aa5c..d67b88665194ab0c17aa5bbc31529e866278a5f9 100644 (file)
--- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.c
+++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.c
@@ -7592,6 +7592,26 @@ static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
        if (ret)
                goto exit;
 
+       /* RFSW Control - clear bit 14 ?? */
+       if (priv->rtl_chip != RTL8723B)
+               rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003);
+       /* 0x07000760 */
+       if (priv->rtl_chip == RTL8192E) {
+               val32 = 0;
+       } else {
+               val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW |
+                       FPGA0_RF_ANTSWB | FPGA0_RF_PAPE |
+                       ((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB | FPGA0_RF_PAPE) <<
+                        FPGA0_RF_BD_CTRL_SHIFT);
+       }
+       rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
+       /* 0x860[6:5]= 00 - why? - this sets antenna B */
+       if (priv->rtl_chip != RTL8192E)
+               rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66f60210);
+
+       priv->rf_mode_ag[0] = rtl8xxxu_read_rfreg(priv, RF_A,
+                                                 RF6052_REG_MODE_AG);
+
        /*
         * Chip specific quirks
         */
@@ -7653,21 +7673,6 @@ static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
        if (ret)
                goto exit;
 
-       /* RFSW Control - clear bit 14 ?? */
-       if (priv->rtl_chip != RTL8723B)
-               rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003);
-       /* 0x07000760 */
-       val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW |
-               FPGA0_RF_ANTSWB | FPGA0_RF_PAPE |
-               ((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB | FPGA0_RF_PAPE) <<
-                FPGA0_RF_BD_CTRL_SHIFT);
-       rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
-       /* 0x860[6:5]= 00 - why? - this sets antenna B */
-       rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66F60210);
-
-       priv->rf_mode_ag[0] = rtl8xxxu_read_rfreg(priv, RF_A,
-                                                 RF6052_REG_MODE_AG);
-
        /*
         * Set RX page boundary
         */