arm64: Extend workaround for erratum 1024718 to all versions of Cortex-A55

commit c0b15c25d25171db4b70cc0b7dbc1130ee94017d upstream.

The erratum 1024718 affects Cortex-A55 r0p0 to r2p0. However
we apply the work around for r0p0 - r1p0. Unfortunately this
won't be fixed for the future revisions for the CPU. Thus
extend the work around for all versions of A55, to cover
for r2p0 and any future revisions.

Cc: stable@vger.kernel.org
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: James Morse <james.morse@arm.com>
Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20210203230057.3961239-1-suzuki.poulose@arm.com
[will: Update Kconfig help text]
Signed-off-by: Will Deacon <will@kernel.org>
[Nanyon: adjust for stable version below v4.16, which set TCR_HD earlier
in assembly code]
Signed-off-by: Nanyong Sun <sunnanyong@huawei.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index e296ae3e20f48898ba36ec1575f52403e0ffe2a1..e76f74874a4201d6523f2296654f4acbb0e0dae6 100644 (file)
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -450,7 +450,7 @@ config ARM64_ERRATUM_1024718
        help
          This option adds work around for Arm Cortex-A55 Erratum 1024718.
 
-         Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
+         Affected Cortex-A55 cores (all revisions) could cause incorrect
          update of the hardware dirty bit when the DBM/AP bits are updated
          without a break-before-make. The work around is to disable the usage
          of hardware DBM locally on the affected cores. CPUs not affected by

diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
index ecbc060807d2c7238aaa2b84b6ca8410a35ca0a3..a9ff7fb4183200b62a80f8307994bc4b7cae2701 100644 (file)
--- a/arch/arm64/mm/proc.S
+++ b/arch/arm64/mm/proc.S
@@ -455,8 +455,8 @@ ENTRY(__cpu_setup)
        cmp     x9, #2
        b.lt    1f
 #ifdef CONFIG_ARM64_ERRATUM_1024718
-       /* Disable hardware DBM on Cortex-A55 r0p0, r0p1 & r1p0 */
-       cpu_midr_match MIDR_CORTEX_A55, MIDR_CPU_VAR_REV(0, 0), MIDR_CPU_VAR_REV(1, 0), x1, x2, x3, x4
+       /* Disable hardware DBM on Cortex-A55 all versions */
+       cpu_midr_match MIDR_CORTEX_A55, MIDR_CPU_VAR_REV(0, 0), MIDR_CPU_VAR_REV(0xf, 0xf), x1, x2, x3, x4
        cbnz    x1, 1f
 #endif
        orr     x10, x10, #TCR_HD               // hardware Dirty flag update