#endif
/* Sonics side: PCI core and host control registers */
-typedef struct sbpciregs {
+struct sbpciregs {
u32 control; /* PCI control */
u32 PAD[3];
u32 arbcontrol; /* PCI arbiter control */
u32 pcicfg[4][64]; /* 0x400 - 0x7FF, PCI Cfg Space (>=rev8) */
u16 sprom[36]; /* SPROM shadow Area */
u32 PAD[46];
-} sbpciregs_t;
+};
#endif /* _LANGUAGE_ASSEMBLY */
typedef struct {
union {
sbpcieregs_t *pcieregs;
- sbpciregs_t *pciregs;
+ struct sbpciregs *pciregs;
} regs; /* Memory mapped register to the core */
si_t *sih; /* System interconnect handle */
ASSERT(cap_ptr);
pi->pciecap_lcreg_offset = cap_ptr + PCIE_CAP_LINKCTRL_OFFSET;
} else
- pi->regs.pciregs = (sbpciregs_t *) regs;
+ pi->regs.pciregs = (struct sbpciregs *) regs;
return pi;
}
void si_pci_setup(si_t *sih, uint coremask)
{
si_info_t *sii;
- sbpciregs_t *pciregs = NULL;
+ struct sbpciregs *pciregs = NULL;
u32 siflag = 0, w;
uint idx = 0;
siflag = si_flag(sih);
/* switch over to pci core */
- pciregs =
- (sbpciregs_t *) si_setcoreidx(sih, sii->pub.buscoreidx);
+ pciregs = (struct sbpciregs *)si_setcoreidx(sih, sii->pub.buscoreidx);
}
/*
int si_pci_fixcfg(si_t *sih)
{
uint origidx, pciidx;
- sbpciregs_t *pciregs = NULL;
+ struct sbpciregs *pciregs = NULL;
sbpcieregs_t *pcieregs = NULL;
void *regs = NULL;
u16 val16, *reg16 = NULL;
ASSERT(pcieregs != NULL);
reg16 = &pcieregs->sprom[SRSH_PI_OFFSET];
} else if (sii->pub.buscoretype == PCI_CORE_ID) {
- pciregs = (sbpciregs_t *) si_setcore(&sii->pub, PCI_CORE_ID, 0);
+ pciregs = (struct sbpciregs *)si_setcore(&sii->pub, PCI_CORE_ID, 0);
regs = pciregs;
ASSERT(pciregs != NULL);
reg16 = &pciregs->sprom[SRSH_PI_OFFSET];