static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
int amount_pull, struct napi_struct *napi);
-void gfar_halt(struct net_device *dev);
-static void gfar_halt_nodisable(struct net_device *dev);
-void gfar_start(struct net_device *dev);
+static void gfar_halt_nodisable(struct gfar_private *priv);
static void gfar_clear_exact_match(struct net_device *dev);
static void gfar_set_mac_for_addr(struct net_device *dev, int num,
const u8 *addr);
/* Program the interrupt steering regs, only for MG devices */
if (priv->num_grps > 1)
gfar_write_isrg(priv);
-
- /* Enable all Rx/Tx queues after MAC reset */
- gfar_write(®s->rqueue, priv->rqueue);
- gfar_write(®s->tqueue, priv->tqueue);
}
static void __init gfar_init_addr_hash_table(struct gfar_private *priv)
/* Stop the DMA engine now, in case it was running before
* (The firmware could have used it, and left it running).
*/
- gfar_halt(dev);
+ gfar_halt(priv);
gfar_hw_init(priv);
lock_tx_qs(priv);
lock_rx_qs(priv);
- gfar_halt_nodisable(ndev);
+ gfar_halt_nodisable(priv);
/* Disable Tx, and Rx if wake-on-LAN is disabled. */
tempval = gfar_read(®s->maccfg1);
tempval &= ~MACCFG2_MPEN;
gfar_write(®s->maccfg2, tempval);
- gfar_start(ndev);
+ gfar_start(priv);
unlock_rx_qs(priv);
unlock_tx_qs(priv);
init_registers(ndev);
gfar_set_mac_address(ndev);
gfar_init_mac(ndev);
- gfar_start(ndev);
+ gfar_start(priv);
priv->oldlink = 0;
priv->oldspeed = 0;
}
/* Halt the receive and transmit queues */
-static void gfar_halt_nodisable(struct net_device *dev)
+static void gfar_halt_nodisable(struct gfar_private *priv)
{
- struct gfar_private *priv = netdev_priv(dev);
struct gfar __iomem *regs = priv->gfargrp[0].regs;
u32 tempval;
}
/* Halt the receive and transmit queues */
-void gfar_halt(struct net_device *dev)
+void gfar_halt(struct gfar_private *priv)
{
- struct gfar_private *priv = netdev_priv(dev);
struct gfar __iomem *regs = priv->gfargrp[0].regs;
u32 tempval;
- gfar_halt_nodisable(dev);
+ /* Dissable the Rx/Tx hw queues */
+ gfar_write(®s->rqueue, 0);
+ gfar_write(®s->tqueue, 0);
- /* Disable Rx and Tx */
+ mdelay(10);
+
+ gfar_halt_nodisable(priv);
+
+ /* Disable Rx/Tx DMA */
tempval = gfar_read(®s->maccfg1);
tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
gfar_write(®s->maccfg1, tempval);
lock_tx_qs(priv);
lock_rx_qs(priv);
- gfar_halt(dev);
+ gfar_halt(priv);
unlock_rx_qs(priv);
unlock_tx_qs(priv);
priv->tx_queue[0]->tx_bd_dma_base);
}
-void gfar_start(struct net_device *dev)
+void gfar_start(struct gfar_private *priv)
{
- struct gfar_private *priv = netdev_priv(dev);
struct gfar __iomem *regs = priv->gfargrp[0].regs;
u32 tempval;
int i = 0;
- /* Enable Rx and Tx in MACCFG1 */
- tempval = gfar_read(®s->maccfg1);
- tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
- gfar_write(®s->maccfg1, tempval);
+ /* Enable Rx/Tx hw queues */
+ gfar_write(®s->rqueue, priv->rqueue);
+ gfar_write(®s->tqueue, priv->tqueue);
/* Initialize DMACTRL to have WWR and WOP */
tempval = gfar_read(®s->dmactrl);
gfar_write(®s->rstat, priv->gfargrp[i].rstat);
}
+ /* Enable Rx/Tx DMA */
+ tempval = gfar_read(®s->maccfg1);
+ tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
+ gfar_write(®s->maccfg1, tempval);
+
gfar_ints_enable(priv);
- dev->trans_start = jiffies; /* prevent tx timeout */
+ priv->ndev->trans_start = jiffies; /* prevent tx timeout */
}
static void gfar_configure_coalescing(struct gfar_private *priv,
}
/* Start the controller */
- gfar_start(ndev);
+ gfar_start(priv);
phy_start(priv->phydev);