#define CLK_SRC_PLL 1 /* FCLK_DIV2 */
#define CLK_SRC_PLL_RATE 1000000000
#define CLK_CORE_PHASE_MASK GENMASK(9, 8)
+#define CLK_TX_PHASE_MASK GENMASK(11, 10)
+#define CLK_RX_PHASE_MASK GENMASK(13, 12)
#define CLK_PHASE_0 0
#define CLK_PHASE_90 1
#define CLK_PHASE_180 2
#define SD_EMMC_CFG_CMD_GAP 16 /* in clock cycles */
#define MUX_CLK_NUM_PARENTS 2
+struct meson_tuning_params {
+ u8 core_phase;
+ u8 tx_phase;
+ u8 rx_phase;
+};
+
struct meson_host {
struct device *dev;
struct mmc_host *mmc;
void *bounce_buf;
dma_addr_t bounce_dma_addr;
+ struct meson_tuning_params tp;
bool vqmmc_enabled;
};
/* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
clk_reg = 0;
- clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
+ clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, host->tp.core_phase);
+ clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, host->tp.tx_phase);
+ clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, host->tp.rx_phase);
clk_reg |= FIELD_PREP(CLK_SRC_MASK, CLK_SRC_XTAL);
clk_reg |= FIELD_PREP(CLK_DIV_MASK, CLK_DIV_MAX);
clk_reg &= ~CLK_ALWAYS_ON;
if (ret)
goto free_host;
+ host->tp.core_phase = CLK_PHASE_180;
+ host->tp.tx_phase = CLK_PHASE_0;
+ host->tp.rx_phase = CLK_PHASE_0;
+
ret = meson_mmc_clk_init(host);
if (ret)
goto err_core_clk;