[POWERPC] 85xx: Add next-level-cache property

Added next-level-cache to the L1 and a reference to the new L2 label.
This is per the ePAPR 0.94 spec.  Since we are't really dependent on this
today we aren't supporting the "legacy" l2-cache phandle that is specified
in the PPC v2.1 OF Binding spec.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/arch/powerpc/boot/dts/ksi8560.dts b/arch/powerpc/boot/dts/ksi8560.dts
index f869ce3ca0b74193792acbaca1ec848c3cb28e4a..6eb7c771f6a456654f7e25b288edb7299cca1d60 100644 (file)
--- a/arch/powerpc/boot/dts/ksi8560.dts
+++ b/arch/powerpc/boot/dts/ksi8560.dts
@@ -40,6 +40,7 @@
                        timebase-frequency = <0>;               /* From U-boot */
                        bus-frequency = <0>;                    /* From U-boot */
                        clock-frequency = <0>;                  /* From U-boot */
+                       next-level-cache = <&L2>;
                };
        };
 
@@ -62,7 +63,7 @@
                        interrupts = <0x12 0x2>;
                };
 
-               l2-cache-controller@20000 {
+               L2: l2-cache-controller@20000 {
                        compatible = "fsl,8540-l2-cache-controller";
                        reg = <0x20000 0x1000>;
                        cache-line-size = <0x20>;               /* 32 bytes */

diff --git a/arch/powerpc/boot/dts/mpc8540ads.dts b/arch/powerpc/boot/dts/mpc8540ads.dts
index 58e165e8737391a93f4d488b5ca658ee7b4e04f8..79881a1fb8aa94e6053cd132c21eb80797092143 100644 (file)
--- a/arch/powerpc/boot/dts/mpc8540ads.dts
+++ b/arch/powerpc/boot/dts/mpc8540ads.dts
@@ -40,6 +40,7 @@
                        timebase-frequency = <0>;       //  33 MHz, from uboot
                        bus-frequency = <0>;    // 166 MHz
                        clock-frequency = <0>;  // 825 MHz, from uboot
+                       next-level-cache = <&L2>;
                };
        };
 
@@ -63,7 +64,7 @@
                        interrupts = <18 2>;
                };
 
-               l2-cache-controller@20000 {
+               L2: l2-cache-controller@20000 {
                        compatible = "fsl,8540-l2-cache-controller";
                        reg = <0x20000 0x1000>;
                        cache-line-size = <32>; // 32 bytes

diff --git a/arch/powerpc/boot/dts/mpc8541cds.dts b/arch/powerpc/boot/dts/mpc8541cds.dts
index 21ebe7cc454ac04fde23c80b7c7c31ae2337e4f2..66192aa0f311afaf71b9286f5d21a2c8b99677f1 100644 (file)
--- a/arch/powerpc/boot/dts/mpc8541cds.dts
+++ b/arch/powerpc/boot/dts/mpc8541cds.dts
@@ -40,6 +40,7 @@
                        timebase-frequency = <0>;       //  33 MHz, from uboot
                        bus-frequency = <0>;    // 166 MHz
                        clock-frequency = <0>;  // 825 MHz, from uboot
+                       next-level-cache = <&L2>;
                };
        };
 
@@ -63,7 +64,7 @@
                        interrupts = <18 2>;
                };
 
-               l2-cache-controller@20000 {
+               L2: l2-cache-controller@20000 {
                        compatible = "fsl,8541-l2-cache-controller";
                        reg = <0x20000 0x1000>;
                        cache-line-size = <32>; // 32 bytes

diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts b/arch/powerpc/boot/dts/mpc8544ds.dts
index 921f9f6848ea0b0530863e5e09aa55e24f4d91ba..6cf533f4b5fb94390d22c74454e868f19ff8991c 100644 (file)
--- a/arch/powerpc/boot/dts/mpc8544ds.dts
+++ b/arch/powerpc/boot/dts/mpc8544ds.dts
@@ -41,6 +41,7 @@
                        timebase-frequency = <0>;
                        bus-frequency = <0>;
                        clock-frequency = <0>;
+                       next-level-cache = <&L2>;
                };
        };
 
@@ -65,7 +66,7 @@
                        interrupts = <18 2>;
                };
 
-               l2-cache-controller@20000 {
+               L2: l2-cache-controller@20000 {
                        compatible = "fsl,8544-l2-cache-controller";
                        reg = <0x20000 0x1000>;
                        cache-line-size = <32>; // 32 bytes

diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
index 213c88e5aee801c7483ef76c092b651c59f3d5ed..205598d51f2560134f9d5939f171dc731c2cc410 100644 (file)
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ b/arch/powerpc/boot/dts/mpc8548cds.dts
@@ -45,6 +45,7 @@
                        timebase-frequency = <0>;       //  33 MHz, from uboot
                        bus-frequency = <0>;    // 166 MHz
                        clock-frequency = <0>;  // 825 MHz, from uboot
+                       next-level-cache = <&L2>;
                };
        };
 
@@ -68,7 +69,7 @@
                        interrupts = <18 2>;
                };
 
-               l2-cache-controller@20000 {
+               L2: l2-cache-controller@20000 {
                        compatible = "fsl,8548-l2-cache-controller";
                        reg = <0x20000 0x1000>;
                        cache-line-size = <32>; // 32 bytes

diff --git a/arch/powerpc/boot/dts/mpc8555cds.dts b/arch/powerpc/boot/dts/mpc8555cds.dts
index 400f6dbc3a86dce6eed352e286aaf24414ff5a57..7c9d0b16d7e567468a572380762ed1da4c3b011d 100644 (file)
--- a/arch/powerpc/boot/dts/mpc8555cds.dts
+++ b/arch/powerpc/boot/dts/mpc8555cds.dts
@@ -40,6 +40,7 @@
                        timebase-frequency = <0>;       //  33 MHz, from uboot
                        bus-frequency = <0>;    // 166 MHz
                        clock-frequency = <0>;  // 825 MHz, from uboot
+                       next-level-cache = <&L2>;
                };
        };
 
@@ -63,7 +64,7 @@
                        interrupts = <18 2>;
                };
 
-               l2-cache-controller@20000 {
+               L2: l2-cache-controller@20000 {
                        compatible = "fsl,8555-l2-cache-controller";
                        reg = <0x20000 0x1000>;
                        cache-line-size = <32>; // 32 bytes

diff --git a/arch/powerpc/boot/dts/mpc8560ads.dts b/arch/powerpc/boot/dts/mpc8560ads.dts
index f0b1f98a2df8ba8b12334ab1b77cb2f4f842c977..5d9f3c4b5b7147aaf6ef144ac8a01983ff4f5b96 100644 (file)
--- a/arch/powerpc/boot/dts/mpc8560ads.dts
+++ b/arch/powerpc/boot/dts/mpc8560ads.dts
@@ -64,7 +64,7 @@
                        interrupts = <18 2>;
                };
 
-               l2-cache-controller@20000 {
+               L2: l2-cache-controller@20000 {
                        compatible = "fsl,8540-l2-cache-controller";
                        reg = <0x20000 0x1000>;
                        cache-line-size = <32>; // 32 bytes

diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts
index d9064ee2d2d8d9226b28251f0aebe5b1c1c121d7..d7af8db1a22f1db51c4d47dc6a97961f05b0da3a 100644 (file)
--- a/arch/powerpc/boot/dts/mpc8568mds.dts
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts
@@ -42,6 +42,7 @@
                        timebase-frequency = <0>;
                        bus-frequency = <0>;
                        clock-frequency = <0>;
+                       next-level-cache = <&L2>;
                };
        };
 
@@ -70,7 +71,7 @@
                        interrupts = <18 2>;
                };
 
-               l2-cache-controller@20000 {
+               L2: l2-cache-controller@20000 {
                        compatible = "fsl,8568-l2-cache-controller";
                        reg = <0x20000 0x1000>;
                        cache-line-size = <32>; // 32 bytes

diff --git a/arch/powerpc/boot/dts/mpc8572ds.dts b/arch/powerpc/boot/dts/mpc8572ds.dts
index 3ca8cae493b605b7cba07926da63ec1e22b2cca7..a444e6a2387d381b2a174c5cd03bf959fd62615f 100644 (file)
--- a/arch/powerpc/boot/dts/mpc8572ds.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds.dts
@@ -42,6 +42,7 @@
                        timebase-frequency = <0>;
                        bus-frequency = <0>;
                        clock-frequency = <0>;
+                       next-level-cache = <&L2>;
                };
 
                PowerPC,8572@1 {
@@ -54,6 +55,7 @@
                        timebase-frequency = <0>;
                        bus-frequency = <0>;
                        clock-frequency = <0>;
+                       next-level-cache = <&L2>;
                };
        };
 
@@ -84,7 +86,7 @@
                        interrupts = <18 2>;
                };
 
-               l2-cache-controller@20000 {
+               L2: l2-cache-controller@20000 {
                        compatible = "fsl,mpc8572-l2-cache-controller";
                        reg = <0x20000 0x1000>;
                        cache-line-size = <32>; // 32 bytes

diff --git a/arch/powerpc/boot/dts/sbc8548.dts b/arch/powerpc/boot/dts/sbc8548.dts
index ce496fb27894dc51f786c0d7f7d9a204ab267cc7..d252e38283e78652872cca0897adffba3d79577a 100644 (file)
--- a/arch/powerpc/boot/dts/sbc8548.dts
+++ b/arch/powerpc/boot/dts/sbc8548.dts
@@ -44,6 +44,7 @@
                        timebase-frequency = <0>;       // From uboot
                        bus-frequency = <0>;
                        clock-frequency = <0>;
+                       next-level-cache = <&L2>;
                };
        };
 
@@ -161,7 +162,7 @@
                        interrupts = <0x12 0x2>;
                };
 
-               l2-cache-controller@20000 {
+               L2: l2-cache-controller@20000 {
                        compatible = "fsl,8548-l2-cache-controller";
                        reg = <0x20000 0x1000>;
                        cache-line-size = <0x20>;       // 32 bytes

diff --git a/arch/powerpc/boot/dts/sbc8560.dts b/arch/powerpc/boot/dts/sbc8560.dts
index 266350196cd21a44f891e49da13f9dc4ae0caabf..e556c5a4cf954746a933eef68276ba1d7240e77c 100644 (file)
--- a/arch/powerpc/boot/dts/sbc8560.dts
+++ b/arch/powerpc/boot/dts/sbc8560.dts
@@ -43,6 +43,7 @@
                        timebase-frequency = <0>;       // From uboot
                        bus-frequency = <0>;
                        clock-frequency = <0>;
+                       next-level-cache = <&L2>;
                };
        };
 
@@ -66,7 +67,7 @@
                        interrupts = <0x12 0x2>;
                };
 
-               l2-cache-controller@20000 {
+               L2: l2-cache-controller@20000 {
                        compatible = "fsl,8560-l2-cache-controller";
                        reg = <0x20000 0x1000>;
                        cache-line-size = <0x20>;       // 32 bytes

diff --git a/arch/powerpc/boot/dts/stx_gp3_8560.dts b/arch/powerpc/boot/dts/stx_gp3_8560.dts
index 096277b7192d8220bd6b40a4f3db4ad6e22fce88..1e612836b248063cfc2035f07724421d05576df9 100644 (file)
--- a/arch/powerpc/boot/dts/stx_gp3_8560.dts
+++ b/arch/powerpc/boot/dts/stx_gp3_8560.dts
@@ -38,6 +38,7 @@
                        timebase-frequency = <0>;
                        bus-frequency = <0>;
                        clock-frequency = <0>;
+                       next-level-cache = <&L2>;
                };
        };
 
@@ -62,7 +63,7 @@
                        interrupts = <18 2>;
                };
 
-               l2-cache-controller@20000 {
+               L2: l2-cache-controller@20000 {
                        compatible = "fsl,8540-l2-cache-controller";
                        reg = <0x20000 0x1000>;
                        cache-line-size = <32>;

diff --git a/arch/powerpc/boot/dts/tqm8540.dts b/arch/powerpc/boot/dts/tqm8540.dts
index 8ee4664c7490505f3f967723122efb6ad15241c2..7b653a583a2d02dbb204c982a46c9a3183684270 100644 (file)
--- a/arch/powerpc/boot/dts/tqm8540.dts
+++ b/arch/powerpc/boot/dts/tqm8540.dts
@@ -40,6 +40,7 @@
                        timebase-frequency = <0>;
                        bus-frequency = <0>;
                        clock-frequency = <0>;
+                       next-level-cache = <&L2>;
                };
        };
 
@@ -64,7 +65,7 @@
                        interrupts = <18 2>;
                };
 
-               l2-cache-controller@20000 {
+               L2: l2-cache-controller@20000 {
                        compatible = "fsl,8540-l2-cache-controller";
                        reg = <0x20000 0x1000>;
                        cache-line-size = <32>;

diff --git a/arch/powerpc/boot/dts/tqm8541.dts b/arch/powerpc/boot/dts/tqm8541.dts
index cadbebfd0edbf15324649c61e30f270f56f019d5..8fe73ef34195b76601c99484dd7dc828e964136d 100644 (file)
--- a/arch/powerpc/boot/dts/tqm8541.dts
+++ b/arch/powerpc/boot/dts/tqm8541.dts
@@ -39,6 +39,7 @@
                        timebase-frequency = <0>;
                        bus-frequency = <0>;
                        clock-frequency = <0>;
+                       next-level-cache = <&L2>;
                };
        };
 
@@ -63,7 +64,7 @@
                        interrupts = <18 2>;
                };
 
-               l2-cache-controller@20000 {
+               L2: l2-cache-controller@20000 {
                        compatible = "fsl,8540-l2-cache-controller";
                        reg = <0x20000 0x1000>;
                        cache-line-size = <32>;

diff --git a/arch/powerpc/boot/dts/tqm8555.dts b/arch/powerpc/boot/dts/tqm8555.dts
index 9d6dc04e8c406d230e081da6b6dc033b4d645501..0a53bb9ce76ff8e348eedf2a373bcb5cec2d6295 100644 (file)
--- a/arch/powerpc/boot/dts/tqm8555.dts
+++ b/arch/powerpc/boot/dts/tqm8555.dts
@@ -39,6 +39,7 @@
                        timebase-frequency = <0>;
                        bus-frequency = <0>;
                        clock-frequency = <0>;
+                       next-level-cache = <&L2>;
                };
        };
 
@@ -63,7 +64,7 @@
                        interrupts = <18 2>;
                };
 
-               l2-cache-controller@20000 {
+               L2: l2-cache-controller@20000 {
                        compatible = "fsl,8540-l2-cache-controller";
                        reg = <0x20000 0x1000>;
                        cache-line-size = <32>;

diff --git a/arch/powerpc/boot/dts/tqm8560.dts b/arch/powerpc/boot/dts/tqm8560.dts
index 358cbd7c7572ab9413332701cf2a81a662751729..a4ee596e97bc6bcaf85d0f335e69d7ac39b28ec5 100644 (file)
--- a/arch/powerpc/boot/dts/tqm8560.dts
+++ b/arch/powerpc/boot/dts/tqm8560.dts
@@ -40,6 +40,7 @@
                        timebase-frequency = <0>;
                        bus-frequency = <0>;
                        clock-frequency = <0>;
+                       next-level-cache = <&L2>;
                };
        };
 
@@ -64,7 +65,7 @@
                        interrupts = <18 2>;
                };
 
-               l2-cache-controller@20000 {
+               L2: l2-cache-controller@20000 {
                        compatible = "fsl,8540-l2-cache-controller";
                        reg = <0x20000 0x1000>;
                        cache-line-size = <32>;