if (DMA64_ENAB(di) && DMA64_MODE(di)) {
if (di->txd64)
DMA_FREE_CONSISTENT(di->osh,
- ((s8 *) (uintptr) di->txd64 -
+ ((s8 *)di->txd64 -
di->txdalign), di->txdalloc,
(di->txdpaorig), &di->tx_dmah);
if (di->rxd64)
DMA_FREE_CONSISTENT(di->osh,
- ((s8 *) (uintptr) di->rxd64 -
+ ((s8 *)di->rxd64 -
di->rxdalign), di->rxdalloc,
(di->rxdpaorig), &di->rx_dmah);
} else if (DMA32_ENAB(di)) {
if (di->txd32)
DMA_FREE_CONSISTENT(di->osh,
- ((s8 *) (uintptr) di->txd32 -
+ ((s8 *)di->txd32 -
di->txdalign), di->txdalloc,
(di->txdpaorig), &di->tx_dmah);
if (di->rxd32)
DMA_FREE_CONSISTENT(di->osh,
- ((s8 *) (uintptr) di->rxd32 -
+ ((s8 *)di->rxd32 -
di->rxdalign), di->rxdalloc,
(di->rxdpaorig), &di->rx_dmah);
} else
/* clear rx descriptor ring */
if (DMA64_ENAB(di) && DMA64_MODE(di)) {
- BZERO_SM((void *)(uintptr) di->rxd64,
+ BZERO_SM((void *)di->rxd64,
(di->nrxd * sizeof(dma64dd_t)));
/* DMA engine with out alignment requirement requires table to be inited
if (di->aligndesc_4k)
_dma_ddtable_init(di, DMA_RX, di->rxdpa);
} else if (DMA32_ENAB(di)) {
- BZERO_SM((void *)(uintptr) di->rxd32,
+ BZERO_SM((void *)di->rxd32,
(di->nrxd * sizeof(dma32dd_t)));
_dma_rxenable(di);
_dma_ddtable_init(di, DMA_RX, di->rxdpa);
di->hnddma.txavail = di->ntxd - 1;
/* clear tx descriptor ring */
- BZERO_SM((void *)(uintptr) di->txd32, (di->ntxd * sizeof(dma32dd_t)));
+ BZERO_SM((void *)di->txd32, (di->ntxd * sizeof(dma32dd_t)));
if ((di->hnddma.dmactrlflags & DMA_CTRL_PEN) == 0)
control |= XC_PD;
ASSERT(PHYSADDRHI(di->txdpaorig) == 0);
di->txd32 = (dma32dd_t *) ROUNDUP((uintptr) va, align);
di->txdalign =
- (uint) ((s8 *) (uintptr) di->txd32 - (s8 *) va);
+ (uint) ((s8 *)di->txd32 - (s8 *) va);
PHYSADDRLOSET(di->txdpa,
PHYSADDRLO(di->txdpaorig) + di->txdalign);
ASSERT(PHYSADDRHI(di->rxdpaorig) == 0);
di->rxd32 = (dma32dd_t *) ROUNDUP((uintptr) va, align);
di->rxdalign =
- (uint) ((s8 *) (uintptr) di->rxd32 - (s8 *) va);
+ (uint) ((s8 *)di->rxd32 - (s8 *) va);
PHYSADDRLOSET(di->rxdpa,
PHYSADDRLO(di->rxdpaorig) + di->rxdalign);
di->hnddma.txavail = di->ntxd - 1;
/* clear tx descriptor ring */
- BZERO_SM((void *)(uintptr) di->txd64, (di->ntxd * sizeof(dma64dd_t)));
+ BZERO_SM((void *)di->txd64, (di->ntxd * sizeof(dma64dd_t)));
/* DMA engine with out alignment requirement requires table to be inited
* before enabling the engine
}
align = (1 << align_bits);
di->txd64 = (dma64dd_t *) ROUNDUP((uintptr) va, align);
- di->txdalign =
- (uint) ((s8 *) (uintptr) di->txd64 - (s8 *) va);
+ di->txdalign = (uint) ((s8 *)di->txd64 - (s8 *) va);
PHYSADDRLOSET(di->txdpa,
PHYSADDRLO(di->txdpaorig) + di->txdalign);
/* Make sure that alignment didn't overflow */
}
align = (1 << align_bits);
di->rxd64 = (dma64dd_t *) ROUNDUP((uintptr) va, align);
- di->rxdalign =
- (uint) ((s8 *) (uintptr) di->rxd64 - (s8 *) va);
+ di->rxdalign = (uint) ((s8 *)di->rxd64 - (s8 *) va);
PHYSADDRLOSET(di->rxdpa,
PHYSADDRLO(di->rxdpaorig) + di->rxdalign);
/* Make sure that alignment didn't overflow */
uint pciidx, pcieidx, pcirev, pcierev;
cc = si_setcoreidx(&sii->pub, SI_CC_IDX);
- ASSERT((uintptr) cc);
+ ASSERT(cc);
/* get chipcommon rev */
sii->pub.ccrev = (int)si_corerev(&sii->pub);
if (BUSTYPE(sii->pub.bustype) == PCI_BUS) {
if (SI_FAST(sii)) {
if (!sii->pch) {
- sii->pch = (void *)(uintptr)pcicore_init(
+ sii->pch = (void *)pcicore_init(
&sii->pub, sii->osh,
(void *)PCIEREGS(sii));
if (sii->pch == NULL)
if (CHIPTYPE(sii->pub.socitype) == SOCI_AI) {
SI_MSG(("Found chip type AI (0x%08x)\n", w));
/* pass chipc address instead of original core base */
- ai_scan(&sii->pub, (void *)(uintptr) cc, devid);
+ ai_scan(&sii->pub, (void *)cc, devid);
} else {
SI_ERROR(("Found chip of unknown type (0x%08x)\n", w));
return NULL;
SET_REG(sii->osh, &cc->system_clk_ctl, SYCC_CD_MASK,
(ILP_DIV_1MHZ << SYCC_CD_SHIFT));
- si_clkctl_setdelay(sii, (void *)(uintptr) cc);
+ si_clkctl_setdelay(sii, (void *)cc);
if (!fast)
si_setcoreidx(sih, origidx);