drm/i915: disable powersave feature for Ironlake currently
authorZhenyu Wang <zhenyuw@linux.intel.com>
Tue, 29 Sep 2009 03:01:23 +0000 (11:01 +0800)
committerEric Anholt <eric@anholt.net>
Tue, 13 Oct 2009 17:56:57 +0000 (10:56 -0700)
Until we figure out the right setting for powersave features on
Ironlake, disable it for now. Also disable watermark update,
which has new registers for it on Ironlake too.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[anholt: Resolved against the Pineview FBC changes]
Signed-off-by: Eric Anholt <eric@anholt.net>
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/intel_display.c

index 1254c4b80e30f7c1f029fb23b12515cd75c1e16b..24e154e47225e540ab145e0ea204ff7421211e34 100644 (file)
@@ -984,7 +984,10 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
 
 #define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IGDNG(dev))
 #define HAS_PIPE_CXSR(dev) (IS_G4X(dev) || IS_IGDNG(dev))
-#define I915_HAS_FBC(dev) (IS_MOBILE(dev) && (IS_I9XX(dev) || IS_GM45(dev)) && !IS_IGD(dev))
+#define I915_HAS_FBC(dev) (IS_MOBILE(dev) && \
+                          (IS_I9XX(dev) || IS_GM45(dev)) && \
+                          !IS_IGD(dev) && \
+                          !IS_IGDNG(dev))
 
 #define PRIMARY_RINGBUFFER_SIZE         (128*1024)
 
index 9efe11761be37ddd70b0a394277be2ec3f3a27b8..be7fada590d497311b812fb6b25c5735b0f7ae26 100644 (file)
@@ -2586,6 +2586,9 @@ static void intel_update_watermarks(struct drm_device *dev)
        unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
        int enabled = 0, pixel_size = 0;
 
+       if (!dev_priv->display.update_wm)
+               return;
+
        /* Get the clock config from both planes */
        list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
                intel_crtc = to_intel_crtc(crtc);
@@ -4126,7 +4129,9 @@ void intel_init_clock_gating(struct drm_device *dev)
         * Disable clock gating reported to work incorrectly according to the
         * specs, but enable as much else as we can.
         */
-       if (IS_G4X(dev)) {
+       if (IS_IGDNG(dev)) {
+               return;
+       } else if (IS_G4X(dev)) {
                uint32_t dspclk_gate;
                I915_WRITE(RENCLK_GATE_D1, 0);
                I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
@@ -4214,7 +4219,9 @@ static void intel_init_display(struct drm_device *dev)
                        i830_get_display_clock_speed;
 
        /* For FIFO watermark updates */
-       if (IS_G4X(dev))
+       if (IS_IGDNG(dev))
+               dev_priv->display.update_wm = NULL;
+       else if (IS_G4X(dev))
                dev_priv->display.update_wm = g4x_update_wm;
        else if (IS_I965G(dev))
                dev_priv->display.update_wm = i965_update_wm;