PCI: rockchip: Use gpiod_set_value_cansleep() to allow reset via expanders

The reset GPIO can be connected to a I2C or SPI IO expander, which may
sleep, so it is safer to use the gpiod_set_value_cansleep() variant
instead.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Shawn Lin <shawn.lin@rock-chips.com>

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index 9ed784360d312f8d2562249b79a26ec85cb3a6ed..c10b8987d7b32b4e5da19d41bf1f700c23db0fd6 100644 (file)
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -543,7 +543,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
        int err, i;
        u32 status;
 
-       gpiod_set_value(rockchip->ep_gpio, 0);
+       gpiod_set_value_cansleep(rockchip->ep_gpio, 0);
 
        err = reset_control_assert(rockchip->aclk_rst);
        if (err) {
@@ -688,7 +688,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
        rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
                            PCIE_CLIENT_CONFIG);
 
-       gpiod_set_value(rockchip->ep_gpio, 1);
+       gpiod_set_value_cansleep(rockchip->ep_gpio, 1);
 
        /* 500ms timeout value should be enough for Gen1/2 training */
        err = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_BASIC_STATUS1,