KVM: MIPS/T&E: Default to reset vector

Set the default VCPU state closer to the architectural reset state, with
PC pointing at the reset vector (uncached PA 0x1fc00000, which for KVM
T&E is VA 0x5fc00000), and with CP0_Status.BEV and CP0_Status.ERL to 1.

Although QEMU at least will overwrite this state, it makes sense to do
this now that CP0_EBase is properly implemented to check BEV, and now
that we support a sparse GPA layout potentially with a boot ROM at GPA
0x1fc00000.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: "Radim Krčmář" <rkrcmar@redhat.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org

diff --git a/arch/mips/kvm/trap_emul.c b/arch/mips/kvm/trap_emul.c
index 80a681f42bf509ab059781555f920cc110f19820..ce44f91c653a2533908bcf31fae7ece6207251f7 100644 (file)
--- a/arch/mips/kvm/trap_emul.c
+++ b/arch/mips/kvm/trap_emul.c
@@ -614,6 +614,9 @@ static int kvm_trap_emul_vcpu_setup(struct kvm_vcpu *vcpu)
        /* Set Wait IE/IXMT Ignore in Config7, IAR, AR */
        kvm_write_c0_guest_config7(cop0, (MIPS_CONF7_WII) | (1 << 10));
 
+       /* Status */
+       kvm_write_c0_guest_status(cop0, ST0_BEV | ST0_ERL);
+
        /*
         * Setup IntCtl defaults, compatibility mode for timer interrupts (HW5)
         */
@@ -623,6 +626,9 @@ static int kvm_trap_emul_vcpu_setup(struct kvm_vcpu *vcpu)
        kvm_write_c0_guest_ebase(cop0, KVM_GUEST_KSEG0 |
                                       (vcpu_id & MIPS_EBASE_CPUNUM));
 
+       /* Put PC at guest reset vector */
+       vcpu->arch.pc = KVM_GUEST_CKSEG1ADDR(0x1fc00000);
+
        return 0;
 }