return err;
}
}
+ mask_ck = mask_ck >> 1;
}
- /* Kasin Added for restore config value. */
- mali_hw_core_register_write_relaxed(&pmu->hw_core, PMU_REG_ADDR_MGMT_SW_DELAY, pmu->switch_delay);
+ if (xxd != 0) {
+ printk("@@@@ warn\n");
+ printk("mask_ck:%d,active_mask:%d\n", mask_ck, active_mask);
+ //panic(0);
+ }
+ if (swt_dly != pmu->switch_delay)
+ mali_hw_core_register_write_relaxed(&pmu->hw_core, PMU_REG_ADDR_MGMT_SW_DELAY, pmu->switch_delay);
-
#endif
#if defined(DEBUG)
} mali_osk_irq_object_t;
typedef irqreturn_t (*irq_handler_func_t)(int, void *, struct pt_regs *);
-static irqreturn_t irq_handler_upper_half (int port_name, void* dev_id ); /* , struct pt_regs *regs*/
+static irqreturn_t irq_handler_upper_half(int port_name, void *dev_id); /* , struct pt_regs *regs*/
+ #if MESON_CPU_TYPE == MESON_CPU_TYPE_MESON6
+ u32 get_irqnum(struct _mali_osk_irq_t_struct* irq)
+ {
+ if (irq)
+ return irq->irqnum;
+ else
+ return 0;
+ }
+ #endif
+
#if defined(DEBUG)
-#if 0
struct test_interrupt_data {
_mali_osk_irq_ack_t ack_func;
#include <mach/io.h>
#include <plat/io.h>
#include <asm/io.h>
-
#include "meson_main.h"
+ #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6TVD
+
#define FCLK_MPLL2 (2 << 9)
-
static DEFINE_SPINLOCK(lock);
+ static mali_plat_info_t* pmali_plat = NULL;
+ static u32 mali_extr_backup = 0;
+ static u32 mali_extr_sample_backup = 0;
- static u32 mali_extr_backup;
+ int mali_clock_init(mali_plat_info_t* mali_plat)
+ {
+ u32 def_clk_data;
+ if (mali_plat == NULL) {
+ printk(" Mali platform data is NULL!!!\n");
+ return -1;
+ }
- #if MESON_CPU_TYPE > MESON_CPU_TYPE_MESON8
- #define HAVE_MALI_CLOCK_SWITCH 1
- #endif
+ pmali_plat = mali_plat;
+ if (pmali_plat->have_switch) {
+ def_clk_data = pmali_plat->clk[pmali_plat->def_clock];
+ writel(def_clk_data | (def_clk_data << 16), (u32*)P_HHI_MALI_CLK_CNTL);
+ setbits_le32((u32)P_HHI_MALI_CLK_CNTL, 1 << 24);
+ setbits_le32((u32)P_HHI_MALI_CLK_CNTL, 1 << 8);
+ } else {
+ mali_clock_set(pmali_plat->def_clock);
+ }
- int mali_clock_init(u32 def_clk_idx)
- {
- #ifdef HAVE_MALI_CLOCK_SWITCH
- writel((mali_dvfs_clk[def_clk_idx]<<16)|(mali_dvfs_clk[def_clk_idx]<<16), (u32*)P_HHI_MALI_CLK_CNTL);
- setbits_le32((u32)P_HHI_MALI_CLK_CNTL, 1 << 24);
- setbits_le32((u32)P_HHI_MALI_CLK_CNTL, 1 << 8);
- #else
- mali_clock_set(def_clk_idx);
- #endif
- mali_extr_backup = mali_dvfs_clk[get_mali_tbl_size() -1];
+ mali_extr_backup = pmali_plat->clk[pmali_plat->clk_len - 1];
+ mali_extr_sample_backup = pmali_plat->clk_sample[pmali_plat->clk_len - 1];
return 0;
}
637, /* 637.5 Mhz */
};
+ static mali_dvfs_threshold_table mali_dvfs_table[]={
+ { 0, 0, 3, 70, 180}, /* for 182.1 */
+ { 1, 1, 3, 108, 205}, /* for 318.7 */
+ { 2, 2, 3, 150, 215}, /* for 425.0 */
+ { 3, 3, 3, 170, 253}, /* for 510.0 */
+ { 4, 4, 3, 230, 256}, /* for 637.5 */
+ { 0, 0, 3, 0, 0}
+ };
+
+ static void mali_plat_preheat(void);
+ static mali_plat_info_t mali_plat_data = {
+ .cfg_pp = CFG_PP, /* number of pp. */
+ .cfg_min_pp = CFG_MIN_PP,
+ .turbo_clock = 4, /* reserved clock src. */
+ .def_clock = 2, /* gpu clock used most of time.*/
+ .cfg_clock = CFG_CLOCK, /* max gpu clock. */
+ .cfg_clock_bkup = CFG_CLOCK,
+ .cfg_min_clock = CFG_MIN_CLOCK,
+
+ .sc_mpp = 3, /* number of pp used most of time.*/
+ .bst_gpu = 210, /* threshold for boosting gpu. */
+ .bst_pp = 160, /* threshold for boosting PP. */
+
+ .clk = mali_dvfs_clk, /* clock source table. */
+ .clk_sample = mali_dvfs_clk_sample, /* freqency table for show. */
+ .clk_len = sizeof(mali_dvfs_clk) / sizeof(mali_dvfs_clk[0]),
+ .have_switch = 1,
+
+ .dvfs_table = mali_dvfs_table, /* DVFS table. */
+ .dvfs_table_size = sizeof(mali_dvfs_table) / sizeof(mali_dvfs_threshold_table),
+
+ .scale_info = {
+ CFG_MIN_PP, /* minpp */
+ CFG_PP, /* maxpp, should be same as cfg_pp */
+ CFG_MIN_CLOCK, /* minclk */
+ CFG_CLOCK, /* maxclk should be same as cfg_clock */
+ },
+
+ .limit_on = 1,
+ .plat_preheat = mali_plat_preheat,
+ };
+
+ static void mali_plat_preheat(void)
+ {
+ u32 pre_fs;
+ u32 clk, pp;
+
+ if (get_mali_schel_mode() != MALI_PP_FS_SCALING)
+ return;
+
+ get_mali_rt_clkpp(&clk, &pp);
+ pre_fs = mali_plat_data.def_clock + 1;
+ if (clk < pre_fs)
+ clk = pre_fs;
+ if (pp < mali_plat_data.sc_mpp)
+ pp = mali_plat_data.sc_mpp;
+ set_mali_rt_clkpp(clk, pp, 1);
+ }
+
+ mali_plat_info_t* get_mali_plat_data(void) {
+ return &mali_plat_data;
+ }
+
int get_mali_freq_level(int freq)
{
+ int mali_freq_num;
int i = 0, level = -1;
+ int mali_freq_num;
+
if(freq < 0)
return level;
- mali_freq_num = sizeof(mali_dvfs_clk_sample) / sizeof(mali_dvfs_clk_sample[0]) - 1;
- if(freq <= mali_dvfs_clk_sample[0])
++
+ mali_freq_num = mali_plat_data.dvfs_table_size - 1;
+ if(freq <= mali_plat_data.clk_sample[0])
level = mali_freq_num-1;
- if(freq >= mali_dvfs_clk_sample[mali_freq_num - 1])
+ if(freq >= mali_plat_data.clk_sample[mali_freq_num - 1])
level = 0;
for(i=0; i<mali_freq_num - 1 ;i++) {
- if(freq >= mali_dvfs_clk_sample[i] && freq<=mali_dvfs_clk_sample[i+1]) {
+ if(freq >= mali_plat_data.clk_sample[i] && freq<=mali_plat_data.clk_sample[i + 1]) {
level = i;
- level = mali_freq_num-level-1;
+ level = mali_freq_num-level - 1;
}
}
return level;
ret = device->driver->pm->resume(device);
}
return ret;
-
+
+ }
+
+ int mali_light_suspend(struct device *device)
+ {
+ int ret = 0;
+ #ifdef CONFIG_MALI400_PROFILING
+ _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
+ MALI_PROFILING_EVENT_CHANNEL_GPU |
+ MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
+ 0, 0, 0, 0, 0);
+ #endif
+
+ /* clock scaling. Kasin..*/
+ ret = mali_clock_critical(mali_cri_light_suspend, (size_t)device);
+ disable_clock();
+ return ret;
+ }
+
+ int mali_light_resume(struct device *device)
+ {
+ int ret = 0;
+ enable_clock();
+ ret = mali_clock_critical(mali_cri_light_resume, (size_t)device);
+ #ifdef CONFIG_MALI400_PROFILING
+ _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
+ MALI_PROFILING_EVENT_CHANNEL_GPU |
+ MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
+ get_current_frequency(), 0, 0, 0, 0);
+ #endif
+ return ret;
+ }
+
+ int mali_deep_suspend(struct device *device)
+ {
+ int ret = 0;
++ struct mali_pmu_core *pmu;
++
++ pmu = mali_pmu_get_global_pmu_core();
+ enable_clock();
+ flush_scaling_job();
+
+ /* clock scaling off. Kasin... */
+ ret = mali_clock_critical(mali_cri_deep_suspend, (size_t)device);
+ disable_clock();
+ return ret;
+ }
+
+ int mali_deep_resume(struct device *device)
+ {
+ int ret = 0;
+
+ /* clock scaling up. Kasin.. */
+ enable_clock();
+ ret = mali_clock_critical(mali_cri_deep_resume, (size_t)device);
+ return ret;
}
projects / GitHub / LineageOS / G12 / android_hardware_amlogic_kernel-modules_mali-driver.git / commitdiff