MIPS: BMIPS: Align secondary boot sequence with latest firmware releases

On some older BMIPS5200 (dual core / quad thread) platforms, the
PROM code set up CPU2/CPU3 so they would be started through an NMI
instead of through the ACTION register.  But this was incompatible with
some power management features that were later added, so the scheme was
changed so that Linux is fully responsible for booting CPU2/CPU3.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: mbizon@freebox.fr
Cc: jogo@openwrt.org
Cc: jfraser@broadcom.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8157/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c
index 06bb5ed6d80a68728b56329db41a6531d377eca8..4e569113ff56054ef4879db023ee47af13ba564c 100644 (file)
--- a/arch/mips/kernel/smp-bmips.c
+++ b/arch/mips/kernel/smp-bmips.c
@@ -213,17 +213,7 @@ static void bmips_boot_secondary(int cpu, struct task_struct *idle)
                                set_c0_brcm_cmt_ctrl(0x01);
                        break;
                case CPU_BMIPS5000:
-                       if (cpu & 0x01)
-                               write_c0_brcm_action(ACTION_BOOT_THREAD(cpu));
-                       else {
-                               /*
-                                * core N thread 0 was already booted; just
-                                * pulse the NMI line
-                                */
-                               bmips_write_zscm_reg(0x210, 0xc0000000);
-                               udelay(10);
-                               bmips_write_zscm_reg(0x210, 0x00);
-                       }
+                       write_c0_brcm_action(ACTION_BOOT_THREAD(cpu));
                        break;
                }
                cpumask_set_cpu(cpu, &bmips_booted_mask);