__u8 pad03[5];
};
-struct gf110_dma_v0 {
+struct gf119_dma_v0 {
__u8 version;
-#define GF110_DMA_V0_PAGE_LP 0x00
-#define GF110_DMA_V0_PAGE_SP 0x01
+#define GF119_DMA_V0_PAGE_LP 0x00
+#define GF119_DMA_V0_PAGE_SP 0x01
__u8 page;
-#define GF110_DMA_V0_KIND_PITCH 0x00
-#define GF110_DMA_V0_KIND_VM 0xff
+#define GF119_DMA_V0_KIND_PITCH 0x00
+#define GF119_DMA_V0_KIND_VM 0xff
__u8 kind;
__u8 pad03[5];
};
#define __NVKM_DMA_H__
#include <core/engine.h>
struct nvkm_client;
-struct nvkm_gpuobj;
struct nvkm_dmaobj {
const struct nvkm_dmaobj_func *func;
u64 handle; /*XXX HANDLE MERGE */
};
-struct nvkm_dmaobj_func {
- int (*bind)(struct nvkm_dmaobj *, struct nvkm_gpuobj *, int align,
- struct nvkm_gpuobj **);
-};
-
struct nvkm_dma {
+ const struct nvkm_dma_func *func;
struct nvkm_engine engine;
};
struct nvkm_dmaobj *
nvkm_dma_search(struct nvkm_dma *, struct nvkm_client *, u64 object);
-extern struct nvkm_oclass *nv04_dmaeng_oclass;
-extern struct nvkm_oclass *nv50_dmaeng_oclass;
-extern struct nvkm_oclass *gf100_dmaeng_oclass;
-extern struct nvkm_oclass *gf110_dmaeng_oclass;
+int nv04_dma_new(struct nvkm_device *, int, struct nvkm_dma **);
+int nv50_dma_new(struct nvkm_device *, int, struct nvkm_dma **);
+int gf100_dma_new(struct nvkm_device *, int, struct nvkm_dma **);
+int gf119_dma_new(struct nvkm_device *, int, struct nvkm_dma **);
#endif
union {
struct nv50_dma_v0 nv50;
struct gf100_dma_v0 gf100;
- struct gf110_dma_v0 gf110;
+ struct gf119_dma_v0 gf119;
};
} args = {};
struct nv50_fbdma *fbdma;
args.gf100.kind = kind;
size += sizeof(args.gf100);
} else {
- args.gf110.page = GF110_DMA_V0_PAGE_LP;
- args.gf110.kind = kind;
- size += sizeof(args.gf110);
+ args.gf119.page = GF119_DMA_V0_PAGE_LP;
+ args.gf119.kind = kind;
+ size += sizeof(args.gf119);
}
list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
.mmu = nv04_mmu_new,
.timer = nv04_timer_new,
// .disp = nv04_disp_new,
-// .dma = nv04_dma_new,
+ .dma = nv04_dma_new,
// .fifo = nv04_fifo_new,
// .gr = nv04_gr_new,
// .sw = nv04_sw_new,
.mmu = nv04_mmu_new,
.timer = nv04_timer_new,
// .disp = nv04_disp_new,
-// .dma = nv04_dma_new,
+ .dma = nv04_dma_new,
// .fifo = nv04_fifo_new,
// .gr = nv04_gr_new,
// .sw = nv04_sw_new,
.mmu = nv04_mmu_new,
.timer = nv04_timer_new,
// .disp = nv04_disp_new,
-// .dma = nv04_dma_new,
+ .dma = nv04_dma_new,
// .gr = nv10_gr_new,
};
.mmu = nv04_mmu_new,
.timer = nv04_timer_new,
// .disp = nv04_disp_new,
-// .dma = nv04_dma_new,
+ .dma = nv04_dma_new,
// .fifo = nv10_fifo_new,
// .gr = nv10_gr_new,
// .sw = nv10_sw_new,
.mmu = nv04_mmu_new,
.timer = nv04_timer_new,
// .disp = nv04_disp_new,
-// .dma = nv04_dma_new,
+ .dma = nv04_dma_new,
// .fifo = nv10_fifo_new,
// .gr = nv10_gr_new,
// .sw = nv10_sw_new,
.mmu = nv04_mmu_new,
.timer = nv04_timer_new,
// .disp = nv04_disp_new,
-// .dma = nv04_dma_new,
+ .dma = nv04_dma_new,
// .fifo = nv17_fifo_new,
// .gr = nv10_gr_new,
// .sw = nv10_sw_new,
.mmu = nv04_mmu_new,
.timer = nv04_timer_new,
// .disp = nv04_disp_new,
-// .dma = nv04_dma_new,
+ .dma = nv04_dma_new,
// .fifo = nv17_fifo_new,
// .gr = nv10_gr_new,
// .sw = nv10_sw_new,
.mmu = nv04_mmu_new,
.timer = nv04_timer_new,
// .disp = nv04_disp_new,
-// .dma = nv04_dma_new,
+ .dma = nv04_dma_new,
// .fifo = nv10_fifo_new,
// .gr = nv10_gr_new,
// .sw = nv10_sw_new,
.mmu = nv04_mmu_new,
.timer = nv04_timer_new,
// .disp = nv04_disp_new,
-// .dma = nv04_dma_new,
+ .dma = nv04_dma_new,
// .fifo = nv17_fifo_new,
// .gr = nv10_gr_new,
// .sw = nv10_sw_new,
.mmu = nv04_mmu_new,
.timer = nv04_timer_new,
// .disp = nv04_disp_new,
-// .dma = nv04_dma_new,
+ .dma = nv04_dma_new,
// .fifo = nv17_fifo_new,
// .gr = nv20_gr_new,
// .sw = nv10_sw_new,
.mmu = nv04_mmu_new,
.timer = nv04_timer_new,
// .disp = nv04_disp_new,
-// .dma = nv04_dma_new,
+ .dma = nv04_dma_new,
// .fifo = nv17_fifo_new,
// .gr = nv25_gr_new,
// .sw = nv10_sw_new,
.mmu = nv04_mmu_new,
.timer = nv04_timer_new,
// .disp = nv04_disp_new,
-// .dma = nv04_dma_new,
+ .dma = nv04_dma_new,
// .fifo = nv17_fifo_new,
// .gr = nv25_gr_new,
// .sw = nv10_sw_new,
.mmu = nv04_mmu_new,
.timer = nv04_timer_new,
// .disp = nv04_disp_new,
-// .dma = nv04_dma_new,
+ .dma = nv04_dma_new,
// .fifo = nv17_fifo_new,
// .gr = nv2a_gr_new,
// .sw = nv10_sw_new,
.mmu = nv04_mmu_new,
.timer = nv04_timer_new,
// .disp = nv04_disp_new,
-// .dma = nv04_dma_new,
+ .dma = nv04_dma_new,
// .fifo = nv17_fifo_new,
// .gr = nv30_gr_new,
// .sw = nv10_sw_new,
.mmu = nv04_mmu_new,
.timer = nv04_timer_new,
// .disp = nv04_disp_new,
-// .dma = nv04_dma_new,
+ .dma = nv04_dma_new,
// .fifo = nv17_fifo_new,
// .gr = nv30_gr_new,
// .mpeg = nv31_mpeg_new,
.mmu = nv04_mmu_new,
.timer = nv04_timer_new,
// .disp = nv04_disp_new,
-// .dma = nv04_dma_new,
+ .dma = nv04_dma_new,
// .fifo = nv17_fifo_new,
// .gr = nv34_gr_new,
// .mpeg = nv31_mpeg_new,
.mmu = nv04_mmu_new,
.timer = nv04_timer_new,
// .disp = nv04_disp_new,
-// .dma = nv04_dma_new,
+ .dma = nv04_dma_new,
// .fifo = nv17_fifo_new,
// .gr = nv35_gr_new,
// .sw = nv10_sw_new,
.mmu = nv04_mmu_new,
.timer = nv04_timer_new,
// .disp = nv04_disp_new,
-// .dma = nv04_dma_new,
+ .dma = nv04_dma_new,
// .fifo = nv17_fifo_new,
// .gr = nv35_gr_new,
// .mpeg = nv31_mpeg_new,
.timer = nv40_timer_new,
.volt = nv40_volt_new,
// .disp = nv04_disp_new,
-// .dma = nv04_dma_new,
+ .dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
// .gr = nv40_gr_new,
// .mpeg = nv40_mpeg_new,
.timer = nv41_timer_new,
.volt = nv40_volt_new,
// .disp = nv04_disp_new,
-// .dma = nv04_dma_new,
+ .dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
// .gr = nv40_gr_new,
// .mpeg = nv40_mpeg_new,
.timer = nv41_timer_new,
.volt = nv40_volt_new,
// .disp = nv04_disp_new,
-// .dma = nv04_dma_new,
+ .dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
// .gr = nv40_gr_new,
// .mpeg = nv40_mpeg_new,
.timer = nv41_timer_new,
.volt = nv40_volt_new,
// .disp = nv04_disp_new,
-// .dma = nv04_dma_new,
+ .dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
// .gr = nv40_gr_new,
// .mpeg = nv40_mpeg_new,
.timer = nv41_timer_new,
.volt = nv40_volt_new,
// .disp = nv04_disp_new,
-// .dma = nv04_dma_new,
+ .dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
// .gr = nv40_gr_new,
// .mpeg = nv44_mpeg_new,
.timer = nv41_timer_new,
.volt = nv40_volt_new,
// .disp = nv04_disp_new,
-// .dma = nv04_dma_new,
+ .dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
// .gr = nv40_gr_new,
// .mpeg = nv44_mpeg_new,
.timer = nv41_timer_new,
.volt = nv40_volt_new,
// .disp = nv04_disp_new,
-// .dma = nv04_dma_new,
+ .dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
// .gr = nv40_gr_new,
// .mpeg = nv44_mpeg_new,
.timer = nv41_timer_new,
.volt = nv40_volt_new,
// .disp = nv04_disp_new,
-// .dma = nv04_dma_new,
+ .dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
// .gr = nv40_gr_new,
// .mpeg = nv44_mpeg_new,
.timer = nv41_timer_new,
.volt = nv40_volt_new,
// .disp = nv04_disp_new,
-// .dma = nv04_dma_new,
+ .dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
// .gr = nv40_gr_new,
// .mpeg = nv44_mpeg_new,
.timer = nv41_timer_new,
.volt = nv40_volt_new,
// .disp = nv04_disp_new,
-// .dma = nv04_dma_new,
+ .dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
// .gr = nv40_gr_new,
// .mpeg = nv44_mpeg_new,
.timer = nv41_timer_new,
.volt = nv40_volt_new,
// .disp = nv04_disp_new,
-// .dma = nv04_dma_new,
+ .dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
// .gr = nv40_gr_new,
// .mpeg = nv44_mpeg_new,
.timer = nv41_timer_new,
.volt = nv40_volt_new,
// .disp = nv04_disp_new,
-// .dma = nv04_dma_new,
+ .dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
// .gr = nv40_gr_new,
// .mpeg = nv44_mpeg_new,
.timer = nv41_timer_new,
.volt = nv40_volt_new,
// .disp = nv04_disp_new,
-// .dma = nv04_dma_new,
+ .dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
// .gr = nv40_gr_new,
// .mpeg = nv44_mpeg_new,
.timer = nv41_timer_new,
.volt = nv40_volt_new,
// .disp = nv50_disp_new,
-// .dma = nv50_dma_new,
+ .dma = nv50_dma_new,
// .fifo = nv50_fifo_new,
// .gr = nv50_gr_new,
// .mpeg = nv50_mpeg_new,
.timer = nv41_timer_new,
.volt = nv40_volt_new,
// .disp = nv04_disp_new,
-// .dma = nv04_dma_new,
+ .dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
// .gr = nv40_gr_new,
// .mpeg = nv44_mpeg_new,
.timer = nv41_timer_new,
.volt = nv40_volt_new,
// .disp = nv04_disp_new,
-// .dma = nv04_dma_new,
+ .dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
// .gr = nv40_gr_new,
// .mpeg = nv44_mpeg_new,
.timer = nv41_timer_new,
.volt = nv40_volt_new,
// .disp = nv04_disp_new,
-// .dma = nv04_dma_new,
+ .dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
// .gr = nv40_gr_new,
// .mpeg = nv44_mpeg_new,
.bsp = g84_bsp_new,
.cipher = g84_cipher_new,
// .disp = g84_disp_new,
-// .dma = nv50_dma_new,
+ .dma = nv50_dma_new,
// .fifo = g84_fifo_new,
// .gr = nv50_gr_new,
// .mpeg = g84_mpeg_new,
.bsp = g84_bsp_new,
.cipher = g84_cipher_new,
// .disp = g84_disp_new,
-// .dma = nv50_dma_new,
+ .dma = nv50_dma_new,
// .fifo = g84_fifo_new,
// .gr = nv50_gr_new,
// .mpeg = g84_mpeg_new,
.bsp = g84_bsp_new,
.cipher = g84_cipher_new,
// .disp = g84_disp_new,
-// .dma = nv50_dma_new,
+ .dma = nv50_dma_new,
// .fifo = g84_fifo_new,
// .gr = nv50_gr_new,
// .mpeg = g84_mpeg_new,
.bsp = g84_bsp_new,
.cipher = g84_cipher_new,
// .disp = g94_disp_new,
-// .dma = nv50_dma_new,
+ .dma = nv50_dma_new,
// .fifo = g84_fifo_new,
// .gr = nv50_gr_new,
// .mpeg = g84_mpeg_new,
.mmu = nv50_mmu_new,
.bar = g84_bar_new,
.volt = nv40_volt_new,
-// .dma = nv50_dma_new,
+ .dma = nv50_dma_new,
// .fifo = g84_fifo_new,
// .sw = nv50_sw_new,
// .gr = nv50_gr_new,
.mmu = nv50_mmu_new,
.bar = g84_bar_new,
.volt = nv40_volt_new,
-// .dma = nv50_dma_new,
+ .dma = nv50_dma_new,
// .fifo = g84_fifo_new,
// .sw = nv50_sw_new,
// .gr = nv50_gr_new,
.bsp = g84_bsp_new,
.cipher = g84_cipher_new,
// .disp = gt200_disp_new,
-// .dma = nv50_dma_new,
+ .dma = nv50_dma_new,
// .fifo = g84_fifo_new,
// .gr = nv50_gr_new,
// .mpeg = g84_mpeg_new,
.volt = nv40_volt_new,
.ce[0] = gt215_ce_new,
// .disp = gt215_disp_new,
-// .dma = nv50_dma_new,
+ .dma = nv50_dma_new,
// .fifo = g84_fifo_new,
// .gr = nv50_gr_new,
// .mpeg = g84_mpeg_new,
.volt = nv40_volt_new,
.ce[0] = gt215_ce_new,
// .disp = gt215_disp_new,
-// .dma = nv50_dma_new,
+ .dma = nv50_dma_new,
// .fifo = g84_fifo_new,
// .gr = nv50_gr_new,
.mspdec = gt215_mspdec_new,
.volt = nv40_volt_new,
.ce[0] = gt215_ce_new,
// .disp = gt215_disp_new,
-// .dma = nv50_dma_new,
+ .dma = nv50_dma_new,
// .fifo = g84_fifo_new,
// .gr = nv50_gr_new,
.mspdec = gt215_mspdec_new,
.timer = nv41_timer_new,
.volt = nv40_volt_new,
// .disp = g94_disp_new,
-// .dma = nv50_dma_new,
+ .dma = nv50_dma_new,
// .fifo = g84_fifo_new,
// .gr = nv50_gr_new,
.mspdec = g98_mspdec_new,
.timer = nv41_timer_new,
.volt = nv40_volt_new,
// .disp = g94_disp_new,
-// .dma = nv50_dma_new,
+ .dma = nv50_dma_new,
// .fifo = g84_fifo_new,
// .gr = nv50_gr_new,
.mspdec = g98_mspdec_new,
.volt = nv40_volt_new,
.ce[0] = gt215_ce_new,
// .disp = gt215_disp_new,
-// .dma = nv50_dma_new,
+ .dma = nv50_dma_new,
// .fifo = g84_fifo_new,
// .gr = nv50_gr_new,
.mspdec = gt215_mspdec_new,
.ce[0] = gf100_ce_new,
.ce[1] = gf100_ce_new,
// .disp = gt215_disp_new,
-// .dma = gf100_dma_new,
+ .dma = gf100_dma_new,
// .fifo = gf100_fifo_new,
// .gr = gf100_gr_new,
.mspdec = gf100_mspdec_new,
.volt = nv40_volt_new,
.ce[0] = gf100_ce_new,
// .disp = gt215_disp_new,
-// .dma = gf100_dma_new,
+ .dma = gf100_dma_new,
// .fifo = gf100_fifo_new,
// .gr = gf108_gr_new,
.mspdec = gf100_mspdec_new,
.volt = nv40_volt_new,
.ce[0] = gf100_ce_new,
// .disp = gt215_disp_new,
-// .dma = gf100_dma_new,
+ .dma = gf100_dma_new,
// .fifo = gf100_fifo_new,
// .gr = gf104_gr_new,
.mspdec = gf100_mspdec_new,
.ce[0] = gf100_ce_new,
.ce[1] = gf100_ce_new,
// .disp = gt215_disp_new,
-// .dma = gf100_dma_new,
+ .dma = gf100_dma_new,
// .fifo = gf100_fifo_new,
// .gr = gf104_gr_new,
.mspdec = gf100_mspdec_new,
.ce[0] = gf100_ce_new,
.ce[1] = gf100_ce_new,
// .disp = gt215_disp_new,
-// .dma = gf100_dma_new,
+ .dma = gf100_dma_new,
// .fifo = gf100_fifo_new,
// .gr = gf110_gr_new,
.mspdec = gf100_mspdec_new,
.ce[0] = gf100_ce_new,
.ce[1] = gf100_ce_new,
// .disp = gt215_disp_new,
-// .dma = gf100_dma_new,
+ .dma = gf100_dma_new,
// .fifo = gf100_fifo_new,
// .gr = gf104_gr_new,
.mspdec = gf100_mspdec_new,
.volt = nv40_volt_new,
.ce[0] = gf100_ce_new,
// .disp = gt215_disp_new,
-// .dma = gf100_dma_new,
+ .dma = gf100_dma_new,
// .fifo = gf100_fifo_new,
// .gr = gf104_gr_new,
.mspdec = gf100_mspdec_new,
.timer = nv41_timer_new,
.ce[0] = gf100_ce_new,
// .disp = gf119_disp_new,
-// .dma = gf119_dma_new,
+ .dma = gf119_dma_new,
// .fifo = gf100_fifo_new,
// .gr = gf117_gr_new,
.mspdec = gf100_mspdec_new,
.volt = nv40_volt_new,
.ce[0] = gf100_ce_new,
// .disp = gf119_disp_new,
-// .dma = gf119_dma_new,
+ .dma = gf119_dma_new,
// .fifo = gf100_fifo_new,
// .gr = gf119_gr_new,
.mspdec = gf100_mspdec_new,
.ce[1] = gk104_ce_new,
.ce[2] = gk104_ce_new,
// .disp = gk104_disp_new,
-// .dma = gf119_dma_new,
+ .dma = gf119_dma_new,
// .fifo = gk104_fifo_new,
// .gr = gk104_gr_new,
.mspdec = gk104_mspdec_new,
.ce[1] = gk104_ce_new,
.ce[2] = gk104_ce_new,
// .disp = gk104_disp_new,
-// .dma = gf119_dma_new,
+ .dma = gf119_dma_new,
// .fifo = gk104_fifo_new,
// .gr = gk104_gr_new,
.mspdec = gk104_mspdec_new,
.ce[1] = gk104_ce_new,
.ce[2] = gk104_ce_new,
// .disp = gk104_disp_new,
-// .dma = gf119_dma_new,
+ .dma = gf119_dma_new,
// .fifo = gk104_fifo_new,
// .gr = gk104_gr_new,
.mspdec = gk104_mspdec_new,
.timer = gk20a_timer_new,
.volt = gk20a_volt_new,
.ce[2] = gk104_ce_new,
-// .dma = gf119_dma_new,
+ .dma = gf119_dma_new,
// .fifo = gk20a_fifo_new,
// .gr = gk20a_gr_new,
// .pm = gk104_pm_new,
.ce[1] = gk104_ce_new,
.ce[2] = gk104_ce_new,
// .disp = gk110_disp_new,
-// .dma = gf119_dma_new,
+ .dma = gf119_dma_new,
// .fifo = gk104_fifo_new,
// .gr = gk110_gr_new,
.mspdec = gk104_mspdec_new,
.ce[1] = gk104_ce_new,
.ce[2] = gk104_ce_new,
// .disp = gk110_disp_new,
-// .dma = gf119_dma_new,
+ .dma = gf119_dma_new,
// .fifo = gk104_fifo_new,
// .gr = gk110b_gr_new,
.mspdec = gk104_mspdec_new,
.ce[1] = gk104_ce_new,
.ce[2] = gk104_ce_new,
// .disp = gk110_disp_new,
-// .dma = gf119_dma_new,
+ .dma = gf119_dma_new,
// .fifo = gk208_fifo_new,
// .gr = gk208_gr_new,
.mspdec = gk104_mspdec_new,
.ce[1] = gk104_ce_new,
.ce[2] = gk104_ce_new,
// .disp = gk110_disp_new,
-// .dma = gf119_dma_new,
+ .dma = gf119_dma_new,
// .fifo = gk208_fifo_new,
// .gr = gk208_gr_new,
.mspdec = gk104_mspdec_new,
.ce[0] = gk104_ce_new,
.ce[2] = gk104_ce_new,
// .disp = gm107_disp_new,
-// .dma = gf119_dma_new,
+ .dma = gf119_dma_new,
// .fifo = gk208_fifo_new,
// .gr = gm107_gr_new,
// .sw = gf100_sw_new,
.ce[1] = gm204_ce_new,
.ce[2] = gm204_ce_new,
// .disp = gm204_disp_new,
-// .dma = gf119_dma_new,
+ .dma = gf119_dma_new,
// .fifo = gm204_fifo_new,
// .gr = gm204_gr_new,
// .sw = gf100_sw_new,
.ce[1] = gm204_ce_new,
.ce[2] = gm204_ce_new,
// .disp = gm204_disp_new,
-// .dma = gf119_dma_new,
+ .dma = gf119_dma_new,
// .fifo = gm204_fifo_new,
// .gr = gm206_gr_new,
// .sw = gf100_sw_new,
.mmu = gf100_mmu_new,
.timer = gk20a_timer_new,
.ce[2] = gm204_ce_new,
-// .dma = gf119_dma_new,
+ .dma = gf119_dma_new,
// .fifo = gm20b_fifo_new,
// .gr = gm20b_gr_new,
// .sw = gf100_sw_new,
{
switch (device->chipset) {
case 0xc0:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf100_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xc4:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xc3:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xce:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xcf:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xc1:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf108_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gf108_pm_oclass;
break;
case 0xc8:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf110_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xd9:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf119_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gf117_pm_oclass;
break;
case 0xd7:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf117_gr_oclass;
{
switch (device->chipset) {
case 0xe4:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
break;
case 0xe7:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
break;
case 0xe6:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
break;
case 0xea:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk20a_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
break;
case 0xf0:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk110_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass;
break;
case 0xf1:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk110b_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass;
break;
case 0x106:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk208_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass;
break;
case 0x108:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk208_gr_oclass;
#if 0
#endif
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gm107_gr_oclass;
#endif
#if 0
#endif
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gm204_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gm204_gr_oclass;
#endif
#if 0
#endif
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gm204_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gm206_gr_oclass;
break;
case 0x12b:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gm20b_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gm20b_gr_oclass;
{
switch (device->chipset) {
case 0x04:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv04_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv04_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x05:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv04_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv04_gr_oclass;
{
switch (device->chipset) {
case 0x10:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x15:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x16:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x1a:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x11:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x17:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x1f:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x18:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
{
switch (device->chipset) {
case 0x20:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv20_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x25:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv25_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x28:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv25_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x2a:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv2a_gr_oclass;
{
switch (device->chipset) {
case 0x30:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv30_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x35:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv35_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x31:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv30_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x36:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv35_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x34:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv34_gr_oclass;
{
switch (device->chipset) {
case 0x40:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x41:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x42:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x43:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x45:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x47:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x49:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x4b:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x44:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x46:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x4a:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x4c:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x4e:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x63:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x67:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x68:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
{
switch (device->chipset) {
case 0x50:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv50_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv50_pm_oclass;
break;
case 0x84:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0x86:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0x92:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0x94:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0x96:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0x98:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0xa0:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gt200_pm_oclass;
break;
case 0xaa:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0xac:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0xa3:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
break;
case 0xa5:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
break;
case 0xa8:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
break;
case 0xaf:
- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
nvkm-y += nvkm/engine/dma/nv04.o
nvkm-y += nvkm/engine/dma/nv50.o
nvkm-y += nvkm/engine/dma/gf100.o
-nvkm-y += nvkm/engine/dma/gf110.o
+nvkm-y += nvkm/engine/dma/gf119.o
nvkm-y += nvkm/engine/dma/user.o
nvkm-y += nvkm/engine/dma/usernv04.o
nvkm-y += nvkm/engine/dma/usernv50.o
nvkm-y += nvkm/engine/dma/usergf100.o
-nvkm-y += nvkm/engine/dma/usergf110.o
+nvkm-y += nvkm/engine/dma/usergf119.o
struct nvkm_object **pobject)
{
struct nvkm_dma *dma = nvkm_dma(oclass->engine);
- struct nvkm_dma_impl *impl = (void *)dma->engine.subdev.object.oclass;
struct nvkm_dmaobj *dmaobj = NULL;
struct nvkm_client *client = oclass->client;
struct rb_node **ptr = &client->dmaroot.rb_node;
struct rb_node *parent = NULL;
int ret;
- ret = impl->class_new(dma, oclass, data, size, &dmaobj);
+ ret = dma->func->class_new(dma, oclass, data, size, &dmaobj);
if (dmaobj)
*pobject = &dmaobj->object;
if (ret)
return count;
}
+static void *
+nvkm_dma_dtor(struct nvkm_engine *engine)
+{
+ return nvkm_dma(engine);
+}
+
static const struct nvkm_engine_func
nvkm_dma = {
+ .dtor = nvkm_dma_dtor,
.base.sclass = nvkm_dma_oclass_base_get,
.fifo.sclass = nvkm_dma_oclass_fifo_get,
};
int
-_nvkm_dma_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
- struct nvkm_oclass *oclass, void *data, u32 size,
- struct nvkm_object **pobject)
+nvkm_dma_new_(const struct nvkm_dma_func *func, struct nvkm_device *device,
+ int index, struct nvkm_dma **pdma)
{
- struct nvkm_dma *dmaeng;
- int ret;
+ struct nvkm_dma *dma;
- ret = nvkm_engine_create(parent, engine, oclass, true, "DMAOBJ",
- "dmaobj", &dmaeng);
- *pobject = nv_object(dmaeng);
- if (ret)
- return ret;
+ if (!(dma = *pdma = kzalloc(sizeof(*dma), GFP_KERNEL)))
+ return -ENOMEM;
+ dma->func = func;
- dmaeng->engine.func = &nvkm_dma;
- return 0;
+ return nvkm_engine_ctor(&nvkm_dma, device, index,
+ 0, true, &dma->engine);
}
#include "priv.h"
#include "user.h"
-struct nvkm_oclass *
-gf100_dmaeng_oclass = &(struct nvkm_dma_impl) {
- .base.handle = NV_ENGINE(DMAOBJ, 0xc0),
- .base.ofuncs = &(struct nvkm_ofuncs) {
- .ctor = _nvkm_dma_ctor,
- .dtor = _nvkm_dma_dtor,
- .init = _nvkm_dma_init,
- .fini = _nvkm_dma_fini,
- },
+static const struct nvkm_dma_func
+gf100_dma = {
.class_new = gf100_dmaobj_new,
-}.base;
+};
+
+int
+gf100_dma_new(struct nvkm_device *device, int index, struct nvkm_dma **pdma)
+{
+ return nvkm_dma_new_(&gf100_dma, device, index, pdma);
+}
+++ /dev/null
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-#include "priv.h"
-#include "user.h"
-
-struct nvkm_oclass *
-gf110_dmaeng_oclass = &(struct nvkm_dma_impl) {
- .base.handle = NV_ENGINE(DMAOBJ, 0xd0),
- .base.ofuncs = &(struct nvkm_ofuncs) {
- .ctor = _nvkm_dma_ctor,
- .dtor = _nvkm_dma_dtor,
- .init = _nvkm_dma_init,
- .fini = _nvkm_dma_fini,
- },
- .class_new = gf110_dmaobj_new,
-}.base;
--- /dev/null
+/*
+ * Copyright 2012 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+#include "priv.h"
+#include "user.h"
+
+static const struct nvkm_dma_func
+gf119_dma = {
+ .class_new = gf119_dmaobj_new,
+};
+
+int
+gf119_dma_new(struct nvkm_device *device, int index, struct nvkm_dma **pdma)
+{
+ return nvkm_dma_new_(&gf119_dma, device, index, pdma);
+}
#include "priv.h"
#include "user.h"
-struct nvkm_oclass *
-nv04_dmaeng_oclass = &(struct nvkm_dma_impl) {
- .base.handle = NV_ENGINE(DMAOBJ, 0x04),
- .base.ofuncs = &(struct nvkm_ofuncs) {
- .ctor = _nvkm_dma_ctor,
- .dtor = _nvkm_dma_dtor,
- .init = _nvkm_dma_init,
- .fini = _nvkm_dma_fini,
- },
+static const struct nvkm_dma_func
+nv04_dma = {
.class_new = nv04_dmaobj_new,
-}.base;
+};
+
+int
+nv04_dma_new(struct nvkm_device *device, int index, struct nvkm_dma **pdma)
+{
+ return nvkm_dma_new_(&nv04_dma, device, index, pdma);
+}
#include "priv.h"
#include "user.h"
-struct nvkm_oclass *
-nv50_dmaeng_oclass = &(struct nvkm_dma_impl) {
- .base.handle = NV_ENGINE(DMAOBJ, 0x50),
- .base.ofuncs = &(struct nvkm_ofuncs) {
- .ctor = _nvkm_dma_ctor,
- .dtor = _nvkm_dma_dtor,
- .init = _nvkm_dma_init,
- .fini = _nvkm_dma_fini,
- },
+static const struct nvkm_dma_func
+nv50_dma = {
.class_new = nv50_dmaobj_new,
-}.base;
+};
+
+int
+nv50_dma_new(struct nvkm_device *device, int index, struct nvkm_dma **pdma)
+{
+ return nvkm_dma_new_(&nv50_dma, device, index, pdma);
+}
#define nvkm_dma(p) container_of((p), struct nvkm_dma, engine)
#include <engine/dma.h>
-int _nvkm_dma_ctor(struct nvkm_object *, struct nvkm_object *,
- struct nvkm_oclass *, void *, u32,
- struct nvkm_object **);
-#define _nvkm_dma_dtor _nvkm_engine_dtor
-#define _nvkm_dma_init _nvkm_engine_init
-#define _nvkm_dma_fini _nvkm_engine_fini
-
-struct nvkm_dma_impl {
- struct nvkm_oclass base;
- struct nvkm_oclass *sclass;
- int (*bind)(struct nvkm_dmaobj *, struct nvkm_gpuobj *,
+struct nvkm_dmaobj_func {
+ int (*bind)(struct nvkm_dmaobj *, struct nvkm_gpuobj *, int align,
struct nvkm_gpuobj **);
+};
+
+int nvkm_dma_new_(const struct nvkm_dma_func *, struct nvkm_device *,
+ int index, struct nvkm_dma **);
+
+struct nvkm_dma_func {
int (*class_new)(struct nvkm_dma *, const struct nvkm_oclass *,
void *data, u32 size, struct nvkm_dmaobj **);
};
struct nvkm_dmaobj **);
int gf100_dmaobj_new(struct nvkm_dma *, const struct nvkm_oclass *, void *, u32,
struct nvkm_dmaobj **);
-int gf110_dmaobj_new(struct nvkm_dma *, const struct nvkm_oclass *, void *, u32,
+int gf119_dmaobj_new(struct nvkm_dma *, const struct nvkm_oclass *, void *, u32,
struct nvkm_dmaobj **);
#endif
+++ /dev/null
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-#define gf110_dmaobj(p) container_of((p), struct gf110_dmaobj, base)
-#include "user.h"
-
-#include <core/client.h>
-#include <core/gpuobj.h>
-#include <subdev/fb.h>
-
-#include <nvif/class.h>
-#include <nvif/unpack.h>
-
-struct gf110_dmaobj {
- struct nvkm_dmaobj base;
- u32 flags0;
-};
-
-static int
-gf110_dmaobj_bind(struct nvkm_dmaobj *base, struct nvkm_gpuobj *parent,
- int align, struct nvkm_gpuobj **pgpuobj)
-{
- struct gf110_dmaobj *dmaobj = gf110_dmaobj(base);
- struct nvkm_device *device = dmaobj->base.dma->engine.subdev.device;
- int ret;
-
- ret = nvkm_gpuobj_new(device, 24, align, false, parent, pgpuobj);
- if (ret == 0) {
- nvkm_kmap(*pgpuobj);
- nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0);
- nvkm_wo32(*pgpuobj, 0x04, dmaobj->base.start >> 8);
- nvkm_wo32(*pgpuobj, 0x08, dmaobj->base.limit >> 8);
- nvkm_wo32(*pgpuobj, 0x0c, 0x00000000);
- nvkm_wo32(*pgpuobj, 0x10, 0x00000000);
- nvkm_wo32(*pgpuobj, 0x14, 0x00000000);
- nvkm_done(*pgpuobj);
- }
-
- return ret;
-}
-
-static const struct nvkm_dmaobj_func
-gf110_dmaobj_func = {
- .bind = gf110_dmaobj_bind,
-};
-
-int
-gf110_dmaobj_new(struct nvkm_dma *dma, const struct nvkm_oclass *oclass,
- void *data, u32 size, struct nvkm_dmaobj **pdmaobj)
-{
- union {
- struct gf110_dma_v0 v0;
- } *args;
- struct nvkm_object *parent = oclass->parent;
- struct gf110_dmaobj *dmaobj;
- u32 kind, page;
- int ret;
-
- if (!(dmaobj = kzalloc(sizeof(*dmaobj), GFP_KERNEL)))
- return -ENOMEM;
- *pdmaobj = &dmaobj->base;
-
- ret = nvkm_dmaobj_ctor(&gf110_dmaobj_func, dma, oclass,
- &data, &size, &dmaobj->base);
- if (ret)
- return ret;
-
- args = data;
-
- nvif_ioctl(parent, "create gf110 dma size %d\n", size);
- if (nvif_unpack(args->v0, 0, 0, false)) {
- nvif_ioctl(parent,
- "create gf100 dma vers %d page %d kind %02x\n",
- args->v0.version, args->v0.page, args->v0.kind);
- kind = args->v0.kind;
- page = args->v0.page;
- } else
- if (size == 0) {
- if (dmaobj->base.target != NV_MEM_TARGET_VM) {
- kind = GF110_DMA_V0_KIND_PITCH;
- page = GF110_DMA_V0_PAGE_SP;
- } else {
- kind = GF110_DMA_V0_KIND_VM;
- page = GF110_DMA_V0_PAGE_LP;
- }
- } else
- return ret;
-
- if (page > 1)
- return -EINVAL;
- dmaobj->flags0 = (kind << 20) | (page << 6);
-
- switch (dmaobj->base.target) {
- case NV_MEM_TARGET_VRAM:
- dmaobj->flags0 |= 0x00000009;
- break;
- case NV_MEM_TARGET_VM:
- case NV_MEM_TARGET_PCI:
- case NV_MEM_TARGET_PCI_NOSNOOP:
- /* XXX: don't currently know how to construct a real one
- * of these. we only use them to represent pushbufs
- * on these chipsets, and the classes that use them
- * deal with the target themselves.
- */
- break;
- default:
- return -EINVAL;
- }
-
- return 0;
-}
--- /dev/null
+/*
+ * Copyright 2012 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+#define gf119_dmaobj(p) container_of((p), struct gf119_dmaobj, base)
+#include "user.h"
+
+#include <core/client.h>
+#include <core/gpuobj.h>
+#include <subdev/fb.h>
+
+#include <nvif/class.h>
+#include <nvif/unpack.h>
+
+struct gf119_dmaobj {
+ struct nvkm_dmaobj base;
+ u32 flags0;
+};
+
+static int
+gf119_dmaobj_bind(struct nvkm_dmaobj *base, struct nvkm_gpuobj *parent,
+ int align, struct nvkm_gpuobj **pgpuobj)
+{
+ struct gf119_dmaobj *dmaobj = gf119_dmaobj(base);
+ struct nvkm_device *device = dmaobj->base.dma->engine.subdev.device;
+ int ret;
+
+ ret = nvkm_gpuobj_new(device, 24, align, false, parent, pgpuobj);
+ if (ret == 0) {
+ nvkm_kmap(*pgpuobj);
+ nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0);
+ nvkm_wo32(*pgpuobj, 0x04, dmaobj->base.start >> 8);
+ nvkm_wo32(*pgpuobj, 0x08, dmaobj->base.limit >> 8);
+ nvkm_wo32(*pgpuobj, 0x0c, 0x00000000);
+ nvkm_wo32(*pgpuobj, 0x10, 0x00000000);
+ nvkm_wo32(*pgpuobj, 0x14, 0x00000000);
+ nvkm_done(*pgpuobj);
+ }
+
+ return ret;
+}
+
+static const struct nvkm_dmaobj_func
+gf119_dmaobj_func = {
+ .bind = gf119_dmaobj_bind,
+};
+
+int
+gf119_dmaobj_new(struct nvkm_dma *dma, const struct nvkm_oclass *oclass,
+ void *data, u32 size, struct nvkm_dmaobj **pdmaobj)
+{
+ union {
+ struct gf119_dma_v0 v0;
+ } *args;
+ struct nvkm_object *parent = oclass->parent;
+ struct gf119_dmaobj *dmaobj;
+ u32 kind, page;
+ int ret;
+
+ if (!(dmaobj = kzalloc(sizeof(*dmaobj), GFP_KERNEL)))
+ return -ENOMEM;
+ *pdmaobj = &dmaobj->base;
+
+ ret = nvkm_dmaobj_ctor(&gf119_dmaobj_func, dma, oclass,
+ &data, &size, &dmaobj->base);
+ if (ret)
+ return ret;
+
+ args = data;
+
+ nvif_ioctl(parent, "create gf119 dma size %d\n", size);
+ if (nvif_unpack(args->v0, 0, 0, false)) {
+ nvif_ioctl(parent,
+ "create gf100 dma vers %d page %d kind %02x\n",
+ args->v0.version, args->v0.page, args->v0.kind);
+ kind = args->v0.kind;
+ page = args->v0.page;
+ } else
+ if (size == 0) {
+ if (dmaobj->base.target != NV_MEM_TARGET_VM) {
+ kind = GF119_DMA_V0_KIND_PITCH;
+ page = GF119_DMA_V0_PAGE_SP;
+ } else {
+ kind = GF119_DMA_V0_KIND_VM;
+ page = GF119_DMA_V0_PAGE_LP;
+ }
+ } else
+ return ret;
+
+ if (page > 1)
+ return -EINVAL;
+ dmaobj->flags0 = (kind << 20) | (page << 6);
+
+ switch (dmaobj->base.target) {
+ case NV_MEM_TARGET_VRAM:
+ dmaobj->flags0 |= 0x00000009;
+ break;
+ case NV_MEM_TARGET_VM:
+ case NV_MEM_TARGET_PCI:
+ case NV_MEM_TARGET_PCI_NOSNOOP:
+ /* XXX: don't currently know how to construct a real one
+ * of these. we only use them to represent pushbufs
+ * on these chipsets, and the classes that use them
+ * deal with the target themselves.
+ */
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
projects / GitHub / moto-9609 / android_kernel_motorola_exynos9610.git / commitdiff