drm/i915: add POWER_DOMAIN_PLLS

And get/put it when needed. The special thing about this commit is
that it will now return false in ibx_pch_dpll_get_hw_state() in case
the power domain is not enabled. This will fix some WARNs we have when
we run pm_rpm on SNB.

Testcase: igt/pm_rpm
Bugzilla:https://bugs.freedesktop.org/show_bug.cgi?id=80463
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index f22a81dba64adfb9c634b16646f63111351b1b38..2effe1a3781520bc222e3ac0910c0e2ade07ec82 100644 (file)
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2043,6 +2043,8 @@ static const char *power_domain_str(enum intel_display_power_domain domain)
                return "VGA";
        case POWER_DOMAIN_AUDIO:
                return "AUDIO";
+       case POWER_DOMAIN_PLLS:
+               return "PLLS";
        case POWER_DOMAIN_INIT:
                return "INIT";
        default:

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 26982d12039fccd0a6e135a7ddf60fea5b962ea0..479a9aa77ee3e68aeed58bb192265ebd1168afe8 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -129,6 +129,7 @@ enum intel_display_power_domain {
        POWER_DOMAIN_PORT_OTHER,
        POWER_DOMAIN_VGA,
        POWER_DOMAIN_AUDIO,
+       POWER_DOMAIN_PLLS,
        POWER_DOMAIN_INIT,
 
        POWER_DOMAIN_NUM,

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0874f3589722eb34e9abb49d0ae63226f0baef0f..d61c5e43fc19fe5ce4fe864cf9812944eafd605e 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1814,6 +1814,8 @@ static void intel_enable_shared_dpll(struct intel_crtc *crtc)
        }
        WARN_ON(pll->on);
 
+       intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
+
        DRM_DEBUG_KMS("enabling %s\n", pll->name);
        pll->enable(dev_priv, pll);
        pll->on = true;
@@ -1850,6 +1852,8 @@ static void intel_disable_shared_dpll(struct intel_crtc *crtc)
        DRM_DEBUG_KMS("disabling %s\n", pll->name);
        pll->disable(dev_priv, pll);
        pll->on = false;
+
+       intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
 }
 
 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
@@ -11302,6 +11306,9 @@ static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
 {
        uint32_t val;
 
+       if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS))
+               return false;
+
        val = I915_READ(PCH_DPLL(pll->id));
        hw_state->dpll = val;
        hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
@@ -12867,6 +12874,9 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
 
                DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
                              pll->name, pll->refcount, pll->on);
+
+               if (pll->refcount)
+                       intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
        }
 
        list_for_each_entry(encoder, &dev->mode_config.encoder_list,

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 19c5c26badae24cd279ca9370403ede65795cc90..55228df5cf23ec6e2273cd96400b9fb9f5e31043 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6346,6 +6346,7 @@ EXPORT_SYMBOL_GPL(i915_get_cdclk_freq);
        BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |          \
        BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |          \
        BIT(POWER_DOMAIN_PORT_CRT) |                    \
+       BIT(POWER_DOMAIN_PLLS) |                        \
        BIT(POWER_DOMAIN_INIT))
 #define HSW_DISPLAY_POWER_DOMAINS (                            \
        (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) |    \