drm/radeon/uvd: revert lower msg&fb buffer requirements on UVD3
authorChristian König <christian.koenig@amd.com>
Tue, 15 Oct 2013 18:12:03 +0000 (20:12 +0200)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 18 Oct 2013 20:16:16 +0000 (16:16 -0400)
This only seem to work for H.264 but not for VC-1 streams.

Need to investigate further why exactly.

This reverts commit 4b40e5921230beb1951f04d2b1b92c4c88fbad43.

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/radeon/radeon_cs.c
drivers/gpu/drm/radeon/radeon_uvd.c
drivers/gpu/drm/radeon/uvd_v1_0.c

index 66c222836631a4bc8dcd12b2f81f6e935218c566..80285e35bc6513fda3d5f5c975399a60feaab1e3 100644 (file)
@@ -85,9 +85,8 @@ static int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
                   VRAM, also but everything into VRAM on AGP cards to avoid
                   image corruptions */
                if (p->ring == R600_RING_TYPE_UVD_INDEX &&
-                   p->rdev->family < CHIP_PALM &&
                    (i == 0 || drm_pci_device_is_agp(p->rdev->ddev))) {
-
+                       /* TODO: is this still needed for NI+ ? */
                        p->relocs[i].lobj.domain =
                                RADEON_GEM_DOMAIN_VRAM;
 
index 4f2e73f79638f244c43558722128910404b2b04b..308eff5be1b420b74b18ccb1b1e0c89f4bd67f32 100644 (file)
@@ -476,7 +476,8 @@ static int radeon_uvd_cs_reloc(struct radeon_cs_parser *p,
                return -EINVAL;
        }
 
-       if (p->rdev->family < CHIP_PALM && (cmd == 0 || cmd == 0x3) &&
+       /* TODO: is this still necessary on NI+ ? */
+       if ((cmd == 0 || cmd == 0x3) &&
            (start >> 28) != (p->rdev->uvd.gpu_addr >> 28)) {
                DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
                          start, end);
index 3100fa9cb52f4ff5f0b924af6d146f1e06ae6908..7266805d9786c6fe9bfd38501f7ab674f7d05a73 100644 (file)
@@ -212,8 +212,8 @@ int uvd_v1_0_start(struct radeon_device *rdev)
        /* enable VCPU clock */
        WREG32(UVD_VCPU_CNTL,  1 << 9);
 
-       /* enable UMC and NC0 */
-       WREG32_P(UVD_LMI_CTRL2, 1 << 13, ~((1 << 8) | (1 << 13)));
+       /* enable UMC */
+       WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8));
 
        /* boot up the VCPU */
        WREG32(UVD_SOFT_RESET, 0);